US20050029580A1 - Method of fabricating flash memory device using sidewall process - Google Patents

Method of fabricating flash memory device using sidewall process Download PDF

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Publication number
US20050029580A1
US20050029580A1 US10/913,474 US91347404A US2005029580A1 US 20050029580 A1 US20050029580 A1 US 20050029580A1 US 91347404 A US91347404 A US 91347404A US 2005029580 A1 US2005029580 A1 US 2005029580A1
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layer
photoresist pattern
flash memory
substrate
polysilicon layer
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US10/913,474
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English (en)
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Jae Kim
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DB HiTek Co Ltd
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Anam Semiconductor Inc
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Assigned to ANAM SEMICONDUCTOR INC. reassignment ANAM SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, JAE YOUNG
Publication of US20050029580A1 publication Critical patent/US20050029580A1/en
Assigned to DONGBUANAM SEMICONDUCTOR INC. reassignment DONGBUANAM SEMICONDUCTOR INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: ANAM SEMICONDUCTOR INC.
Assigned to DONGBU ELECTRONICS CO., LTD. reassignment DONGBU ELECTRONICS CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: DONGBUANAM SEMICONDUCTOR INC.
Priority to US11/766,758 priority Critical patent/US7473601B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method of fabricating a floating gate of a flash memory cell using a sidewall process.
  • a flash memory cell having an EEPROM (electrically erasable programmable read-only memory) tunnel oxide structure comprises a floating gate which is formed over an active area of a semiconductor substrate and is electrically isolated from the semiconductor substrate by a gate oxide layer, where the substrate has device isolation structures formed thereon, a control gate which is formed over the floating gate and is electrically isolated from the floating gate by a dielectric layer, and a source/drain region which is formed at both sides of the floating gate on the semiconductor substrate.
  • the device isolation structure is made by a shallow trench isolation (STI) process or LOCOS (local oxidation of silicon) process.
  • Conventional technology forms a nitride capping layer as a hard mask by using bottom, anti-reflective coating and then performs a polysilicon etching process to fabricate a floating gate because of a difference in height between a field region and a moat region and bad reflection characteristics of a polysilicon layer.
  • the technology has difficulty in controlling a critical dimension (CD), and causes excessive polysilicon loss while etching the nitride capping layer.
  • the excessive polysilicon loss may cause a bad profile and a moat pit in a later polysilicon etching process.
  • FIG. 1 illustrates, in a cross-sectional view, the structure of a flash memory device according to the conventional technology.
  • the conventional flash memory device comprises at least one floating gate 1 formed over a substrate, a control gate 2 covering the floating gate 1 , and select gates 3 , which are positioned on both sides of the control gate 2 .
  • One control gate operates two transistors, which increases the size of a cell device.
  • U.S. Pat. No. 6,605,506 to Wu discloses a method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays.
  • the method uses four different spacer techniques to fabricate a scalable stacked-gate flash memory device.
  • the first spacer technique is used to form buffer-oxide spacers.
  • the second spacer technique is used to highly adjust the coupling ratio of the self-aligned floating gate using an STI structure.
  • the third spacer is used to define the gate length of a scalable stacked-gate structure.
  • the fourth spacer technique is used to form the sidewall spacers for self-aligned source/drain implant, self-aligned source/drain or common buried-source silicidation, and self-aligned contacts.
  • U.S. Pat. No. 6,501,125 to Kobayashi describes a method of manufacturing a semiconductor device which can solve the problem that a memory cell size determines a write/erase speed of memory cell transistors and can increase the write/erase speed without the reduction in the reliability of an insulating film between a control gate and a second-layer floating gate.
  • U.S. Pat. No. 6,261,903 to Chang et al. provides a integrated circuit device having a flash memory cell.
  • the flash memory cell has a tunnel dielectric layer overlying a surface of a semiconductor substrate and a floating gate layer defined overlying the tunnel dielectric layer.
  • the gate layer has an edge and a sidewall spacer extends along and on the edge. The combination of the sidewall spacer and the gate layer provide a surface for increasing gate coupling ratio.
  • U.S. Pat. No. 5,702,965 to Kim discloses a split-gate type flash memory cell with an insulation spacer of ONO (oxide-nitride-oxide) or ON (oxide-nitride) structure formed at the sidewalls of the floating gate.
  • ONO oxide-nitride-oxide
  • ON oxide-nitride
  • the present invention provides a method of fabricating a flash memory, comprising the steps of depositing and etching an insulating layer on a substrate having STI structures, depositing a first polysilicon layer over the insulating layer and the substrate, etching the first polysilicon layer to form floating gates, removing the insulating layer, forming a first photoresist pattern, performing a first ion implantation using the first photoresist pattern to form first source/drain regions in the substrate and adjacent to the floating gate, removing the first photoresist pattern, depositing an ONO layer on the resulting structure, depositing a second polysilicon layer over the ONO layer, etching the second polysilicon layer to form a control gate and at least one select gate, forming a second photoresist pattern, and performing a second ion implantation using the second photoresist pattern to form second source/drain regions in the substrate and adjacent to the select gate.
  • FIG. 1 illustrates, in a cross-sectional view, the structure of a conventional flash memory cell
  • FIG. 2 illustrates a cross-sectional view of a step of the process of fabricating a flash memory cell according to the present invention
  • FIG. 3 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention
  • FIG. 4 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention
  • FIG. 5 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention
  • FIG. 6 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention
  • FIG. 7 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention
  • FIG. 8 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention
  • FIG. 9 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • FIG. 10 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • FIG. 2 shows a cross-sectional view of a step of the process of fabricating a flash memory cell according to the present invention.
  • a gate oxide layer 10 is deposited over a substrate, where the substrate includes one or more shallow trench isolations (STIs, not shown) formed therein.
  • An insulating layer 11 is deposited over the gate oxide layer 10 . Then, some part of the insulating layer 11 is removed to form one or more trenches (only one trench is shown) therein so that a predetermined portion of the gate oxide layer 10 can be exposed.
  • the thickness of the insulating layer 11 is between 2000 ⁇ and 3000 ⁇ , preferably 2500 ⁇ .
  • FIG. 3 shows a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • a polysilicon layer 12 to make at least one floating gate is deposited over the insulating layer and in the trench.
  • the thickness of the deposited polysilicon layer 12 is between 4000 ⁇ and 6000 ⁇ , preferably 5000 ⁇ .
  • FIG. 4 shows a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • the polysilicon layer 12 is etched without a mask to form polysilicon sidewalls 14 on the side surfaces of the insulating layer 11 .
  • Polysilicon sidewalls 14 serve as floating gates.
  • the polysilicon layer is etched without a mask, some polysilicon in the trench still remains on the side surfaces of the insulating layer 11 after the polysilicon over the insulating layer is completely removed due to the topology difference of the deposited polysilicon layer. Therefore, the polysilicon sidewalls are formed on the side surfaces of the trench.
  • FIG. 5 shows a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • the insulating layer is removed to leave only the polysilicon sidewalls 14 .
  • the polysilicon sidewalls 14 are used as floating gates in the later process.
  • FIG. 6 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • a first photoresist pattern 15 is formed over the resulting substrate.
  • a first ion implantation 16 is then performed using the first photoresist pattern 15 as a mask to form source/drain regions 17 in the substrate and adjacent to the floating gates 14 .
  • the first photoresist pattern 15 is removed.
  • FIG. 7 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • an oxide-nitride-oxide (ONO) layer 18 is formed on the floating gates and the substrate.
  • the ONO layer 18 consists of a first oxide layer (not shown), a nitride layer (not shown), and a second oxide layer (not shown).
  • the thickness of the first oxide layer is between 50 ⁇ and 100 ⁇ , preferably 80 ⁇ .
  • the thickness of the nitride layer is between 50 ⁇ and 100 ⁇ , preferably 80 ⁇ .
  • the thickness of second oxide layer is between 300 ⁇ and 400 ⁇ , preferably 350 ⁇ .
  • FIG. 8 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • a second polysilicon layer is deposited over the ONO layer 18 .
  • the thickness of the deposited second polysilicon layer is between 1500 ⁇ and 2500 ⁇ , preferably 2000 ⁇ .
  • the second polysilicon layer is etched by using a predetermined mask pattern to form a control gate 19 and at least one select gate 20 .
  • FIG. 9 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • a second photoresist pattern 21 is formed over the resulting substrate.
  • a second ion implantation 23 is performed using the second photoresist pattern 21 as a mask to form source/drain regions 22 in the substrate and adjacent to the select gate.
  • FIG. 10 illustrates a cross-sectional view of a subsequent step of the process of fabricating a flash memory cell according to the present invention.
  • the second photoresist pattern 21 is removed and a flash memory device is completed.
  • the disclosed method can reduce the unit production cost because it does not need to use a nitride capping layer as a hard mask and can omit pattern processes by forming floating gates using a sidewall process.
  • this method can easily control the CD because it does not use the nitride capping layer as a hard mask for etching the floating gate, and prevents the formation of a moat pit while etching the floating gate.
  • the disclosed method can reduce the size of a flash memory device because it makes the floating gate using the sidewall process.

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US10/913,474 2003-08-08 2004-08-09 Method of fabricating flash memory device using sidewall process Abandoned US20050029580A1 (en)

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KR1020030054837A KR100559994B1 (ko) 2003-08-08 2003-08-08 측벽 방식을 이용한 플래시 메모리의 플로팅 게이트 형성방법
KR10-2003-0054837 2003-08-08

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070128799A1 (en) * 2005-02-04 2007-06-07 Powerchip Semiconductor Corp. Method of fabricating flash memory
CN101800226A (zh) * 2010-03-12 2010-08-11 上海宏力半导体制造有限公司 多晶硅存储器
CN102738058A (zh) * 2011-04-01 2012-10-17 无锡华润上华半导体有限公司 有源区的形成方法和sti沟槽的形成方法
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100827441B1 (ko) 2006-10-12 2008-05-06 삼성전자주식회사 비휘발성 메모리 소자 및 이의 제조 방법
KR100940666B1 (ko) * 2007-11-29 2010-02-05 주식회사 동부하이텍 플래시 메모리 소자 및 그 제조 방법

Citations (13)

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US5702965A (en) * 1995-06-24 1997-12-30 Hyundai Electronics Industries Co., Ltd. Flash memory cell and method of making the same
US6261903B1 (en) * 1998-05-14 2001-07-17 Mosel Vitelic, Inc. Floating gate method and device
US6284597B1 (en) * 1999-01-30 2001-09-04 United Microelectronics, Corp. Method of fabricating flash memory
US6420234B1 (en) * 1999-03-19 2002-07-16 Hyundai Electronics Industries Co., Ltd. Short channel length transistor and method of fabricating the same
US20020187609A1 (en) * 2001-06-07 2002-12-12 Samsung Electronics Co., Ltd. Non-volatile memory devices and methods of fabricating the same
US6501125B2 (en) * 1999-07-23 2002-12-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6605506B2 (en) * 2001-01-29 2003-08-12 Silicon-Based Technology Corp. Method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays
US6635533B1 (en) * 2003-03-27 2003-10-21 Powerchip Semiconductor Corp. Method of fabricating flash memory
US20040043638A1 (en) * 2002-08-30 2004-03-04 Fujitsu Amd Semiconductor Limited Semiconductor memory device and method for manufacturing semiconductor device
US6706592B2 (en) * 2002-05-14 2004-03-16 Silicon Storage Technology, Inc. Self aligned method of forming a semiconductor array of non-volatile memory cells
US6773993B2 (en) * 2001-04-03 2004-08-10 Nanya Technology Corporation Method for manufacturing a self-aligned split-gate flash memory cell
US20040166641A1 (en) * 2003-02-26 2004-08-26 Chih-Wei Hung Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate electrode
US6800525B2 (en) * 2002-08-07 2004-10-05 Samsung Electronics Co., Ltd. Method of manufacturing split gate flash memory device

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Publication number Priority date Publication date Assignee Title
US5702965A (en) * 1995-06-24 1997-12-30 Hyundai Electronics Industries Co., Ltd. Flash memory cell and method of making the same
US6261903B1 (en) * 1998-05-14 2001-07-17 Mosel Vitelic, Inc. Floating gate method and device
US6284597B1 (en) * 1999-01-30 2001-09-04 United Microelectronics, Corp. Method of fabricating flash memory
US6420234B1 (en) * 1999-03-19 2002-07-16 Hyundai Electronics Industries Co., Ltd. Short channel length transistor and method of fabricating the same
US6501125B2 (en) * 1999-07-23 2002-12-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6605506B2 (en) * 2001-01-29 2003-08-12 Silicon-Based Technology Corp. Method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays
US6773993B2 (en) * 2001-04-03 2004-08-10 Nanya Technology Corporation Method for manufacturing a self-aligned split-gate flash memory cell
US20020187609A1 (en) * 2001-06-07 2002-12-12 Samsung Electronics Co., Ltd. Non-volatile memory devices and methods of fabricating the same
US6706592B2 (en) * 2002-05-14 2004-03-16 Silicon Storage Technology, Inc. Self aligned method of forming a semiconductor array of non-volatile memory cells
US6800525B2 (en) * 2002-08-07 2004-10-05 Samsung Electronics Co., Ltd. Method of manufacturing split gate flash memory device
US20040043638A1 (en) * 2002-08-30 2004-03-04 Fujitsu Amd Semiconductor Limited Semiconductor memory device and method for manufacturing semiconductor device
US20040166641A1 (en) * 2003-02-26 2004-08-26 Chih-Wei Hung Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate electrode
US6635533B1 (en) * 2003-03-27 2003-10-21 Powerchip Semiconductor Corp. Method of fabricating flash memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070128799A1 (en) * 2005-02-04 2007-06-07 Powerchip Semiconductor Corp. Method of fabricating flash memory
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
CN101800226A (zh) * 2010-03-12 2010-08-11 上海宏力半导体制造有限公司 多晶硅存储器
CN102738058A (zh) * 2011-04-01 2012-10-17 无锡华润上华半导体有限公司 有源区的形成方法和sti沟槽的形成方法

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US7473601B2 (en) 2009-01-06
KR20050017121A (ko) 2005-02-22
JP2005064503A (ja) 2005-03-10
KR100559994B1 (ko) 2006-03-13
US20070243681A1 (en) 2007-10-18
JP4391354B2 (ja) 2009-12-24

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