US20030133066A1 - Liquid crystal display device and image display device - Google Patents

Liquid crystal display device and image display device Download PDF

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US20030133066A1
US20030133066A1 US10/310,915 US31091502A US2003133066A1 US 20030133066 A1 US20030133066 A1 US 20030133066A1 US 31091502 A US31091502 A US 31091502A US 2003133066 A1 US2003133066 A1 US 2003133066A1
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common electrode
liquid crystal
line
display device
lines
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Kikuo Ono
Takahiro Ochiai
Ryutaro Oke
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Hitachi Ltd
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Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OCHIAI, TAKAHIRO, OKE, RYUTARO, ONO, KIKUO
Publication of US20030133066A1 publication Critical patent/US20030133066A1/en
Priority to US11/503,977 priority Critical patent/US7304708B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to a image display debice and liquid crystal display device, and more particularly to an active matrix liquid crystal display device of a thin film transistor (hereinafter referred to as “TFT”) type or the like and a manufacturing method thereof.
  • TFT thin film transistor
  • An IPS mode liquid crystal display device has been known for adopting a method for realizing a wide viewing angle in Japanese Laid-open Patent Publication 36058/1995 and the like. Further, a method which arranges pixel electrodes and a common electrode on an organic resin via through holes formed in the resin has been proposed in Japanese Laid-open Patent Publication 230378/1997. Further, as active elements which perform switching, thin film transistors (hereinafter referred to as TFTs) using polysilicon have been known other than TFTs using amorphous silicon.
  • TFTs thin film transistors
  • the IPS type liquid crystal display device has a drawback that the numerical aperture is lower than that of a TN type liquid crystal display device and hence, the improvement of the numerical aperture has been a task of the IPS type liquid crystal display device heretofore. Further, to cope with a demand for video digital media including a large-sized liquid crystal television set, there has been a task that the high luminance must be realized and a further uniform display must be realized by reducing the influence of wiring delay in a liquid crystal display device having a large-sized screen.
  • the common electrode is formed of lines connected in the screen and wiring delay with respect to the resistivity of the electrode material and a load of the capacitance value with other lines causes a delay time which deteriorates the image quality.
  • the holding capacitance is the largest factor which causes the wiring delay. Accordingly, inventors of the present invention have found that the necessity to decrease the wiring delay time of the common electrode is particularly effective to enhance the image quality.
  • the inventors have also found that to reduce the number of driving ICs arranged outside by incorporating a circuit for driving drain lines into a TFT substrate made of glass or the like, it is necessary to decrease the wiring delay of the drain lines. Accordingly, the liquid crystal display device has to cope with a task that the drain line capacitance must be reduced.
  • a liquid crystal display device having a liquid crystal layer and a color filter layer sandwiched between a first transparent substrate and a second transparent substrate, having a plurality of gate lines, a plurality of drain lines which cross the plurality of gate lines in a matrix array and thin film transistors formed corresponding to respective crossing points of the gate lines and the drain lines on the first substrate, constituting pixel regions from regions each of which is surrounded by the neighboring gate lines and the neighboring drain lines, wherein each pixel includes at least a common electrode line, a common electrode and a pixel electrode,
  • the common electrode line comprising a first common electrode line which extends in the extending direction of the gate lines and a second common electrode line which extends in the extending direction of the drain lines in the pixel region, the first common electrode line and the second common electrode line are spaced apart from each other by way of a first insulating film, the first common electrode line and the second common electrode line are connected via an opening portion formed in the first insulating film, and a second insulating film is formed over the opening portion.
  • the first common electrode line and the second common electrode line include at least the second insulating film between the common electrode and the′ first and second common electrode lines in the pixel region, and the common electrode includes a portion which is arranged over the drain line by way of at least the second insulating film such that the portion has a width larger than a width of the drain line.
  • the liquid crystal display device comprising a first island-like electrode in the pixel region, an opening portion formed in a first insulating film which covers the first island-like electrode, a common electrode line which extends in the extending direction of the drain lines, wherein the first island-like electrode and the common electrode line are connected via the opening portion, the first island-like electrode constitutes a lower electrode, and a second island-like electrode which is connected to a source of the thin film transistor and is formed on the first insulating film constitutes an upper electrode thus forming holding capacitance.
  • the liquid crystal display device includes the common electrodes which are formed over an insulating film which covers the drain line over the first substrate, the common electrodes are connected in a matrix array between neighboring pixels, and the common electrodes include portions which have a width wider than a width of the drain lines over an insulating film which are applied onto the drain lines.
  • the insulating film of the holding capacitance is an inorganic insulating film which covers the gate line of the thin film transistor.
  • a liquid crystal display device having a liquid crystal layer and a color filter layer sandwiched between a first substrate and a second substrate, having a plurality of gate lines, a plurality of drain lines which cross the plurality of gate lines in a matrix array and thin film transistors formed corresponding to respective crossing points of the gate lines and the drain lines on the first substrate, constituting pixel regions from regions each of which is surrounded by the neighboring gate lines and the neighboring drain lines, wherein each pixel includes at least a common electrode line, a common electrode and a pixel electrode,
  • the liquid crystal display device comprising a common electrode line which extends in the extending direction of the drain line as the common electrode line, an island-like metal pixel electrode which is connected to a source of the thin film transistor, wherein the pixel region includes an opening portion which is divided into 6 or more opening portions between the neighboring drain lines, at least 1 divided opening portion is arranged between the island-like metal pixel electrode and one of the neighboring drain lines, at least 2 divided opening portions are arranged between the common electrode line and the other of the neighboring drain lines, and at least 3 divided opening portions are arranged between the island-like metal pixel electrode and the common electrode line.
  • a liquid crystal display device having a liquid crystal layer and a color filter layer sandwiched between a first substrate and a second substrate, having a plurality of gate lines, a plurality of drain lines which cross the plurality of gate lines in a matrix array and thin film transistors formed corresponding to respective crossing points of the gate lines and the drain lines on the first substrate, constituting pixel regions from regions each of which is surrounded by the neighboring gate lines and the neighboring drain lines, wherein each pixel includes at least a common electrode line, a common electrode and a pixel electrode,
  • the liquid crystal display device comprising a common electrode line which extends in the extending direction of the drain line as the common electrode line, an island-like metal pixel electrode which is connected to a source of the thin film transistor, wherein the pixel region includes an opening portion which is divided into 8 or more opening portions between the neighboring drain lines, at least 3 divided opening portions are arranged between the island-like metal pixel electrode and one of the neighboring drain lines, at least 2 divided opening portions are arranged between the common electrode line and the other of the neighboring drain lines, and at least 3 divided opening portions are arranged between the island-like metal pixel electrode and the common electrode line.
  • a liquid crystal display device having a liquid crystal layer and a color filter layer sandwiched between a first substrate and a second substrate, having a plurality of gate lines, a plurality of drain lines which cross the plurality of gate lines in a matrix array and thin film transistors formed corresponding to respective crossing points of the gate lines and the drain lines on the first substrate, constituting pixel regions from regions each of which is surrounded by the neighboring gate lines and the neighboring drain lines, wherein each pixel includes at least a common electrode line, a transparent common electrode and a transparent pixel electrode,
  • the transparent common electrode and the transparent pixel electrode are formed on a same layer above the drain lines
  • the liquid crystal display device includes a common electrode line which extends in the extending direction of the drain line as the common electrode line, a metal pixel electrode which is connected to a source of the thin film transistor, wherein the pixel region includes an opening portion which is divided into 6 or more opening portions between the neighboring drain lines, the metal pixel electrode is arranged below the transparent pixel electrode which is closest to one drain line of the neighboring drain lines, the common electrode line is arranged close to the other drain line of the neighboring drain lines and below the transparent common electrode which is not arranged on the other drain line, and at least 1 or more transparent common electrode or 1 or more transparent pixel electrodes are arranged between the metal pixel electrode and the common electrode line.
  • a liquid crystal display device having a liquid crystal layer and a color filter layer sandwiched between a first substrate and a second substrate, having a plurality of gate lines, a plurality of drain lines which cross the plurality of gate lines in a matrix array and thin film transistors formed corresponding to respective crossing points of the gate lines and the drain lines on the first substrate, constituting pixel regions from regions each of which is surrounded by the neighboring gate lines and the neighboring drain lines, wherein each pixel includes at least a common electrode line, a common electrode and a pixel electrode,
  • the liquid crystal display device comprising a metal pixel electrode which is arranged in a region sandwiched by the neighboring drain lines, a common electrode which extends in the extending direction of the drain line as the common electrode, and a distance between one of the neighboring drain lines and the metal pixel electrode, a distance between the metal pixel electrode and the common electrode and a distance between the common electrode and the other of the neighboring drain lines are set to approximately equal with respect to the number of division of the pixel region.
  • the approximately equal distances with respect to the number of division of the pixel region are set to 3+3+2 in the liquid crystal display device in which the number of division of the region between the neighboring drain signal lines is 8, are set to 3+3+4 in the liquid crystal display device in which the number of division of the region between the neighboring drain signal lines is 10, and are set to 5+4+3 in the liquid crystal display device in which the number of division of the region between the neighboring drain signal lines is 12.
  • a liquid crystal display device having a liquid crystal layer and a color filter layer sandwiched between a first transparent substrate and a second transparent substrate, having a plurality of gate lines, a plurality of drain lines which cross the plurality of gate lines in a matrix array and thin film transistors formed corresponding to respective crossing points of the gate lines and the drain lines on the first substrate, constituting pixel regions from regions each of which is surrounded by the neighboring gate lines and the neighboring drain lines, wherein each pixel includes at least a holding capacitance line and a pixel electrode,
  • an insulating film is formed over the gate line
  • the transparent common electrode is formed over the insulating film and has a region which covers the insulating film and has a width which is larger than a width of the gate line
  • the transparent electrode line having the width wider than the width of the gate line plays a role of a black matrix in the liquid crystal display device.
  • An image display device which is used as a liquid crystal television set is constituted using an active matrix type liquid crystal display device adopting either any one of the means (1) to (10) or any one of the means (12) to (18).
  • FIG. 1 is a plan view of an essential part of a pixel of a TFT liquid crystal display device according to one embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of an essential part of a pixel taken along a line 4 - 4 ′ in FIG. 1.
  • FIG. 7 is a cross-sectional view for explaining the manufacturing method of the TFT substrate of the TFT liquid crystal display device according to one embodiment of the present invention up to the completion of the third photolithography step.
  • FIG. 8 is a cross-sectional view for explaining the manufacturing method of the TFT substrate of the TFT liquid crystal display device according to one embodiment of the present invention up to the completion of the fourth photolithography step.
  • FIG. 9 is a cross-sectional view for explaining the manufacturing method of the TFT substrate of the TFT liquid crystal display device according to one embodiment of the present invention up to the completion of the fifth photolithography step.
  • FIG. 11 is an overall plan view showing a state in which a PCB board and a TAB are connected to the LCD cell.
  • FIG. 12 is a cross-sectional view of the TAB of the LCD cell and a neighborhood of a drain-side pull-out terminal portion.
  • FIG. 13 is a plan view expressing a schematic equivalent circuit of the TFT liquid crystal display device according to one embodiment of the present invention.
  • FIG. 15 is an explanatory view showing one example of the module constitution of the present invention.
  • FIG. 18 is a cross-sectional view of an essential part taken along a line 18 - 18 ′ in FIG. 17.
  • FIG. 19 is a plan view of a pixel of a TFT liquid crystal display device according to another embodiment of the present invention.
  • FIG. 21 is a plan view of a pixel of a TFT liquid crystal display device according to another embodiment of the present invention.
  • FIG. 24 is a plan view of a pixel of a TFT liquid crystal display device according to another embodiment of the present invention.
  • FIG. 25 is a cross-sectional view of an essential part taken along a line 25 - 25 ′ in FIG. 24.
  • FIG. 27 is a cross-sectional view of an essential part taken along a line 27 - 27 ′ in FIG. 26.
  • One of the features of this planar structure lies in a point that the lateral common electrode line CLMG and the vertical common electrode line CLMD are connected to each other via a fourth contact hole CNT 4 . Accordingly, when viewed from the screen region of the liquid crystal display device, there exists a state in which the common electrode lines having low resistance are connected in a mesh pattern so that wiring delay can be made extremely small.
  • These common electrode lines CLMG, CLMD which are made of metal play a role of mainly supplying the potential to the holding capacitance which is defined in an area region where the metal pixel electrode SPM and the lateral common electrode line CLMG are overlapped to each other in plane.
  • the vertical common electrode line CLMD by forming the vertical common electrode line CLMD on the same layer as the drain line DL, the common potential supplied from the vertical direction receives the influence from the gate line GL similar to that of the video signals.
  • the voltage written in the holding capacitance portion gives rise to a differential voltage between voltages and hence, it is possible to obtain an advantageous effect that the differential voltage works in the direction to cancel the influence of the gate lines GL. Accordingly, the reduction of the display irregularities and the reduction of the smear can be achieved. Further, as can be understood clearly from FIG.
  • the value becomes not more than one half compared to the liquid crystal capacitance of the TN type liquid crystal display device which forms the liquid crystal capacitance between electrodes formed over the major regions of surfaces of substrates which face each other.
  • various transparent conductors that is, ITO (Indium-Tin-Oxide), IZO (Indium-Zinc-Oxide), ITZO (Indium-Tin-Zinc-Oxide), SnO 2 , In 2 O 3 and the like can be used. Further, it is possible to obtain the high image quality by suppressing the luminance irregularities and the smear.
  • FIG. 2 is a cross-sectional view taken along a line 2 - 2 ′ in FIG. 1 and shows a portion which traverses one pixel region between the neighboring drain lines DL.
  • a background insulating film ULS which is constituted of a Si 3 N 4 film having a film thickness of 50 nm and a SiO 2 film having a film thickness of 120 nm is formed over an alkalifree TFT glass substrate GLS 1 having a strain point of approximately 670 degree centigrade.
  • the background insulating film ULS has a role of preventing the diffusion of impurities such as Na or the like from the TFT glass substrate GLS 1 .
  • a gate insulating film GI which is formed of SiO 2 is formed over the background insulating film ULS.
  • An interlayer insulating film ILI made of SiO 2 is formed such that the film ILI covers all of the above-mentioned parts or members.
  • the drain line DL formed of a three-layered metal film such as Ti/Al/Ti is formed over the interlayer insulating film ILI.
  • the metal pixel electrode SPM which is formed of the same material and by the same steps as the above-mentioned drain lines DL constitutes an electrode which supplies the pixel potential via the second contact hole CNT 2 of the TFT in FIG. 1.
  • the vertical common electrode line CLMD which is formed of the same material and by the same steps as the drain lines DL is formed in parallel with the drain lines DL and plays a role to supply the common potential to the holding capacitance.
  • the main transmitting regions are four regions consisting of (1) a region formed between the transparent common electrode line CLT over the drain line DL and the transparent pixel electrode SPT, (2) a region formed between the above-mentioned transparent pixel electrode SPT and the transparent common electrode line CLT extending upwardly and downwardly from the gate line GL in a plan view shown in FIG. 1 such that the transparent common electrode line CLT covers the vertical common electrode line CLMD, (3) a region formed between the above-mentioned transparent common electrode line CLT and the transparent pixel electrode SPT, and (4) a region arranged between the transparent pixel electrode SPT and the transparent common electrode line CLT arranged over the drain line DL.
  • the above-mentioned transparent pixel electrode SPT and the transparent common electrode line CLT constitute electrodes which drive the liquid crystal.
  • the vertical common electrode line CLMD has a feature that even when the width thereof is set to a minimum value which is decided by a process rule, the wiring delay can be made small and hence, there is no possibility that the numerical aperture is reduced.
  • the constitution that the vertical common electrode line CLMD is arranged below the transparent electrode line CLT which is indispensable in the driving of the liquid crystal thus preventing any further reduction of the numerical aperture also constitutes the feature of this embodiment.
  • the holding capacitance Cstg is formed in such a manner that, the lateral common electrode line CLMG is used as one electrode, an interlayer insulating film ILI is used as the insulating film and the metal pixel electrode SPM is used as the other electrode.
  • the holding capacitance Cstg is set to hold the potential during the image display period (holding period) which is determined by the liquid crystal capacitance with respect to a leak current which is increased by a pair of electrons and positive holes generated by irradiation of light by the backlight for display from the TFT glass substrate GLS 1 side to the polysilicon PSI of the TFT in FIG. 3. If this value can be set large, it is possible to hold the uniformity over the display screen in an extremely favorable state.
  • the polarizer In the state that there is no electric field or the lateral electric field is small, the polarizer is arranged in a crossed Nicols state and hence, the black display is exhibited.
  • the electric field When the electric field is applied, the transmission of the elliptically polarized light is generated and light is transmitted in response to the electric field. Accordingly, in the region where there is no electric field or the electric field is small, even when the transparent common electrode CLT is formed of a transparent electrode made of ITO, the backlight light emitted from the TFT glass substrate GLS 1 side is not transmitted and it is possible to obtain the favorable black state even when observed from the CF substrate GLS 2 which is an observer side.
  • the transparent common electrode CLT having the width thereof set to a value which is sufficiently large to cover at least the TFT including the low-temperature polysilicon PSI and the gate line GL, when viewed by human naked eyes, makes a profile of each pixel clear and performs a function similar to the BM to sharpen the image.
  • the transparent common electrode CLT having the width thereof set to a value which is sufficiently large to cover at least the TFT including the low-temperature polysilicon PSI and the gate line GL, when viewed by human naked eyes, makes a profile of each pixel clear and performs a function similar to the BM to sharpen the image.
  • the polarized state of light receives no influence during the transmission of light through the liquid crystal layer whereby the light is shielded by the polarizer POL formed on the CF substrate GLS 2 .
  • the low-temperature polysilicon is originally considered to appear in a state that the low-temperature polysilicon PSI is colored in red, the low-temperature polysilicon appears as the black matrix BM in a completely black display state.
  • the region WR assumes the black state irrespective of the state of the electric field.
  • a conventional black matrix BM is not formed on the CF substrate GLS 2 . Accordingly, in the IPS liquid crystal display device which adopts the structure of this embodiment, a step for forming the black matrix BM layer becomes unnecessary so that the manufacturing cost can be reduced. With respect to an external light, the above-mentioned transparent common electrode CLT plays a role of the black matrix BM which exhibits the extremely favorable small reflection. This is an advantageous effect obtained by using the transparent electrode as the light shielding layer. Further, since the light shielding layer is mounted on the substrate which faces the observation-side substrate in an opposed manner, the reflection is further reduced.
  • the background insulating film ULS is formed by laminating a Si 3 N 4 film and a SiO 2 film over the alkalifree TFT glass substrate GLS 1 , wherein the Si 3 N 4 film having a film thickness of 50 nm is formed by a plasma CVD method using a mixed gas of SiH 4 , NH 3 and N 2 and, thereafter, the SiO 2 film having a film thickness of 120 nm is formed by a plasma CVD method using a mixed gas of tetraethoxysilane and O 2 .
  • the holding capacitance Cstg is set to a large value
  • the wiring delay is increased and the luminance irregularities, the smear, the image retention or flickers are generated. Further, it is impossible to maintain the uniformity of display on the screen.
  • the lateral common electrode lines CLMG and the vertical common electrode lines CLMD which are made of metal material are connected in the screen in a matrix array thus reducing the resistance.
  • the holding capacitance is set to a further larger value whereby it is possible to provide the IPS type liquid crystal display device which can be used in the application which requires the high luminance such as the liquid crystal television set. That is, it is possible to provide the IPS type liquid crystal display device which exhibits the high backlight luminance and also exhibits the least luminance irregularities, the least smear, the least image retention and the least flickers in applications which require the holding capacitance of a large value.
  • the drain lines DL in the pixel region are connected to an external circuit IDC by way of a signal-side built-in circuit DDC on the TFT glass substrate GLS 1 .
  • three drain lines DL are connected to the outside by way of one drain terminal Td. Accordingly, compared to the liquid crystal display device adopting the amorphous silicon TFTs which does not incorporate the signal-side built-in circuit DDC on a glass substrate, the liquid crystal display device of this embodiment can reduce the number of drivers used in the external circuit IDC to one third and hence, the manufacturing cost can be reduced.
  • drain lines DL since the drain lines DL have to write the video voltage spending time three times larger than time necessary for the liquid crystal display device adopting the amorphous silicon TFTs. Accordingly, it is necessary to reduce the wiring resistance and the capacitance of the drain lines DL.
  • FIG. 25 shows the cross-sectional structure of the pixel. That is, FIG. 25 is a cross-sectional view showing the cross section traversing the neighboring drain lines DL and the holding capacitance electrode STM.
  • the holding capacitance electrode STM which is formed by the same step and is formed of the same material as the gate line GL is arranged on the gate insulating film GI between the drain lines DL.
  • the holding capacitance electrode STM is not extended below the drain line DL and hence, the capacitance is not formed.
  • the metal pixel electrode SPM extends from the second contact hole CNT 2 of the TFT formed of the low-temperature polysilicon PSI to the lateral common electrode line CLMG and supplies the pixel potential to the transparent pixel electrode SPT via the third contact hole CNT 3
  • the vertical common electrode line CLMD extends in the vertical direction substantially parallel to the drain lines DL and is connected to the lateral common electrode line CLMG via the fourth contact hole CLMD so as to supply the common potential to the lateral common electrode line CLMG.
  • distances between the vertical common electrode line CLMD and the right-side drain line DL are formed by four transmitting regions L 7 , L 8 , L 9 , L 10 and three transparent electrodes so that the probability of short-circuiting is reduced.
  • the distances between the left-side drain line DL and the metal pixel electrode SPM are formed by three transmitting regions L 1 , L 2 , L 3 and two transparent electrodes.
  • the distances between the metal pixel electrode SPM and the vertical common electrode line CLMD are formed by three transmitting regions L 4 , L 5 , L 6 and two transparent electrodes.

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Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050110930A1 (en) * 2003-11-26 2005-05-26 Lg.Philips Lcd Co., Ltd. Lower substrate, IPS mode liquid crystal display device and method for manufacturing the same
US20050140903A1 (en) * 2003-12-29 2005-06-30 Jong-Jin Park Substrate for a liquid crystal display
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CN1877429A (zh) 2006-12-13
CN100390624C (zh) 2008-05-28
CN1432855A (zh) 2003-07-30
JP2003207797A (ja) 2003-07-25
US7304708B2 (en) 2007-12-04
JP3881248B2 (ja) 2007-02-14
TW591282B (en) 2004-06-11
KR20030063131A (ko) 2003-07-28

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