US20020109166A1 - MFMOS/MFMS non-volatile memory transistors and method of making same - Google Patents

MFMOS/MFMS non-volatile memory transistors and method of making same Download PDF

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Publication number
US20020109166A1
US20020109166A1 US09/783,815 US78381501A US2002109166A1 US 20020109166 A1 US20020109166 A1 US 20020109166A1 US 78381501 A US78381501 A US 78381501A US 2002109166 A1 US2002109166 A1 US 2002109166A1
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United States
Prior art keywords
electrode
layer
depositing
region
memory transistor
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Abandoned
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US09/783,815
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English (en)
Inventor
Sheng Hsu
Fengyan Zhang
Tingkai Li
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Sharp Laboratories of America Inc
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Sharp Laboratories of America Inc
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Publication date
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Priority to US09/783,815 priority Critical patent/US20020109166A1/en
Assigned to SHARP LABORATORIES OF AMERICA, INC. reassignment SHARP LABORATORIES OF AMERICA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSU, SHENG TENG, LI, TINGKAI, ZHANG, FENGYAN
Priority to JP2002022530A priority patent/JP3907100B2/ja
Priority to KR1020020007479A priority patent/KR20020066997A/ko
Priority to EP02250984A priority patent/EP1231631A3/fr
Publication of US20020109166A1 publication Critical patent/US20020109166A1/en
Priority to US10/395,368 priority patent/US6762063B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties

Definitions

  • This invention relates to ferroelectric non-volatile integrated circuits, and specifically to a simplified fabrication technique which minimizes etching-induced ferroelectric stack damage.
  • a gate stack of a state-of-the-art ferroelectric (FE) memory transistor includes formation of a self-aligned FE stack, which includes deposition and etching of a top electrode material, the ferroelectric material, and a bottom electrode material.
  • a self-aligned FE stack which includes deposition and etching of a top electrode material, the ferroelectric material, and a bottom electrode material.
  • a method of fabricating a non-volatile ferroelectric memory transistor includes preparing a silicon substrate, including forming an active region on the substrate, implanting ions to form a source region and a drain region in the active region; forming a bottom electrode, depositing a ferroelectric layer over the active region; depositing a top electrode; depositing an insulating oxide layer over the active region; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode.
  • a non-volatile ferroelectric memory transistor includes a silicon substrate having an active region formed thereon; a source region and a drain region formed about a gate region in the active region; a bottom electrode formed above the gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; a top electrode formed on the ferroelectric layer, an insulating oxide layer, and a source electrode, a gate electrode and a drain electrode.
  • An object of the invention is to fabricate a ferroelectric non-volatile memory transistor which does not require gate stack etching
  • a further object of the invention is to fabricate a ferroelectric non-volatile memory transistor with minimal etching-induced damage.
  • Another object of the invention is to provide a fabrication process for a ferroelectric non-volatile memory transistor which is less complex than prior art techniques
  • FIGS. 1 - 4 depict steps in the fabrication process of the invention for a MFMOS FE non-volatile memory transistor.
  • FIG. 5 depicts a MFMOS FE non-volatile memory transistor constructed according to the invention
  • FIG. 6 depicts a MFMS FE non-volatile memory transistor constructed according to the invention.
  • the ferroelectric memory transistor of the invention may be formed on a silicon-on-insulator (SOI) substrate, such as Separation by IMplantation of Oxygen (SIMOX), or, it may be formed in a bulk silicon substrate.
  • SOI silicon-on-insulator
  • SIMOX Separation by IMplantation of Oxygen
  • silicon substrate refers to either a SOI substrate or to a bulk silicon substrate
  • the method of the invention overcomes the problems associated with etchings to form a self-aligned ferroelectric (FE) gate stack, and to also overcome the problems associated with etching-induced damage.
  • the fabrication method of the invention for a FE non-volatile memory transistor does not require etching of the FE material of the gate stack. Further, the top electrode and the bottom electrode do not need to be self-aligned.
  • the process sequence begins with a substrate 10 .
  • this may be a bulk or SOI substrate
  • STI shallow trench isolation
  • a gate region is oxidized, resulting in a gate oxide 14 , when fabricating a metal-ferro-metal oxide semiconductor (MFMOS) transistor.
  • MMOS metal-ferro-metal oxide semiconductor
  • a surface channel is formed when fabricating a metal-ferro-metal semiconductor (MFMS) transistor.
  • a bottom electrode 16 is deposited by CVD.
  • Bottom electrode 16 is preferably formed of Iridium, deposited to a thickness of between about 100 nm and 200 nm.
  • a layer of photoresist is applied to the desired areas, and bottom electrode 16 is etched, leaving sufficient bottom electrode material to corer a gate region.
  • Bottom electrode 16 has a predetermine area located within a peripheral boundary.
  • Arsenic ions are implanted at a dose of about 1 ⁇ 10 15 cm ⁇ 2 to 3 ⁇ 10 15 cm ⁇ 2 , and at an energy level of 20 keV to 40 keV, to form a source region 18 and a drain region 20 , which are located about a gate region, resulting in the structure depicted in FIG. 1.
  • An oxide layer 22 is formed by chemical vapor deposition (CVD) to a thickness of between about 200 nm and 400 nm, which is thicker than that of bottom electrode 16 Oxide layer 22 is thinned by chemical-mechanical polishing (CMP) to the upper surface of bottom electrode 16 , exposing the bottom electrode, as shown in FIG. 2.
  • CVD chemical vapor deposition
  • CMP chemical-mechanical polishing
  • a FE layer 24 is formed by CVD to a thickness of between about 100 nm and 400 nm.
  • the FE material may be any of the following: Pb(Zr, Ti)O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), Pb 5 Ge 3 O 11 , BaTiO 3 , or LiNbO 3 .
  • a top electrode 26 preferably formed of Platinum, is deposited by CVD to a thickness of between about 100 nm and 300 nm Photoresist is applied to specific regions of the structure, and the top electrode is etched, resulting in the structure shown in FIG. 3 Using the method of the invention, the selectivity of etching of top electrode 26 vs. FE layer 24 is not critical.
  • a barrier insulation layer 28 is deposited by CVD
  • a material such as TiO 2 is suitable for this layer, if required, and may be deposited to a thickness of between about 10 nm and 30 Barrier insulation layer 28 is provided to stop the diffusion of H 2 into the FE layer during annealing.
  • An oxide layer 30 is next deposited by CVD. Photoresist is applied prior to etching of contact holes in the insulating oxide. The structure is then metallized, and then etched, forming source electrode 32 , gate electrode 34 , and drain electrode 36 , resulting in the final MFMOS memory transistor structure shown at 38 in FIG. 5.
  • a surface channel n-layer 42 is formed in place of gate oxide layer 14 in FIGS. 1 - 5 .
  • Surface channel 42 is formed by implantation of Arsenic ions, at a dose of about 1 ⁇ 10 11 cm ⁇ 2 to 5 ⁇ 10 12 cm ⁇ 2 , and at an energy level of about 15 keV to 30 keV, resulting in a n-layer between p-well 12 and bottom electrode 16 .
  • top electrode 26 and bottom electrode 16 are not self-aligned.
  • the effective remnant charge is reduced by A OVERLAP /A BOT , where A OVERLAP is the area of overlap between top electrode 26 and bottom electrode 16 , and A BOT is the area of bottom electrode 16
  • the top electrode When the top electrode is larger than the bottom electrode, the bottom electrode is generally completely covered by the top electrode, and the effective remnant charge is the same as that of a self-aligned gate stack of the same size electrodes
  • the top electrode may also cover portions of source region 18 and/or drain region 20 , and the charge on the FE material will induce a charge on the source/drain junction. This induced charge makes the source region and/or drain region more conductive when the memory cell is programmed to a high conductive state and less conductive when the memory cell is programmed to a low conductive state Thus, this form of overlap does not produce any undesirable effects.
  • the contact via is located a short distance laterally away from bottom electrode 16 , and, because the etched area is relatively small, any plasma etching damage is minimal
  • the method of the invention eliminates the need to etch the FE layer for a self-aligning process The only etching which occurs to the FE layers if the formation of via holes, which is quite minimal, and not likely to result in any loss of non-volatile properties in the FE layer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
US09/783,815 2001-02-13 2001-02-13 MFMOS/MFMS non-volatile memory transistors and method of making same Abandoned US20020109166A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US09/783,815 US20020109166A1 (en) 2001-02-13 2001-02-13 MFMOS/MFMS non-volatile memory transistors and method of making same
JP2002022530A JP3907100B2 (ja) 2001-02-13 2002-01-30 Ｍｆｍｏｓ／ｍｆｍｓ不揮発性メモリトランジスタおよびその製造方法
KR1020020007479A KR20020066997A (ko) 2001-02-13 2002-02-08 Ｍｆｍｏｓ/ｍｆｍｓ 비휘발성 메모리 트랜지스터 및 그제조방법
EP02250984A EP1231631A3 (fr) 2001-02-13 2002-02-13 Transistors à mémoire non-volatile de type MFMOS/MFMS et procédé de fabrication
US10/395,368 US6762063B2 (en) 2001-02-13 2003-03-24 Method of fabricating non-volatile ferroelectric transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/783,815 US20020109166A1 (en) 2001-02-13 2001-02-13 MFMOS/MFMS non-volatile memory transistors and method of making same

Related Child Applications (1)

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US10/395,368 Division US6762063B2 (en) 2001-02-13 2003-03-24 Method of fabricating non-volatile ferroelectric transistors

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US20020109166A1 true US20020109166A1 (en) 2002-08-15

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US09/783,815 Abandoned US20020109166A1 (en) 2001-02-13 2001-02-13 MFMOS/MFMS non-volatile memory transistors and method of making same
US10/395,368 Expired - Lifetime US6762063B2 (en) 2001-02-13 2003-03-24 Method of fabricating non-volatile ferroelectric transistors

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US10/395,368 Expired - Lifetime US6762063B2 (en) 2001-02-13 2003-03-24 Method of fabricating non-volatile ferroelectric transistors

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US (2) US20020109166A1 (fr)
EP (1) EP1231631A3 (fr)
JP (1) JP3907100B2 (fr)
KR (1) KR20020066997A (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030201901A1 (en) * 2002-04-24 2003-10-30 Administrator Of The National Aeronautics And Space Administration Marking electrical wiring with condition indicators
US6838995B2 (en) 2002-04-24 2005-01-04 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method for anticipating problems with electrical wiring
CN110690289A (zh) * 2018-07-06 2020-01-14 三星电子株式会社 具有使用铁电材料的负电容的半导体器件

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4887566B2 (ja) * 2001-03-27 2012-02-29 独立行政法人産業技術総合研究所 半導体不揮発性記憶素子及びその製造方法
JP7038559B2 (ja) * 2018-02-05 2022-03-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384729A (en) * 1991-10-28 1995-01-24 Rohm Co., Ltd. Semiconductor storage device having ferroelectric film
JP3281839B2 (ja) * 1997-06-16 2002-05-13 三洋電機株式会社 誘電体メモリおよびその製造方法
US5907762A (en) * 1997-12-04 1999-05-25 Sharp Microelectronics Technology, Inc. Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing
US6011285A (en) * 1998-01-02 2000-01-04 Sharp Laboratories Of America, Inc. C-axis oriented thin film ferroelectric transistor memory cell and method of making the same
US6048740A (en) * 1998-11-05 2000-04-11 Sharp Laboratories Of America, Inc. Ferroelectric nonvolatile transistor and method of making same
US6303502B1 (en) * 2000-06-06 2001-10-16 Sharp Laboratories Of America, Inc. MOCVD metal oxide for one transistor memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030201901A1 (en) * 2002-04-24 2003-10-30 Administrator Of The National Aeronautics And Space Administration Marking electrical wiring with condition indicators
US6838995B2 (en) 2002-04-24 2005-01-04 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method for anticipating problems with electrical wiring
US6985083B2 (en) 2002-04-24 2006-01-10 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Marking electrical wiring with condition indicators
CN110690289A (zh) * 2018-07-06 2020-01-14 三星电子株式会社 具有使用铁电材料的负电容的半导体器件

Also Published As

Publication number Publication date
JP2002246570A (ja) 2002-08-30
EP1231631A3 (fr) 2004-12-29
US20030173600A1 (en) 2003-09-18
JP3907100B2 (ja) 2007-04-18
US6762063B2 (en) 2004-07-13
KR20020066997A (ko) 2002-08-21
EP1231631A2 (fr) 2002-08-14

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Owner name: SHARP LABORATORIES OF AMERICA, INC., WASHINGTON

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, SHENG TENG;ZHANG, FENGYAN;LI, TINGKAI;REEL/FRAME:011603/0833

Effective date: 20010213

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION