US11605504B2 - Multilayer electronic component and method for manufacturing multilayer electronic component - Google Patents

Multilayer electronic component and method for manufacturing multilayer electronic component Download PDF

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US11605504B2
US11605504B2 US16/909,122 US202016909122A US11605504B2 US 11605504 B2 US11605504 B2 US 11605504B2 US 202016909122 A US202016909122 A US 202016909122A US 11605504 B2 US11605504 B2 US 11605504B2
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internal electrode
electrode layer
sintered
multilayer body
multilayer
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US20200411248A1 (en
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Hideyuki Hashimoto
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/01—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
    • C04B35/46—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates
    • C04B35/462—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates
    • C04B35/465—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates
    • C04B35/468—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates based on barium titanates
    • C04B35/4682—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates based on barium titanates based on BaTiO3 perovskite phase
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/4505—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements characterised by the method of application
    • C04B41/4535—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements characterised by the method of application applied as a solution, emulsion, dispersion or suspension
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/80—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone of only ceramics
    • C04B41/81—Coating or impregnation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H01G4/0085—Fried electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/248—Terminals the terminals embracing or surrounding the capacitive element, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/224—Housing; Encapsulation

Definitions

  • the present disclosure relates to a multilayer electronic component and a method for manufacturing a multilayer electronic component.
  • Multilayer electronic components such as a multilayer ceramic capacitor applied to in-vehicle equipment are required to have high mechanical strength.
  • the mechanical strength as referred to herein refers to a load which leads to fracture in a flexural strength test described hereinafter (hereinafter also simply referred to as flexural strength).
  • Japanese Patent Laying-Open No. 2018-181940 discloses a technique for enhancing a multilayer ceramic capacitor in flexural strength by enhancing an internal electrode layer in strength.
  • the multilayer ceramic capacitor includes a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrode layers.
  • the multilayer body has an electrode facing portion in which the plurality of internal electrode layers face one another with a dielectric layer interposed therebetween, and an external peripheral portion surrounding the electrode facing portion. While it is believed that the external peripheral portion's strength has a significant effect on flexural strength, Japanese Patent Laying-Open No. 2018-181940 is silent on enhancing the external peripheral portion's strength.
  • An object of the present disclosure is to provide a multilayer electronic component having high flexural strength and a method for manufacturing the same.
  • a multilayer electronic component includes a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrode layers interposed between adjacent dielectric layers of the plurality of stacked dielectric layers.
  • the plurality of stacked dielectric layers each have a plurality of crystal grains including a first phase.
  • the multilayer body defines an electrode facing portion where the plurality of internal electrode layers and the plurality of stacked dielectric layers face each other in a stacking direction of the multilayer body, and defines an external peripheral portion surrounding the electrode facing portion.
  • a portion of the plurality of stacked dielectric layers in the external peripheral portion include, in at least some of grain boundaries of the plurality of crystal grains, a second phase including at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al, and P, and the second phase is a different compound from the first phase.
  • a method for manufacturing a multilayer electronic component comprises forming a pre-sintered internal electrode layer on a pre-sintered dielectric layer; stacking a plurality of the pre-sintered dielectric layers having the pre-sintered internal electrode layers formed thereon to obtain a pre-sintered multilayer body; immersing the pre-sintered multilayer body in a sol of a compound including at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al and P while the pre-sintered multilayer body is in a course of being sintered; and completing a sintering of the pre-sintered multilayer body after immersing the pre-sintered multilayer body in the sol to obtain a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrode layers interposed between adjacent dielectric layers of the plurality of stacked dielectric layers.
  • the multilayer electronic component according to the present disclosure can be enhanced in flexural strength. Further, the method for manufacturing a multilayer electronic component according to the present disclosure can manufacture a multilayer electronic component enhanced in flexural strength.
  • FIG. 1 is a cross section of a center portion in a lengthwise direction of a multilayer ceramic capacitor 100 which is a first embodiment of a multilayer electronic component according to the present disclosure.
  • FIG. 2 is a cross section of a center portion in a widthwise direction of multilayer ceramic capacitor 100 .
  • FIG. 3 is a cross section of a center portion in a lengthwise direction of a multilayer body 10 of multilayer ceramic capacitor 100 for illustrating a method for investigating a fine structure of an external peripheral portion 13 b of multilayer body 10 .
  • FIG. 4 a cross section of a center portion in a widthwise direction of multilayer body 10 .
  • FIG. 5 is a schematic diagram of an image observed with a scanning electron microscope (hereinafter also abbreviated as SEM) in a region R 1 of the center portion in the lengthwise direction of multilayer body 10 .
  • SEM scanning electron microscope
  • FIG. 6 is a schematic diagram of an SEM observed image in a region R 4 of the center portion in the lengthwise direction of multilayer body 10 .
  • FIG. 7 is a schematic diagram of an SEM observed image in a region R 7 of the center portion in the lengthwise direction of multilayer body 10 .
  • FIG. 8 is an enlarged schematic diagram of an SEM observed image in region R 4 of the center portion in the lengthwise direction of multilayer body 10 .
  • FIG. 9 is a schematic diagram of an SEM observed image in region R 4 of a center portion in a lengthwise direction of a multilayer body 10 A of a multilayer ceramic capacitor 100 A that is a second embodiment of the multilayer electronic component according to the present disclosure.
  • FIG. 10 is a schematic diagram of an SEM observed image in region R 4 of a center portion in a lengthwise direction of a multilayer body 10 B of a multilayer ceramic capacitor 100 B that is a third embodiment of the multilayer electronic component according to the present disclosure.
  • FIG. 11 is a cross section showing the step of obtaining a green multilayer body 10 g.
  • FIG. 12 is a cross section showing green multilayer body 10 g heated to be a pre-sintered multilayer body 10 p 1 which is in turn immersed in a Sn compound sol to impregnate an external peripheral portion 13 bp 1 and a portion of an electrode facing portion 13 ap 1 with a Sn compound S 1 .
  • FIG. 13 is a cross section showing the step of further heating pre-sintered multilayer body 10 p 1 to obtain a semi-sintered multilayer body 10 p 2 having a first internal electrode layer 12 a and a second internal electrode layer 12 b sintered.
  • FIG. 14 is a cross section showing the step of further heating semi-sintered multilayer body 10 p 2 to obtain multilayer body 10 sintered.
  • a multilayer ceramic capacitor 100 which is a first embodiment of a multilayer electronic component according to the present disclosure will be described with reference to FIGS. 1 to 6 .
  • FIGS. 1 and 2 are cross sections of multilayer ceramic capacitor 100 . More specifically, FIG. 1 is a cross section of a center portion in a lengthwise direction of multilayer ceramic capacitor 100 . FIG. 2 is a cross section of a center portion in a widthwise direction of multilayer ceramic capacitor 100 .
  • the plurality of dielectric layers 11 are layers composed of a dielectric material.
  • the plurality of dielectric layers 11 each have a plurality of crystal grains having as a component a first phase P 1 including a perovskite type compound composed with Ba included therein, as will be described hereinafter with reference to FIG. 8 , for example.
  • An example of the perovskite-type compound is for example a perovskite type compound with BaTiO 3 as a basic structure.
  • Internal electrode layer 12 includes an electrically conductive material.
  • the electrically conductive material for internal electrode layer 12 include at least one type of metal selected from Ni, Ni alloy, Cu, and Cu alloy, or an alloy including the metal.
  • Internal electrode layer 12 may further include dielectric particles called “co-material” as described below. The co-material is added to bring the sintering shrinkability of internal electrode layer 12 closer to the sintering shrinkability of dielectric layer 11 during sintering of multilayer body 10 , and a material therefor is not particularly limited as long as it provides the above-mentioned effect.
  • the plurality of dielectric layers 11 include an outer layer portion and an inner layer portion.
  • the outer layer portion includes a first outer layer portion D 1 provided between first major surface 14 a of multilayer body 10 and internal electrode layer 12 closest to first major surface 14 a , and a second outer layer portion D 2 provided between second major surface 14 b and internal electrode layer 12 closest to second major surface 14 b .
  • the inner layer portion is located in a region sandwiched between first outer layer portion D 1 and second outer layer portion D 2 .
  • the plurality of internal electrode layers 12 have a first internal electrode layer 12 a and a second internal electrode layer 12 b .
  • First internal electrode layer 12 a has a region facing second internal electrode layer 12 b with dielectric layer 11 therebetween, and a lead region reaching first end surface 16 a of multilayer body 10 .
  • Second internal electrode layer 12 b has a region facing first internal electrode layer 12 a with dielectric layer 11 therebetween, and a lead region reaching second end surface 16 b of multilayer body 10 .
  • first internal electrode layer 12 a and second internal electrode layer 12 b face each other with dielectric layer 11 interposed therebetween will be referred to as an electrode facing portion 13 a (a portion surrounded by a broken line in FIGS. 1 and 2 ).
  • Multilayer ceramic capacitor 100 can be said to be a plurality of capacitors including electrode facing portion 13 a and connected in parallel via a first external electrode 17 a and a second external electrode 17 b , which will be described hereinafter.
  • Multilayer body 10 includes a first margin portion M 1 provided between electrode facing portion 13 a and first side surface 15 a and a second margin portion M 2 provided between electrode facing portion 13 a and second side surface 15 b .
  • Multilayer body 10 has a third margin portion M 3 provided between electrode facing portion 13 a and first end surface 16 a , and a fourth margin portion M 4 provided between electrode facing portion 13 a and second end surface 16 b .
  • third margin portion M 3 the lead region of first internal electrode layer 12 a is disposed.
  • fourth margin portion M 4 the lead region of second internal electrode layer 12 b is disposed.
  • first and second outer layer portions D 1 and D 2 and first to fourth margin portions M 1 to M 4 surrounding electrode facing portion 13 a will be referred to as an external peripheral portion 13 b.
  • Multilayer ceramic capacitor 100 further includes first external electrode 17 a and second external electrode 17 b .
  • First external electrode 17 a is formed on first end surface 16 a so as to be electrically connected to first internal electrode layers 12 a .
  • First external electrode 17 a extends from first end surface 16 a to first major surface 14 a , second major surface 14 b , first side surface 15 a , and second side surface 15 b .
  • Second external electrode 17 b is formed on second end surface 16 b so as to be electrically connected to second internal electrode layer 12 b .
  • Second external electrode 17 b extends from second end surface 16 b to first major surface 14 a , second major surface 14 b , first side surface 15 a , and second side surface 15 b.
  • First external electrode 17 a and second external electrode 17 b have, for example, an underlying electrode layer and a plating layer disposed on the underlying electrode layer.
  • the underlying electrode layer includes, for example, at least one selected from a sintered material layer, a conductive resin layer, and a thin film metal layer.
  • the sintered material layer is formed by baking a paste including a glass powder and a metal powder, and includes a glass portion and a metal portion.
  • glass that constitutes the glass portion include B 2 O 3 —SiO 2 —BaO-based glass and the like.
  • metal that constitutes the metal portion include at least one type of metal selected from Ni, Cu, Ag and the like, or an alloy including the metal.
  • a plurality of sintered material layers having different components may be formed. In a manufacturing method described below, the sintered material layer may be fired simultaneously with multilayer body 10 , or may be baked after multilayer body 10 is fired.
  • the electrically conductive resin layer includes, for example, electrically conductive particles such as fine metal particles, and a resin portion.
  • electrically conductive particles such as fine metal particles
  • a resin portion examples of metal that constitutes the fine metal particles include at least one type of metal selected from Ni, Cu, Ag and the like, or an alloy including the metal.
  • resin that constitutes the resin portion include an epoxy-based thermosetting resin and the like.
  • a plurality of electrically conductive resin layers having different components may be formed.
  • the thin film metal layer is formed by, for example, a thin film forming method such as sputtering or vapor deposition, and is a layer having a thickness of not more than 1 ⁇ m and having fine metal particles deposited thereon.
  • metal that constitutes the thin film metal layer include at least one type of metal selected from Ni, Cu, Ag, Au and the like, or an alloy including the metal.
  • a plurality of thin film metal layers having different components may be formed.
  • Examples of metal that constitutes the plating layer include at least one type of metal selected from Ni, Cu, Ag, Au, Sn and the like, and an alloy including the metal.
  • a plurality of plating layers having different components may be formed.
  • the plating layer is preferably composed of a Ni-plating layer and a Sn-plating layer.
  • the Ni-plating layer can prevent the underlying electrode layer from being eroded by solder when the multilayer electronic component is mounted.
  • the Sn-plating layer has good wettability to solder including Sn, and can improve the mountability when the multilayer electronic component is mounted.
  • first external electrode 17 a and second external electrode 17 b may be a plating layer directly provided on multilayer body 10 and directly connected to the above-described corresponding internal electrode layers.
  • the plating layer preferably includes a first plating layer and a second plating layer provided on the first plating layer.
  • metal that constitutes the first plating layer and the second plating layer include at least one type of metal selected from Cu, Ni, Sn, Au, Ag, Pd, Zn and the like, or an alloy including the metal.
  • Cu having good bondability to Ni is preferably used as the metal that constitutes the first plating layer.
  • Sn or Au is used as the metal that constitutes internal electrode layers 12
  • a metal having solder barrier performance is preferably used as the metal that constitutes the first plating layer.
  • Ni having good wettability to solder is preferably used as the metal that constitutes the second plating layer.
  • dielectric layer 11 a dielectric material including BaTiO 3 as a basic structure of a perovskite type compound and having a variety of types of additives added thereto was used.
  • FIG. 3 is a cross section of a center portion in a lengthwise direction of multilayer body 10 for illustrating a sample for the SEM observation and WDX analysis.
  • FIG. 4 is a cross section of a center portion in a widthwise direction of multilayer body 10 for the same purpose.
  • Multilayer body 10 of multilayer ceramic capacitor 100 was obtained according to a manufacturing method described hereinafter. As shown in FIG. 3 , multilayer body 10 was polished on the side of second end surface 16 b to expose the center portion of multilayer body 10 in the lengthwise direction. Further, as shown in FIG. 4 , multilayer body 10 was polished on the side of second side surface 15 b to expose the center portion of multilayer body 10 in the widthwise direction.
  • a region R 1 of first outer layer portion D 1 located at a center portion in the widthwise direction and a region R 2 of second outer layer portion D 2 located at a center portion in the widthwise direction are set as observation regions. Furthermore, in the cross section of multilayer body 10 at the center portion in the lengthwise direction, a region including second margin portion M 2 and electrode facing portion 13 a is assumed, and the region is divided into three equal portions in the layer stacking direction, and in the figure, these portions were set as an upper region R 3 , a center region R 4 , and a lower region R 5 as observation regions.
  • a region including fourth margin portion M 4 and electrode facing portion 13 a is assumed and the region is divided into three equal portions in the layer stacking direction, and in the figure, an upper region R 6 , a center region R 7 , and a lower region R 8 are set as observation regions.
  • an observation through an SEM and an elemental analysis through a WDX accompanying the SEM were performed.
  • FIG. 5 is a schematic diagram of an SEM observed image in region R 1 of the center portion in the lengthwise direction of multilayer body 10 shown in FIGS. 3 and 4 .
  • FIG. 6 is a schematic diagram of an SEM observed image of region R 4 .
  • FIG. 7 is a schematic diagram of an SEM observed image of region R 7 . No significant difference was observed among the SEM observed images and the WDX analysis results in external peripheral portion 13 b at regions R 1 to R 8 . Therefore, a result obtained from region R 4 as will be described below (see FIG. 6 ) will be regarded as the fine structure of external peripheral portion 13 b in multilayer body 10 of multilayer ceramic capacitor 100 according to the present disclosure.
  • FIG. 8 is an enlarged schematic diagram of an SEM observed image in region R 4 of the center portion in the lengthwise direction of multilayer body 10 .
  • a second phase P 2 which is composed of a compound including at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al and P is present, and is different from a compound of the first phase P 1 .
  • the second phase refers to a state in which the compound including at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al and P is segregated.
  • Sn exhibits a role as a sintering aid and is significantly effective.
  • Second phase P 2 may be present so as to fill pore P in dielectric layer 11 .
  • Second phase P 2 is a compound having a low melting point and plays a role of a sintering aid when multilayer body 10 is fired. That is, second phase P 2 present in at least some of grain boundaries GB of the plurality of crystal grains G indicates that external peripheral portion 13 b is increasingly sintered. As a result, external peripheral portion 13 b can be enhanced in strength, and multilayer ceramic capacitor 100 can be enhanced in flexural strength.
  • a multilayer ceramic capacitor 100 A that is a second embodiment of the multilayer electronic component according to the present disclosure will be described with reference to FIG. 9 .
  • FIG. 9 is a schematic diagram of an SEM observed image in region R 4 of a center portion in a lengthwise direction of a multilayer body 10 A of multilayer ceramic capacitor 100 A.
  • Multilayer ceramic capacitor 100 A is different from multilayer ceramic capacitor 100 in terms of the state of layer DL in which Sn oxide is present and the state of an edge portion of internal electrode layer 12 .
  • the remainder in configuration is identical to that of multilayer ceramic capacitor 100 , and will not be described in detail.
  • layer DL in which second phase P 2 that is Sn oxide is present is generated so as to include external peripheral portion 13 b and a portion of electrode facing portion 13 a .
  • the Sn oxide enters vacancy V formed at an edge portion of internal electrode layer 12 .
  • the Sn oxide having entered vacancy V serves as a Sn filler F to fill at least a portion of vacancy V.
  • Sn is present locally in at least a portion of an edge portion of internal electrode layer 12 .
  • An element that is present locally in at least a portion of an edge portion of internal electrode layer 12 is only required to be at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al and P.
  • Multilayer ceramic capacitor 100 A also has the second phase P 2 playing a role of a sintering aid when multilayer body 10 is fired. As a result, as well as multilayer ceramic capacitor 100 , multilayer ceramic capacitor 100 A can have external peripheral portion 13 b enhanced in strength, and multilayer ceramic capacitor 100 A can be enhanced in flexural strength.
  • multilayer ceramic capacitor 100 A has at least a portion of vacancy V located at an edge portion of internal electrode layer 12 filled with filler F and generated at a time of sintering and shrinking. That is, vacancy V is reduced in volume. This can suppress infiltration of moisture at the time of barrel-finishing after firing and when a plating layer included in the external electrode is formed as described above. As a result, migration of metal included in each internal electrode layer can be suppressed, and multilayer ceramic capacitor 100 A can thus be enhanced in reliability.
  • Filler F may be a metal forming internal electrode layer 12 (e.g., Ni) alloyed with the above element or the like to be conductive. Further, filler F may be the above element at least partially reduced while fired in a reducing atmosphere to be conductive. In these cases, filler F can function as a portion of internal electrode layer 12 . As a result, each internal electrode layer can have an increased effective area and hence be enhanced in capacitance.
  • internal electrode layer 12 e.g., Ni
  • filler F may be the above element at least partially reduced while fired in a reducing atmosphere to be conductive. In these cases, filler F can function as a portion of internal electrode layer 12 .
  • each internal electrode layer can have an increased effective area and hence be enhanced in capacitance.
  • a multilayer ceramic capacitor 100 B that is the third embodiment of the multilayer electronic component according to the present disclosure will be described with reference to FIG. 10 .
  • FIG. 10 is a schematic diagram of an SEM observed image in region R 4 of a center portion in a lengthwise direction of a multilayer body 10 B of multilayer ceramic capacitor 100 B.
  • Multilayer ceramic capacitor 100 B is different from multilayer ceramic capacitor 100 in terms of the state of layer DL in which Sn oxide is present and the state of an edge portion of internal electrode layer 12 .
  • the remainder in configuration is identical to that of multilayer ceramic capacitor 100 , and thus will not be described in detail.
  • layer DL in which second phase P 2 that is Sn oxide is present is generated so as to include external peripheral portion 13 b and a portion of electrode facing portion 13 a .
  • the Sn oxide enters vacancy V formed at an edge portion of internal electrode layer 12 .
  • the Sn oxide having entered vacancy V serves as a Sn filler F to fill at least a portion of vacancy V.
  • the Sn oxide serves as a coating C to coat at least a portion of an interface of dielectric layer 11 and internal electrode layer 12 .
  • Sn is present locally at an edge portion of internal electrode layer 12 and at least a portion of an interface between the edge portion of internal electrode layer 12 and dielectric layer 11 .
  • An element present locally at the edge portion of internal electrode layer 12 is only required to be at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al and P.
  • Multilayer ceramic capacitor 100 B also has the second phase P 2 playing a role of a sintering aid when multilayer body 10 is fired. As a result, as well as multilayer ceramic capacitor 100 , multilayer ceramic capacitor 100 B can also have external peripheral portion 13 b enhanced in strength, and multilayer ceramic capacitor 100 B can be enhanced in flexural strength.
  • multilayer ceramic capacitor 100 B at least a portion of vacancy V located at an edge portion of internal electrode layer 12 and generated at a time of sintering and shrinking is filled with filler F. Furthermore, at least a portion of an interface of an edge portion of internal electrode layer 12 and dielectric layer 11 is coated with coating C. As well as multilayer ceramic capacitor 100 A, multilayer ceramic capacitor 100 B has vacancy V having a volume reduced by filler F. Furthermore, coating C can firmly adhere to at least a portion of the interface of the edge portion of internal electrode layer 12 and dielectric layer 11 .
  • This can further suppress infiltration of moisture at the time of barrel-finishing after firing and when a plating layer included in the external electrode is formed as described above for example. As a result, migration of metal included in each internal electrode layer can further be suppressed, and multilayer ceramic capacitor 100 B can thus further be increased in reliability.
  • Filler F and coating C may be a metal forming internal electrode layer 12 (e.g., Ni) alloyed with the above element or the like to be conductive. Further, filler F and coating C may be the above element at least partially reduced while fired in a reducing atmosphere to be conductive. In these cases, filler F and coating C can function as a portion of internal electrode layer 12 .
  • metal forming internal electrode layer 12 e.g., Ni
  • filler F and coating C may be the above element at least partially reduced while fired in a reducing atmosphere to be conductive. In these cases, filler F and coating C can function as a portion of internal electrode layer 12 .
  • Multilayer ceramic capacitor 100 according to the first embodiment and multilayer ceramic capacitor 100 A according to the second embodiment differ only in the degree of impregnation with a Sn compound described hereinafter, and can be manufactured in a similar method. Therefore, how multilayer ceramic capacitors 100 and 100 A are manufactured will not be described.
  • the method for manufacturing multilayer ceramic capacitor 100 B includes the following steps.
  • the method for manufacturing multilayer ceramic capacitor 100 B includes the step of obtaining a plurality of ceramic green sheets by using dielectric raw material powder.
  • the word “green” is an expression representing “pre-sintered” and will be used in that meaning hereinafter.
  • the dielectric raw material powder is, for example, BaTiO 3 powder having a surface with a variety of additives added thereto.
  • the ceramic green sheet includes a binder component other than the dielectric raw material powder.
  • the binder component is not particularly limited.
  • the above-described dielectric raw material powder can be produced, for example, by applying an organic compound of an additive to a surface of a BaTiO 3 powder, and calcinating and burning the organic component, to thereby bring about a state in which the additive is applied to the surface of the BaTiO 3 powder in an oxide state.
  • the dielectric raw material powder is not limited to the above-described state, and may be in a state of including the organic compound, or in a state of including the oxide and the organic compound.
  • the above-described BaTiO 3 powder in the dielectric raw material powder may be a BaTiO 3 solid solution powder.
  • the BaTiO 3 powder can be obtained, for example, by calcinating a mixture of a BaCO 3 powder and a TiO 2 powder.
  • a BaTiO 3 powder made by a known method such as an oxalic acid method or a hydrothermal synthesis method may be used.
  • the method for manufacturing multilayer ceramic capacitor 100 B includes the step of printing an internal electrode layer pattern on the ceramic green sheet.
  • An internal electrode layer paste for example includes metal powder including one of Ni, a Ni alloy, Cu and a Cu alloy, BaTiO 3 powder having a surface with a variety of additives added thereto (i.e., a co-material), and a binder component.
  • the co-material is not essential for the internal electrode layer.
  • the binder component is not particularly limited.
  • the step of printing the internal electrode layer pattern on the ceramic green sheet corresponds to the step of forming a pre-sintered internal electrode layer on a pre-sintered dielectric layer by using the internal electrode layer paste.
  • the co-material can be prepared for example as follows: An additive of an organic compound is provided to a surface of BaTiO 3 powder and calcinated to combust an organic component so that the additive is provided to the surface of the BaTiO 3 powder in the form of an oxide. Note, however, that this is not exclusive, and the co-material may be in a state with an organic compound included or may be in a state with an oxide and an organic compound included. Further, in the co-material, the BaTiO 3 powder may be BaTiO 3 solid solution powder. The co-material may be the same as or different from the dielectric raw material powder.
  • the method for manufacturing multilayer ceramic capacitor 100 B includes the step of stacking a plurality of ceramic green sheets including a ceramic green sheet with an internal electrode pattern formed thereon to obtain a green multilayer body. This step corresponds to the step of stacking a plurality of pre-sintered dielectric layers including a pre-sintered dielectric layer with a pre-sintered internal electrode layer formed thereon to obtain a pre-sintered multilayer body.
  • the method for manufacturing multilayer ceramic capacitor 100 B includes the step of sintering the green multilayer body to obtain a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrode layers.
  • the step of sintering includes a sol immersion step and a sintering step.
  • the pre-sintered multilayer body that is in the course of being sintered in a firing furnace and has a porous state is temporarily ejected from the firing furnace and immersed in a sol of a compound including at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al and P.
  • the sintering step is the step of sintering the pre-sintered multilayer body that has been immersed in the sol and is in the course of being sintered.
  • the pre-sintered multilayer body that is in the course of being sintered in the firing furnace and is has a porous state is heated for example to 800° C. in the firing furnace, held as appropriate, and then cooled to 50° C. or lower and ejected from the firing furnace. Note that the temperatures indicated above are only one example and not exclusive.
  • the ejected pre-sintered multilayer body is immersed in the sol of the compound.
  • the sol of the compound can be a dispersion of an oxide or hydroxide of each element in water.
  • the pre-sintered multilayer body with the above compound having entered the multilayer body through an external surface of the multilayer body through the sol immersion step is again introduced into the firing furnace, heated to a temperature allowing the dielectric raw material powder to be sufficiently sintered, and held as appropriate to obtain multilayer body 10 .
  • second phase P 2 different from first phase P 1 can be formed in at least some of grain boundaries GB of the plurality of crystal grains G including first phase P 1 in external peripheral portion 13 b.
  • the step of obtaining a green multilayer body through to the step of obtaining a sintered multilayer body will be described more specifically with reference to FIGS. 11 to 14 .
  • FIG. 11 is a cross section showing the step of obtaining green multilayer body 10 g .
  • Green multilayer body 10 g is obtained by stacking a ceramic green sheet 11 g , a first internal electrode layer pattern 12 ag , and a second internal electrode layer pattern 12 bg in layers.
  • Ceramic green sheet 11 g includes dielectric raw material powder 1 and a binder (not shown).
  • First internal electrode layer pattern 12 ag and second internal electrode layer pattern 12 bg include Ni-containing metal powder 2 and a binder (not shown) for example.
  • FIG. 12 is a cross section showing green multilayer body 10 g heated to be a pre-sintered multilayer body 10 p 1 which is in turn immersed in a Sn compound sol for example to impregnate external peripheral portion 13 bp 1 and a portion of electrode facing portion 13 ap 1 with an Sn compound S 1 .
  • Heating green multilayer body 10 g removes the binder included in ceramic green sheet 11 g , first internal electrode layer pattern 12 ag , and second internal electrode layer pattern 12 bg.
  • FIG. 13 is a cross section showing the step of further heating pre-sintered multilayer body 10 p 1 to obtain a semi-sintered multilayer body 10 p 2 having first and second internal electrode layers 12 a and 12 b sintered. Further heating pre-sintered multilayer body 10 p 1 from the temperature at which the binder is removed sinters and shrinks first internal electrode layer 12 a and second internal electrode layer 12 b and generates pores at an edge portion. Furthermore, pre-sintered dielectric layer 11 p 1 is further sintered to be a semi-sintered dielectric layer 11 p 2 .
  • semi-sintered multilayer body 10 p 2 includes an electrode facing portion 13 ap 2 and an external peripheral portion 13 bp 2 surrounding electrode facing portion 13 ap 2 .
  • Electrode facing portion 13 ap 2 is a portion having first internal electrode layer 12 a and second internal electrode layer 12 b facing each other with semi-sintered dielectric layer 11 p 2 interposed.
  • Sn compound S 1 becomes a Sn compound S 2 present locally in remaining pores or the like as pre-sintered multilayer body 10 p 1 is further sintered.
  • FIG. 14 is a cross section showing the step of further heating semi-sintered multilayer body 10 p 2 to obtain multilayer body 10 B sintered. Further heating semi-sintered multilayer body 10 p 2 allows semi-sintered dielectric layer 11 p 2 to be sufficiently sintered to be dielectric layer 11 .
  • Sn compound S 2 plays a role of a sintering aid in firing multilayer body 10 B, and finally comes to exist as second phase P 2 in at least some of grain boundaries GB of the plurality of crystal grains G present in external peripheral portion 13 b (see FIG. 8 ). Further, a portion of Sn compound S 2 comes to be present locally at an edge portion of internal electrode layer 12 as filler F and coating C (see FIG. 10 ).
  • Multilayer ceramic capacitor 100 B obtained in the above manufacturing method can have external peripheral portion 13 b enhanced in strength and hence flexural strength, as has been set forth above. Further, it can also suppress migration of metal included in each internal electrode layer, and hence be enhanced in reliability. Furthermore, when filler F and coating C are conductive, internal electrode layer 12 can have an increased effective area and multilayer ceramic capacitor 100 B can hence be increased in capacitance.
  • the step of immersing pre-sintered multilayer body 10 p 1 that is in the course of being sintered and has a porous state in a Sn compound sol preferably further includes the step of vacuuming an atmosphere surrounding the Sn compound sol after pre-sintered multilayer body 10 p 1 is immersed in the Sn compound sol.
  • Vacuuming the atmosphere surrounding the Sn compound sol allows the Sn compound functioning as a sintering aid to be efficiently introduced into pre-sintered multilayer body 10 p 1 .
  • the vacuuming can provide a degree of vacuum up to 0.1 MPa for example. Note, however, that the degree of vacuum is not limited thereto.
  • external peripheral portion 13 b can be enhanced in sinterability and hence strength.
  • multilayer ceramic capacitor 100 B can be enhanced in flexural strength.
  • filler F and coating C can be efficiently formed at an edge portion of internal electrode layer 12 .
  • internal electrode layer 12 can have a further increased effective area and multilayer ceramic capacitor 100 B can hence be further enhanced in capacitance.
  • the sol in which pre-sintered multilayer body 10 p 1 is immersed is not limited to a Sn compound sol, and a sol of a compound including at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al and P suffices.
  • Tables 1 to 3 show an exemplary experiment in which multilayer ceramic capacitor 100 B according to the third embodiment of the multilayer electronic component according to the present disclosure is compared with a multilayer ceramic capacitor without Sn added thereto in a process for manufacturing it.
  • Table 1 shows how a multilayer body varies in dimension when it is sintered, depending on whether Sn is added, that is, whether the multilayer body is impregnated with the Sn compound sol.
  • “vacuumed” means that after the pre-sintered multilayer body was immersed in the Sn compound sol, an atmosphere surrounding the Sn compound sol was vacuumed to 0.1 MPa.
  • the multilayer body is designed such that the internal electrode layer has a thickness of 0.5 ⁇ m, 100 internal electrode layers are stacked, the dielectric layer has a thickness of 1.0 and the multilayer body has a thickness of 0.3 mm after it is sintered.
  • Sn was added as follows: the pre-sintered multilayer body that had been heated to 800° C.
  • adding Sn enhances capacitance. Furthermore, vacuuming the atmosphere surrounding the Sn compound sol to 0.1 MPa enhances capacitance to a further increased degree. That is, efficiently introducing the Sn compound into the pre-sintered multilayer body can increase the internal electrode layer's effective area and thus enhance the multilayer ceramic capacitor in capacitance.
  • a multilayer ceramic capacitor was manufactured through the following procedure. Initially, a dielectric sheet and a conductive paste for an internal electrode were prepared.
  • the dielectric sheet and the conductive paste for the internal electrode include an organic binder and a solvent.
  • the dielectric sheet was prepared using dielectric raw material powder.
  • the dielectric raw material powder includes BaTiO 3 powder.
  • the electrically conductive paste for internal electrodes was printed on the dielectric sheet in a predetermined pattern and an internal electrode pattern was formed on the dielectric sheet.
  • the predetermined number of dielectric sheets for an outer layer having no internal electrode pattern printed thereon were stacked, and then, the dielectric sheet having the internal electrode pattern printed thereon was stacked on those dielectric sheets for an outer layer, and then, the predetermined number of dielectric sheets for an outer layer were stacked on that dielectric sheet.
  • a multilayer sheet was thus produced.
  • the multilayer sheet was pressed in a layer stacking direction by hydrostatic pressing, to thereby obtain a multilayer block.
  • the multilayer block was cut into a predetermined size, to thereby obtain a multilayer chip.
  • a multilayer ceramic capacitor was fabricated in the same manner as in exemplary experiment 1 except that before the step of sintering, a pre-sintered multilayer body heated to 800° C. and cooled to 50° C. in a firing furnace and ejected therefrom was immersed in a Sn compound sol.
  • the Sn compound sol was a dispersion of an oxide of Sn in water. The Sn oxide's concentration was set to 7% by weight.
  • Multilayer ceramic capacitors were fabricated in the same manner as in exemplary experiment 2 except that after the pre-sintered multilayer body was immersed in the Sn compound sol the atmosphere surrounding the Sn compound sol was vacuumed to 0.1 MPa. The atmosphere was vacuumed for periods of time as indicated in Table 4.
  • a sample was prepared from a multilayer ceramic capacitor through the above-described procedure, and region R 4 was observed with an SEM and subjected to an elemental analysis by a WDX accompanying the SEM. Based on a result thereof, a depth of impregnation with a compound including Sn (or a thickness of a layer in which the compound including Sn is present) was determined. A distance from the sample's side or end surface to a region where the above compound was no longer present was measured at lines dividing region R 4 into four equal portions in the layer stacking direction, and an average value thereof was determined as an impregnation depth. The impregnation depth was controlled by adjusting a period of time for immersion in the Sn compound sol.
  • Table 4 indicates average concentration, which is an average of a molar ratio of the above compound to 100 mol of Ti in a region of impregnation depth. Table 4 also shows a value of “impregnation depth/GAP amount.”
  • the GAP amount is a widthwise dimension of second margin portion M 2 , and it is 100 ⁇ m.
  • Flexural strength was measured as follows: a prepared multilayer ceramic capacitor was placed on a rigid plate and had an upper surface pressed at a center portion with a jig to measure a maximum stress that resulted in fracture, and the 20 multilayer ceramic capacitors' measurement values were averaged to calculate flexural strength. A result is shown in Table 4.
  • MTTF mean time to failure
  • HALT highly accelerated life test
  • Multilayer ceramic capacitors were fabricated in the same manner as in exemplary experiment 3 except that the Sn compound sol contained an oxide of Sn at concentrations indicated in Table 5.
  • An exemplary experiment 8 is the same as exemplary experiment 3.
  • the obtained multilayer ceramic capacitors were measured and evaluated in the same manner as in exemplary experiments 1 to 5. A result is shown in Table 5.
  • the concentration of the oxide of Sn is preferably less than 15% by weight, more preferably 10% by weight or less.
  • the multilayer ceramic capacitor has been described as an example of the multilayer electronic component, the invention according to the present disclosure is not limited thereto and is also applicable to, for example, a capacitor element formed within a multilayer board.
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Publication number Priority date Publication date Assignee Title
KR20220052164A (ko) * 2020-10-20 2022-04-27 삼성전기주식회사 적층형 전자 부품
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JP2022181539A (ja) * 2021-05-26 2022-12-08 Tdk株式会社 誘電体組成物および積層セラミック電子部品。
JP2023009744A (ja) * 2021-07-08 2023-01-20 株式会社村田製作所 積層セラミックコンデンサ

Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3920781A (en) 1971-04-02 1975-11-18 Sprague Electric Co Method of forming a ceramic dielectric body
JP2001143957A (ja) 1999-11-17 2001-05-25 Matsushita Electric Ind Co Ltd 積層セラミックコンデンサおよびその製造方法
JP2003142331A (ja) 2001-11-08 2003-05-16 Murata Mfg Co Ltd 積層セラミック電子部品
US20040233612A1 (en) * 2003-02-25 2004-11-25 Kyocera Corporation Multilayer ceramic capacitor and process for preparing the same
JP2005029423A (ja) 2003-07-14 2005-02-03 Tdk Corp 誘電体磁器組成物および電子部品
CN1634800A (zh) 2003-12-30 2005-07-06 广东风华高新科技集团有限公司 超低温烧结的陶瓷介质材料、其制备方法及所得的电容器
JP2008109120A (ja) 2006-09-27 2008-05-08 Kyocera Corp 積層セラミックコンデンサおよびその製法
KR20090011028A (ko) 2006-09-27 2009-01-30 쿄세라 코포레이션 적층 세라믹 콘덴서 및 그 제법
KR20090033099A (ko) 2007-09-28 2009-04-01 티디케이가부시기가이샤 유전체 자기 조성물 및 전자 부품
US20090219666A1 (en) * 2005-08-29 2009-09-03 Kyocera Corporation Dielectric Ceramic, Manufacturing Method Thereof, And Multilayer Ceramic Capacitor
US20100014214A1 (en) 2007-03-27 2010-01-21 Kyocera Corporation Dielectric ceramics and multilayer ceramic capacitor
CN101765894A (zh) 2007-07-27 2010-06-30 京瓷株式会社 叠层陶瓷电容器
JP2010171108A (ja) 2009-01-21 2010-08-05 Murata Mfg Co Ltd セラミック体の製造方法
KR20120080657A (ko) 2009-12-11 2012-07-17 가부시키가이샤 무라타 세이사쿠쇼 적층형 세라믹 전자부품
JP2013026507A (ja) 2011-07-22 2013-02-04 Kyocera Corp コンデンサおよびその製造方法
US20130094121A1 (en) 2011-10-14 2013-04-18 Tdk Corporation Laminated ceramic electronic parts
JP2013157460A (ja) 2012-01-30 2013-08-15 Tdk Corp 積層セラミックコンデンサ
JP2013229551A (ja) 2012-03-30 2013-11-07 Taiyo Yuden Co Ltd 積層セラミックコンデンサ
CN103553591A (zh) 2013-10-11 2014-02-05 山东国瓷功能材料股份有限公司 一种高温高绝缘性能多层陶瓷电容器用电介质陶瓷材料
US20160217924A1 (en) 2015-01-28 2016-07-28 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor
US20170365410A1 (en) 2016-06-20 2017-12-21 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor
US20180182557A1 (en) * 2016-12-28 2018-06-28 Samsung Electro-Mechanics Co., Ltd. Dielectric powder and multilayer capacitor using the same
US20180294098A1 (en) 2017-04-05 2018-10-11 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor and manufacturing method of multilayer ceramic capacitor
US20190051460A1 (en) * 2017-08-10 2019-02-14 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor and manufacturing method of multilayer ceramic capacitor
US20190198245A1 (en) * 2016-08-26 2019-06-27 Sabic Global Technologies B.V. Ceramic-polymer composite capacitors and manufacturing method
US20190233948A1 (en) 2018-01-29 2019-08-01 Academy Of Armored Forces Engineering Nickel-based coating composition for improving damping shock absorbing performance of cylinder head of diesel engine, method for producing the same and use thereof
US20190272954A1 (en) * 2018-03-02 2019-09-05 Taiyo Yuden Co., Ltd. Method of manufacturing multilayer ceramic capacitor and multilayer ceramic capacitor
US20200043665A1 (en) * 2018-08-01 2020-02-06 Samsung Electro-Mechanics Co., Ltd. Multilayer capacitor including liquid pocket
US20200090865A1 (en) * 2018-09-18 2020-03-19 Samsung Electro-Mechanics Co., Ltd. Conductive powder for internal electrode and capacitor component including the same
US20200258684A1 (en) 2019-02-13 2020-08-13 Samsung Electro-Mechanics Co., Ltd. Multi-layered ceramic capacitor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56162820A (en) * 1980-05-20 1981-12-15 Kiyoshi Okazaki Vapor bank layered laminated ceramic capacitor and method of manufacturing same
JP2797525B2 (ja) * 1989-09-29 1998-09-17 東レ株式会社 コンデンサ
JP3908458B2 (ja) * 1999-12-28 2007-04-25 Ｔｄｋ株式会社 誘電体磁器組成物の製造方法
WO2005083726A1 (en) * 2004-02-27 2005-09-09 Energenius, Inc. Thin film ferroelectric composites, method of making and capacitor comprising the same
JP4936850B2 (ja) * 2006-09-15 2012-05-23 太陽誘電株式会社 積層セラミックコンデンサ
JP4591537B2 (ja) * 2007-06-08 2010-12-01 株式会社村田製作所 積層セラミック電子部品
US20110013342A1 (en) * 2008-03-25 2011-01-20 Tokyo University Of Science Educational Foundation Administrative Organization Method for producing dielectric film and method for producing capacitor layer-forming material using the method for producing dielectric film
CN102893349B (zh) * 2010-05-21 2016-01-20 株式会社村田制作所 陶瓷体及其制造方法
KR101701049B1 (ko) * 2015-08-07 2017-01-31 삼성전기주식회사 적층 세라믹 전자부품 및 적층 세라믹 전자부품의 제조방법

Patent Citations (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3920781A (en) 1971-04-02 1975-11-18 Sprague Electric Co Method of forming a ceramic dielectric body
JP2001143957A (ja) 1999-11-17 2001-05-25 Matsushita Electric Ind Co Ltd 積層セラミックコンデンサおよびその製造方法
JP2003142331A (ja) 2001-11-08 2003-05-16 Murata Mfg Co Ltd 積層セラミック電子部品
US20040233612A1 (en) * 2003-02-25 2004-11-25 Kyocera Corporation Multilayer ceramic capacitor and process for preparing the same
JP2005029423A (ja) 2003-07-14 2005-02-03 Tdk Corp 誘電体磁器組成物および電子部品
CN1634800A (zh) 2003-12-30 2005-07-06 广东风华高新科技集团有限公司 超低温烧结的陶瓷介质材料、其制备方法及所得的电容器
US20090219666A1 (en) * 2005-08-29 2009-09-03 Kyocera Corporation Dielectric Ceramic, Manufacturing Method Thereof, And Multilayer Ceramic Capacitor
JP2008109120A (ja) 2006-09-27 2008-05-08 Kyocera Corp 積層セラミックコンデンサおよびその製法
KR20090011028A (ko) 2006-09-27 2009-01-30 쿄세라 코포레이션 적층 세라믹 콘덴서 및 그 제법
US20090225494A1 (en) 2006-09-27 2009-09-10 Kyocera Corporation Multilayer ceramic capacitor and method for production thereof
US20100014214A1 (en) 2007-03-27 2010-01-21 Kyocera Corporation Dielectric ceramics and multilayer ceramic capacitor
CN101765894A (zh) 2007-07-27 2010-06-30 京瓷株式会社 叠层陶瓷电容器
US20100188797A1 (en) 2007-07-27 2010-07-29 Kyocera Corporation Laminated ceramic capacitor
US20090086407A1 (en) 2007-09-28 2009-04-02 Tdk Corporation Dielectric ceramic composition and electronic device
KR20090033099A (ko) 2007-09-28 2009-04-01 티디케이가부시기가이샤 유전체 자기 조성물 및 전자 부품
JP2010171108A (ja) 2009-01-21 2010-08-05 Murata Mfg Co Ltd セラミック体の製造方法
KR20120080657A (ko) 2009-12-11 2012-07-17 가부시키가이샤 무라타 세이사쿠쇼 적층형 세라믹 전자부품
US20120250221A1 (en) 2009-12-11 2012-10-04 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component
JP2013026507A (ja) 2011-07-22 2013-02-04 Kyocera Corp コンデンサおよびその製造方法
KR20130040708A (ko) 2011-10-14 2013-04-24 티디케이가부시기가이샤 적층 세라믹 전자 부품
JP2013102123A (ja) 2011-10-14 2013-05-23 Tdk Corp 積層セラミック電子部品
US20130094121A1 (en) 2011-10-14 2013-04-18 Tdk Corporation Laminated ceramic electronic parts
JP2013157460A (ja) 2012-01-30 2013-08-15 Tdk Corp 積層セラミックコンデンサ
JP2013229551A (ja) 2012-03-30 2013-11-07 Taiyo Yuden Co Ltd 積層セラミックコンデンサ
US20150036264A1 (en) 2012-03-30 2015-02-05 Taiyo Yuden Co., Ltd. Multi-layer ceramic capacitor
US9287046B2 (en) 2012-03-30 2016-03-15 Taiyo Yuden Co., Ltd. Multi-layer ceramic capacitor
CN103553591A (zh) 2013-10-11 2014-02-05 山东国瓷功能材料股份有限公司 一种高温高绝缘性能多层陶瓷电容器用电介质陶瓷材料
US20160217924A1 (en) 2015-01-28 2016-07-28 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor
US10147546B2 (en) 2016-06-20 2018-12-04 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor with dielectric layers containing base metal
US20170365410A1 (en) 2016-06-20 2017-12-21 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor
JP2017228590A (ja) 2016-06-20 2017-12-28 太陽誘電株式会社 積層セラミックコンデンサ
US20190198245A1 (en) * 2016-08-26 2019-06-27 Sabic Global Technologies B.V. Ceramic-polymer composite capacitors and manufacturing method
US20180182557A1 (en) * 2016-12-28 2018-06-28 Samsung Electro-Mechanics Co., Ltd. Dielectric powder and multilayer capacitor using the same
JP2018181940A (ja) 2017-04-05 2018-11-15 太陽誘電株式会社 積層セラミックコンデンサおよびその製造方法
US20180294098A1 (en) 2017-04-05 2018-10-11 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor and manufacturing method of multilayer ceramic capacitor
US20190051460A1 (en) * 2017-08-10 2019-02-14 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor and manufacturing method of multilayer ceramic capacitor
US20190233948A1 (en) 2018-01-29 2019-08-01 Academy Of Armored Forces Engineering Nickel-based coating composition for improving damping shock absorbing performance of cylinder head of diesel engine, method for producing the same and use thereof
US20190272954A1 (en) * 2018-03-02 2019-09-05 Taiyo Yuden Co., Ltd. Method of manufacturing multilayer ceramic capacitor and multilayer ceramic capacitor
US20200043665A1 (en) * 2018-08-01 2020-02-06 Samsung Electro-Mechanics Co., Ltd. Multilayer capacitor including liquid pocket
US20200090865A1 (en) * 2018-09-18 2020-03-19 Samsung Electro-Mechanics Co., Ltd. Conductive powder for internal electrode and capacitor component including the same
US20200258684A1 (en) 2019-02-13 2020-08-13 Samsung Electro-Mechanics Co., Ltd. Multi-layered ceramic capacitor

Non-Patent Citations (15)

* Cited by examiner, † Cited by third party
Title
Barium Titanate_pp. 49 to 104_Sep. 2007.
BariumTitanate_pp. 49 to 104_1999.
Chinese Office Action issued for Chinese Application No. 202010583658.5, dated Aug. 4, 2021.
Definition-of-divalent-cation_Helmenstine_1 page_May 2019.
Dionot, J.; "Topology of Ferroelectric Polarization at the BaTiO3 (001) surface from ab initio calculations and electron microscopy-spectroscopy";pp. 1-154_Dec. 2015.
Gong, H. et al.; "Interfacial Diffusion Behavior In Ni—BaTiO3 MLCCs with Ultra-Thin Active Layers"; Electron. Mater. Lett., vol. 10, No. 2 (2014), pp. 417-421.
Korean Office Action issued for Korean Application No. 10-2020-0072713, dated Nov. 3, 2021.
Korean Office Action issued for Korean Application No. 10-2020-0075437, dated Nov. 24, 2021.
Korean Office Action issued for Korean Application No. 10-2020-0076266, dated Nov. 24, 2021.
Lee, Jae-Young et al.; "Coating BaTiO3 Nanolayers on Spherical Ni Powders for Multilayer Ceramic Capacitors" Advanced Materials, Oct. 2003, 15, No. 19, pp. 1655-1658.
Li, L, et al.; "Synthesis & Characterization of X8R BaTiO3-based dielectric ceramics by doping with NiNb2O6 nanopowders"; J Mater Sci: Mater Electron (2015) 26: pp. 9522-9528.
Oyama, T et al.; "Trapping of oxygen vacancy at grain boundary and its correlation with local atomic configuration and resultant excess energy in barium titanate: A systematic computational analysis"; Physical Review B 82, (2010), pp. 134107-1 to 134107-10.
Rare Earth Elements Ionic Radius_Shannon_p. 1_1976.
Structure & Dielectric Properties of Perovskite BaTiO3_Hsiao-Lin_pp. 1-15_Dec. 2002.
Wu, Wanghua et al.; "Thermally stimulated depolarization current study on barium titanate single crystals"; AIP Advances, 8, 045005-1 to 045005-6, Apr. 2018.

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