US11276649B2 - Devices and methods having magnetic shielding layer - Google Patents

Devices and methods having magnetic shielding layer Download PDF

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Publication number
US11276649B2
US11276649B2 US16/711,152 US201916711152A US11276649B2 US 11276649 B2 US11276649 B2 US 11276649B2 US 201916711152 A US201916711152 A US 201916711152A US 11276649 B2 US11276649 B2 US 11276649B2
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shielding layer
magnetic shielding
semiconductor
semiconductor chip
housing
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US20200411449A1 (en
Inventor
Harry-Hak-Lay Chuang
Tien-Wei Chiang
Chia-Hsiang Chen
Meng-Chun Shih
Ching-Huang Wang
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US16/711,152 priority Critical patent/US11276649B2/en
Priority to DE102019135181.2A priority patent/DE102019135181A1/de
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WANG, CHING-HUANG, CHEN, CHIA-HSIANG, CHIANG, TIEN-WEI, CHUANG, HARRY-HAK-LAY, SHIH, MENG-CHUN
Priority to KR1020200031921A priority patent/KR102378232B1/ko
Priority to TW111124385A priority patent/TWI830269B/zh
Priority to TW109121687A priority patent/TWI774013B/zh
Priority to CN202010598072.6A priority patent/CN112151668A/zh
Publication of US20200411449A1 publication Critical patent/US20200411449A1/en
Publication of US11276649B2 publication Critical patent/US11276649B2/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0073—Shielding materials
    • H05K9/0075—Magnetic shielding materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L43/02—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Definitions

  • an external magnetic field can cause an operation window shift or storage data errors in magnetic sensitive chips or devices, which can result in reading or writing failures.
  • FIG. 1A is a cross-sectional view schematically illustrating a device having a magnetic shielding layer, in accordance with some embodiments.
  • FIG. 1B is a top plan view schematically illustrating relative positioning of the semiconductor chip and the magnetic shielding layer of the device shown in FIG. 1A , in accordance with some embodiments.
  • FIG. 2A is a cross-sectional view illustrating a magnetic shielding layer having a tri-layer structure, in accordance with some embodiments.
  • FIG. 2B is a cross-sectional view illustrating a magnetic shielding layer having a multi-layer structure, in accordance with some embodiments.
  • FIG. 3 is a graph illustrating the variance in magnetic flux density when the magnetic permeability of the magnetic shielding layer is varied, in accordance with some embodiments.
  • FIG. 4 is a cross-sectional view schematically illustrating an electronic device having a magnetic shielding layer, in accordance with some embodiments.
  • FIGS. 5 through 10 are cross-sectional views schematically illustrating electronic devices having magnetic shielding layers disposed in various different positions or arrangements, in accordance with some embodiments.
  • FIG. 11 is a graph illustrating experimental results of bit error rates due to a magnetic field for an unshielded device and for a device including a magnetic shielding layer, in accordance with some embodiments.
  • FIG. 12 is a flowchart illustrating a method of manufacturing an electronic device having a magnetic shielding layer, in accordance with some embodiments.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • This application relates to devices, such as a semiconductor device, chip, or package, having a magnetic shielding layer and methods for forming such devices.
  • the present disclosure provides devices and methods in which a magnetic shielding layer is provided to protect electrical circuitry, such as a semiconductor chip, from damage due to magnetic fields.
  • the magnetic shielding layer may be provided in particular spatial arrangements with respect to the semiconductor chip, and the magnetic shielding layer may reduce interference at the semiconductor chip caused by an external magnetic field.
  • FIG. 1A is a cross-sectional view schematically illustrating a device 10 , in accordance with one or more embodiments of the present disclosure.
  • the device 10 includes a semiconductor device package 12 and a substrate 14 .
  • the semiconductor device package 12 includes at least one semiconductor chip 16 .
  • the semiconductor chip 16 may be or include any electrical circuitry, components, features or the like which may be formed on or in a semiconductor material, such as a monocrystalline silicon (Si), amorphous Si, gallium arsenide (GaAs), or any other semiconductor material or semiconductor substrate.
  • the semiconductor chip 16 is a magnetic sensitive chip that is sensitive to magnetic fields.
  • the semiconductor chip 16 includes one or more electrical circuitry, components, features or the like which may be operationally affected by magnetic fields, such as may exist when a magnetic is brought into close proximity of the device 10 .
  • the semiconductor chip 16 is a magnetic sensitive memory chip, such as a magnetoresistive random-access memory (MRAM) chip.
  • MRAM magnetoresistive random-access memory
  • data in MRAM is stored by magnetic storage elements as opposed to storage as electric charge or current flows.
  • the magnetic storage elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer.
  • One of the two plates may be a permanent magnet set to a particular polarity, while the other plate may have a variable magnetization which can be changed based on application of an external field to store data. Due to the use of magnetic storage elements in an MRAM chip, such MRAM chips are particularly susceptible to unintended effects due to the presence of an external magnetic field caused, for example, by a magnetic being brought into proximity of the MRAM chip.
  • the semiconductor chip 16 is disposed within the semiconductor device package 12 .
  • the semiconductor chip 16 may be encapsulated within the semiconductor device package 12 by an encapsulant 18 .
  • the encapsulant 18 may be any encapsulant material suitable for encapsulating the semiconductor chip 16 , and optionally additional components, within the semiconductor device package 12 .
  • the encapsulant 18 may be an epoxy mold compound (EPC).
  • the encapsulant 18 may be formed of an electrically insulating material or a thermally insulating material.
  • the substrate 14 may be any substrate suitable for supporting the semiconductor device package 12 .
  • the semiconductor device package 12 is mechanically coupled to the substrate 14 .
  • the substrate 14 is electrically coupled to the semiconductor device package 12 , e.g., to the semiconductor chip 16 included within the semiconductor device package 12 .
  • the substrate 14 is a printed circuit board (PCB) having one or more electrical contacts or leads (not shown) that electrically couple the substrate to one or more corresponding electrical contacts or leads (not shown) of the semiconductor device package 12 .
  • the substrate 14 may be electrically coupled to additional electrical devices, packages or the like, which in some embodiments, may be electrically coupled to the semiconductor device package 12 via the substrate 14 .
  • the semiconductor device package 12 may be any type of semiconductor device package, including, for example, integrated fan out (InFO) packages, chip-on-wafer-on-substrate (CoWoS) packages, wire bond packages, ball grid array packages, flip chip packages, or any other type of semiconductor device package.
  • InFO integrated fan out
  • CoWoS chip-on-wafer-on-substrate
  • wire bond packages ball grid array packages, flip chip packages, or any other type of semiconductor device package.
  • a magnetic shielding layer 20 is disposed proximate to the semiconductor chip 16 .
  • the magnetic shielding layer 20 is attached to the semiconductor device package 12 .
  • the magnetic shielding layer 20 may be attached to a surface (e.g., an upper surface) of the semiconductor device package 12 , as shown in FIG. 1A .
  • the magnetic shielding layer 20 may be formed as a part of the semiconductor device package 12 .
  • the magnetic shielding layer 20 may be formed at least partially within the semiconductor device package 12 , such as at least partially embedded in or otherwise surrounded by the encapsulant 18 .
  • the magnetic shielding layer 20 may be attached to the encapsulant 18 by the encapsulant 18 itself, e.g., the encapsulant 18 may secure and hold the magnetic shielding layer 20 in a desired position. In other embodiments, the magnetic shielding layer 20 may be attached to the encapsulant 18 by an adhesive material or the like.
  • the magnetic shielding layer 20 serves to shield the semiconductor chip 16 from magnetic interference or the like, for example, as may be caused by a magnet brought into proximity of the device 10 . More particularly, in some embodiments, the magnetic shielding layer 20 serves to redirect magnetic flux (e.g., from a magnet or magnetic structure positioned near the device 10 ) and significantly reduce magnetic interference on magnetic sensitive devices, such as the semiconductor chip 16 .
  • the device 10 may include a plurality of magnetic shielding layers 20 .
  • magnetic shielding layers 20 may be provided on multiple surfaces of the semiconductor device package 12 , which provides enhanced magnetic shielding of the semiconductor chip 16 from various different directions.
  • FIG. 1B is a top plan view schematically illustrating relative positioning of the semiconductor chip 16 and the magnetic shielding layer 20 .
  • the magnetic shielding layer 20 completely overlaps the semiconductor chip 16 .
  • the magnetic shielding layer 20 may have an area (e.g., a surface area or an area at an upper surface of the magnetic shielding layer 20 ) that is greater than an area of the semiconductor chip 16 (e.g., a surface area or an are at an upper surface of the semiconductor chip 16 ).
  • a width W 1 of the magnetic shielding layer 20 may be greater than a width W 2 of the semiconductor chip 16 .
  • a length L 1 of the magnetic shielding layer 20 may be greater than a length L 2 of the semiconductor chip 16 .
  • portions of the magnetic shielding layer 20 may extend beyond an outer periphery of the semiconductor chip 16 , as shown in FIG. 1B .
  • the magnetic shielding layer 20 may extend laterally outward beyond one or more sides of the semiconductor chip 16 , and in some embodiments, the magnetic shielding layer 20 may extend laterally outward beyond each of four sides of the semiconductor chip 16 , as shown.
  • the magnetic shielding layer 20 extends beyond the outer periphery of the semiconductor chip 16 by a distance equal to or greater than 1 mm. In some embodiments, the magnetic shielding layer 20 extends between about 1 mm to about 300 mm beyond the outer periphery of the semiconductor chip 16 , as indicated by the arrows 22 .
  • the distance at which the magnetic shielding layer 20 extends beyond the outer periphery of the semiconductor chip 16 may be selected as desired to provide desired magnetic shielding effects. For example, by increasing the distance at which the magnetic shielding layer 20 extends beyond the outer periphery of the semiconductor chip 16 , the magnetic shielding effect that is provided by the magnetic shielding layer 20 may be increased. This may be true up to some practical limit, beyond which further increasing the distance of extension of the magnetic shielding layer 20 does not provide additional increases in the magnetic shielding effect.
  • the magnetic shielding layer 20 may be formed of any material suitable to redirect magnetic flux and reduce magnetic interference on magnetic sensitive devices (e.g., the semiconductor chip 16 ).
  • the magnetic shielding layer 20 includes a first material (e.g., a magnetic material) including at least one of: iron (Fe), cobalt (Co), nickel (Ni), NiFe, CoFe, or any combination thereof.
  • the magnetic shielding layer 20 may further include a second material (e.g., a doping material) including at least one of: carbon (C), molybdenum (Mo), chromium (Cr), copper (Cu), niobium (Nb), titanium (Ti), manganese (Mn), aluminum (Al), silicon (Si), tungsten (W), or vanadium (V).
  • a second material e.g., a doping material
  • the magnetic shielding layer 20 is formed of 80% to 100% of the first material and 0% to 20% of the second material.
  • the magnetic shielding layer 20 includes 80% to 100% of CoFe and 0% to 20% of Si, which may be a dopant element. In some embodiments, the magnetic shielding layer 20 is silicon-steel (or electrical steel).
  • the magnetic shielding layer 20 may have any thickness suitable to redirect magnetic flux and reduce magnetic interference on magnetic sensitive devices (e.g., the semiconductor chip 16 ).
  • the magnetic shielding layer 20 has a thickness that is less than 5 mm, and in some embodiments, the thickness of the magnetic shielding layer 20 is less than 1 mm. In some embodiments, the thickness of the magnetic shielding layer 20 is within a range from 0.1 mm to 1 mm. Thicknesses within this range provide good results, e.g., in the way of reduction of interference caused by magnetic fields (e.g., by the presence of a proximate magnet), without significantly increasing a thickness of the semiconductor device package 12 or the device 10 .
  • the magnetic shielding layer 20 may be formed of a plurality of material layers.
  • FIG. 2A is a cross-sectional view illustrating a magnetic shielding layer 220 having a tri-layer structure
  • FIG. 2B is a cross-sectional view illustrating a magnetic shielding layer 320 having a multi-layer structure.
  • the magnetic shielding layer 220 may have a tri-layer structure.
  • the tri-layer structure may include two magnetic layers 221 , and an insulating layer 222 positioned between the magnetic layers 221 .
  • the insulating layer 222 may be formed of any electrically insulating material.
  • the insulating layer 222 may be formed of at least one of glass, polymer, or ceramic materials.
  • the magnetic layers 221 may be the same or substantially the same as the magnetic shielding layer 20 previously described herein, and may be formed of the same materials as the magnetic shielding layer 20 .
  • the magnetic layers 221 of the magnetic shielding layer 220 are formed of about 80% CoFe and about 20% Si.
  • each of the magnetic layers 221 has a thickness less than 1 mm, and in some embodiments, the thickness of each of the magnetic layers 221 is between about 0.1 mm and 1 mm.
  • the insulating layer 222 serves to reduce electrical losses due to eddy currents (e.g., induced currents) through the magnetic shielding layer 220 , for example, in the presence of an alternating current (AC) electromagnetic field. That is, the presence of the insulating layer 222 sandwiched between the two magnetic layers 221 reduces or prevents induced or eddy currents from flowing through the magnetic shielding layer 220 , and this reduction in induced current results in a reduction in a heating effect that is otherwise caused by such currents. Thus, heating of the magnetic shielding layer 220 due to AC electromagnetic fields is reduced by inclusion of the insulating layer 222 in the magnetic shielding layer 220 .
  • AC alternating current
  • the insulating layer 222 has a thickness less than 1 mm, and in some embodiments, the thickness of the insulating layer 222 is between about 0.1 ⁇ m and 1 mm.
  • the total thickness of the magnetic shielding layer 220 in some embodiments, is less than 5 mm.
  • the magnetic shielding layer 320 may have a multi-layer structure in which a plurality of insulating layers 322 and a plurality of magnetic layers 321 are alternately disposed in a stacked arrangement. For example, adjacent ones of the magnetic layers 321 are spaced apart by at least one insulating layer 322 , and adjacent ones of the insulating layers 322 are spaced apart by at least one magnetic layer 321 . While the magnetic shielding layer 320 is shown in FIG.
  • any number of magnetic layers 321 and insulating layers 322 may be included, for example, by repeating the alternating structure of magnetic layers 321 and insulating layers 322 .
  • the insulating layers 322 may be the same or substantially the same as the insulating layers 222 previously described herein.
  • the magnetic layers 321 may be the same or substantially the same as the magnetic layers 221 previously described herein, and in some embodiments, the magnetic layers 321 may be the same or substantially the same as the magnetic shielding layer 20 previously described herein.
  • the magnetic layers 321 of the magnetic shielding layer 320 are formed of about 80% CoFe and about 20% Si.
  • each of the magnetic layers 321 has a thickness less than 1 mm, and in some embodiments, the thickness of each of the magnetic layers 321 is between about 0.1 mm and 1 mm.
  • the insulating layers 322 serve to reduce electrical losses due to eddy currents (e.g., induced currents) through the magnetic shielding layer 320 , for example, as previously described herein with respect to the insulating layer 222 of the magnetic shielding layer 220 shown in FIG. 2A .
  • the insulating layers 322 have a thickness less than 1 mm, and in some embodiments, the thickness of the insulating layers 322 is between about 0.1 ⁇ m and 1 mm.
  • the total thickness of the magnetic shielding layer 320 in some embodiments, is less than 5 mm.
  • the magnetic shielding layer 220 having a tri-layer structure as shown in FIG. 2A or the magnetic shielding layer 320 having the multi-layer structure as shown in FIG. 2B may be utilized as the magnetic shielding layer 20 described herein.
  • FIG. 3 is a graph illustrating the variance in magnetic flux density when the magnetic permeability of the magnetic shielding layer 20 is varied.
  • ⁇ r is relative permeability, which is a ratio of the magnetic permeability of a specific medium ( ⁇ ) (e.g., the magnetic permeability of the magnetic shielding layer 20 ) to the magnetic permeability of free space ( ⁇ 0 ).
  • the magnetic permeability of free space ( ⁇ 0 ) is approximately equal to: 4 ⁇ 10 ⁇ 7 N ⁇ A ⁇ 2 .
  • the x-axis represents distance in millimeters (mm), and the y-axis represents magnetic flux density.
  • a magnet 302 has a front edge aligned with the 0 position along the x-axis, e.g., the front surface of the magnet 302 is at the 0 mm position.
  • the magnetic shielding layer 20 is spaced apart from the front surface of the magnet 302 by about 3 mm, so that a surface of the magnetic shielding layer 20 that faces the front surface of the magnet 302 is about 3 mm away from the front surface of the magnet 302 .
  • the magnetic shielding layer 20 in the example shown in FIG. 3 has a thickness of about 1 mm.
  • the semiconductor chip 16 is spaced apart from the magnetic shielding layer 20 by a distance of about 2 mm. That is, a surface of the magnetic shielding layer 20 that faces the semiconductor chip 16 is about 2 mm away from the semiconductor chip 16 .
  • the graph of FIG. 3 includes four lines, each of the lines corresponding to a different relative permeability (w) for the magnetic shielding layer 20 . More particularly, a first line 331 corresponds to a relative permeability of 1, a second line 332 corresponds to a relative permeability of 10, a third line 333 corresponds to a relative permeability of 100, and a fourth line 334 corresponds to a relative permeability of 1000.
  • the magnetic flux density at the position of the semiconductor chip 16 decreases. This is because materials having higher relative permeability have a greater ability to redirect the magnetic flux of the magnet 302 . Accordingly, by increasing the relative permeability of the magnetic shielding layer 20 , the magnetic flux of the magnet 302 may be redirected, e.g., away from the semiconductor chip 16 , thereby reducing the magnetic flux density at the semiconductor chip 16 . This results in reduced magnetic interference at the semiconductor chip 16 .
  • the magnetic shielding layer 20 may have a relative permeability that is greater than 100, and in some embodiments, the relative permeability of the magnetic shielding layer 20 may be within a range of about 100 to about 1000.
  • FIG. 4 is a cross-sectional view schematically illustrating an electronic device 410 , in accordance with one or more embodiments of the present disclosure.
  • the electronic device 410 includes a housing 402 defining an exterior surface of the electronic device 410 .
  • the electronic device 410 may be any electronic device, including, for example, a smart phone, a display device, a tablet computer, or the like.
  • the housing 402 which defines an exterior surface of the electronic device 410 , may be formed of any suitable material, and in some embodiments, the housing 402 may include glass, polymers, metals, ceramics, or the like.
  • the electronic device 410 may include the device 10 as previously described herein.
  • the device 10 may be disposed at least partially within the housing 402 of the electronic device 410 .
  • the device 10 may include the substrate 14 , such as a PCB, and the package 12 .
  • the package 12 includes at least one semiconductor chip 16 , which may be a magnetic sensitive chip such as a MRAM chip.
  • the magnetic shielding layer 20 is disposed proximate to the semiconductor chip 16 .
  • the magnetic shielding layer 20 is attached to the semiconductor device package 12 .
  • the magnetic shielding layer 20 may be attached to a surface (e.g., an upper surface) of the semiconductor device package 12 , as shown in FIG. 4 .
  • the magnetic shielding layer 20 may be positioned adjacent to a surface of the housing 402 .
  • the magnetic shielding layer 20 may be positioned adjacent to, and in some embodiments in contact with, an interior surface of the housing 402 .
  • the magnetic shielding layer 20 may be positioned at the surface of the housing 402 , so that the magnetic shielding layer 20 is substantially coplanar with the exterior surface of the housing 402 .
  • the housing 402 is illustrated in FIG. 4 as having opposite first and second surfaces 402 a , 402 b (which may be, for example, front and rear surfaces) and opposite third and fourth surfaces 402 c , 402 d (which may be, for example, lateral or side surfaces).
  • any number of surfaces may be included in the housing 402 , and may be arranged in any geometrical shape.
  • the magnetic shielding layer 20 serves to redirect magnetic flux (e.g., from a magnet or magnetic structure positioned near the housing 402 of the electronic device 410 ) and significantly reduce magnetic interference on magnetic sensitive devices, such as the semiconductor chip 16 .
  • the magnetic shielding layer 20 is positioned between the semiconductor chip 16 and the exterior surface of the housing 402 .
  • the positioning of the device 10 within the housing 402 of the electronic device 410 may be selected to provide improved magnetic immunity (e.g., improved magnetic shielding) of the semiconductor chip 16 .
  • a distance 441 between the semiconductor chip 16 and a first surface 402 a (e.g., exterior surface) of the housing 402 of the electronic device 410 i.e., the surface 402 a on which the magnetic layer 20 is disposed in contact with or adjacent to
  • the distance 441 is less than 5 mm.
  • the distance 441 is less than 3 mm.
  • the distance 441 is within a range from about 0.1 mm to about 5 mm.
  • the distance 441 substantially corresponds to a distance between the magnetic shielding layer 20 and the semiconductor chip 16 .
  • the distance 441 may be a distance between the semiconductor chip 16 and a surface of the housing 402 that is nearest to the semiconductor chip 16 . That is, the first surface 402 a of the housing 402 may be a surface that is nearest to the semiconductor chip 16 .
  • a distance 442 between the semiconductor chip 16 and the second surface (e.g., a rear surface) 402 b of the housing 402 may be greater than 3 mm in some embodiments. In some embodiments, the distance 442 is greater than 10 mm. In some embodiments, the distance 442 is within a range from about 3 mm to about 300 mm. Since, in some embodiments, the magnetic shielding layer 20 is not disposed between the semiconductor chip 16 and the second surface 402 b , the distance 442 should be sufficient to avoid significant effects of magnetic interference if a magnet is brought into close proximity with the second surfaced 402 b of the housing 402 . Since magnetic flux decays with distance, the distance 442 may be selected to suitably avoid magnetic interference in the presence of a magnet. In some embodiments, the distance 442 being greater than 3 mm is suitable, while in other embodiments, a distance greater than 10 mm or greater than 100 mm may be selected to provide greater avoidance of magnetic interference.
  • Distances 443 , 444 (e.g., lateral distances) between respective sides of the semiconductor chip 16 and the third and fourth surfaces 402 c , 402 d may be greater than 1 mm in some embodiments. In some embodiments, the distances 443 , 444 are greater than 10 mm. In some embodiments, the distances 443 , 444 are within a range from about 1 mm to about 300 mm.
  • the semiconductor chip 16 may substantially avoid negative or unwanted effects of magnetic interference.
  • the device 10 may be positioned within the housing 402 , and secured at any desired position within the housing 402 , by any suitable techniques.
  • the device 10 may be secured at a selected or desired position within the housing 402 by any mounting brackets, fasteners, adhesive materials, or the like.
  • FIGS. 5 through 10 are cross-sectional views schematically illustrating various electronic devices, in accordance with embodiments of the present disclosure.
  • the electronic devices illustrated in FIGS. 5 through 10 may be substantially the same in many respects as the electronic device 410 illustrated and described with respect to FIG. 4 , except for the differences that will be discussed below.
  • FIG. 5 illustrates an electronic device 510 , in accordance with one or more embodiments of the present disclosure.
  • the electronic device 510 is substantially the same as the electronic device 410 illustrated and described with respect to FIG. 4 , except that the magnetic shielding layer 20 is disposed on the exterior surface 402 a of the housing 402 of the electronic device 510 .
  • the distances between the magnetic shielding layer 20 , the semiconductor chip 16 , and the various surfaces of the housing 402 may be substantially the same as previously described herein with respect to the electronic device 410 shown in FIG. 4 .
  • the distance between the magnetic shielding layer 20 and the semiconductor chip 16 may be within a range from about 0.1 mm to about 5 mm in some embodiments.
  • the magnetic shielding layer 20 may be attached to the exterior of the surface 402 a of the housing 402 by any suitable technique, including, for example, by use of an adhesive material or the like.
  • the semiconductor chip 16 may be disposed within the encapsulant 18 and may be mechanically and electrically coupled to the substrate 14 , which may be a PCB in some embodiments.
  • the semiconductor chip 16 may be positioned within the housing 402 with the magnetic shielding layer 20 completely overlapping the semiconductor chip 16 , for example, as shown and described with respect to FIG. 1B .
  • the magnetic shielding layer 20 may be separate from the semiconductor device package in which the semiconductor chip 16 and the encapsulant 18 are formed.
  • FIG. 6 illustrates an electronic device 610 , in accordance with one or more embodiments of the present disclosure.
  • the electronic device 610 is substantially the same as the electronic device 410 illustrated and described with respect to FIG. 4 , except that the magnetic shielding layer 20 is embedded in the housing 402 .
  • the magnetic shielding layer 20 may be embedded in the surface 402 a of the housing 402 of the electronic device 610 .
  • the distances between the magnetic shielding layer 20 , the semiconductor chip 16 , and the various surfaces of the housing 402 may be substantially the same as previously described herein with respect to the electronic device 410 shown in FIG. 4 .
  • the distance between the magnetic shielding layer 20 and the semiconductor chip 16 may be within a range from about 0.1 mm to about 5 mm in some embodiments.
  • the magnetic shielding layer 20 may be embedded in the surface 402 a of the housing 402 by any suitable technique. In some embodiments, the magnetic shielding layer 20 may be inserted into an opening or aperture formed in the surface 402 a of the housing, and the magnetic shielding layer 20 may be secured within the opening or aperture by a sealing material, adhesive, fasteners, or the like.
  • the semiconductor chip 16 may be disposed within the encapsulant 18 and may be mechanically and electrically coupled to the substrate 14 , which may be a PCB in some embodiments.
  • the semiconductor chip 16 may be positioned within the housing 402 with the magnetic shielding layer 20 completely overlapping the semiconductor chip 16 , for example, as shown and described with respect to FIG. 1B .
  • the magnetic shielding layer 20 may be separate from the semiconductor device package in which the semiconductor chip 16 and the encapsulant 18 are formed.
  • FIG. 7 illustrates an electronic device 710 , in accordance with one or more embodiments of the present disclosure.
  • the electronic device 710 is substantially the same as the electronic device 410 illustrated and described with respect to FIG. 4 , except that the magnetic shielding layer 20 is disposed on an interior of the surface 402 a of the housing 402 of the electronic device 710 , and the magnetic shielding layer 20 is spaced apart from the semiconductor device package in which the semiconductor chip 16 and the encapsulant 18 are formed.
  • the distances between the magnetic shielding layer 20 , the semiconductor chip 16 , and the various surfaces of the housing 402 may be substantially the same as previously described herein with respect to the electronic device 410 shown in FIG. 4 .
  • the distance between the magnetic shielding layer 20 and the semiconductor chip 16 may be within a range from about 0.1 mm to about 5 mm in some embodiments.
  • the magnetic shielding layer 20 may be attached to the interior of the surface 402 a of the housing 402 by any suitable technique, including, for example, by use of an adhesive material or the like.
  • the semiconductor chip 16 may be disposed within the encapsulant 18 and may be mechanically and electrically coupled to the substrate 14 , which may be a PCB in some embodiments.
  • the semiconductor chip 16 may be positioned within the housing 402 with the magnetic shielding layer 20 completely overlapping the semiconductor chip 16 , for example, as shown and described with respect to FIG. 1B .
  • FIG. 8 illustrates an electronic device 810 , in accordance with one or more embodiments of the present disclosure.
  • the electronic device 810 is substantially the same as the electronic device 410 illustrated and described with respect to FIG. 4 , except that the magnetic shielding layer 20 is disposed between an interior of the surface 402 a of the housing 402 of the electronic device 810 and the semiconductor chip 16 , and the magnetic shielding layer 20 is spaced apart from the interior of the surface 402 a and from the semiconductor device package in which the semiconductor chip 16 and the encapsulant 18 are formed.
  • the distances between the magnetic shielding layer 20 , the semiconductor chip 16 , and the various surfaces of the housing 402 may be substantially the same as previously described herein with respect to the electronic device 410 shown in FIG. 4 .
  • the distance between the magnetic shielding layer 20 and the semiconductor chip 16 may be within a range from about 0.1 mm to about 5 mm in some embodiments.
  • the magnetic shielding layer 20 may be secured in a desired location between the interior of the surface 402 a of the housing 402 and the semiconductor chip 16 by any suitable technique, including, for example, by use of an adhesive material, mounting brackets, fasteners, or the like.
  • the semiconductor chip 16 may be disposed within the encapsulant 18 and may be mechanically and electrically coupled to the substrate 14 , which may be a PCB in some embodiments.
  • the semiconductor chip 16 may be positioned within the housing 402 with the magnetic shielding layer 20 completely overlapping the semiconductor chip 16 , for example, as shown and described with respect to FIG. 1B .
  • FIG. 9 illustrates an electronic device 910 , in accordance with one or more embodiments of the present disclosure.
  • the electronic device 910 is substantially the same as the electronic device 410 illustrated and described with respect to FIG. 4 , except that the device 10 is spaced apart from an interior of the surface 402 a of the housing 402 of the electronic device 910 .
  • the device 10 of the electronic device 910 may be substantially the same as the device 10 previously described herein.
  • the magnetic shielding layer 20 may be form as a part of, or may be attached to, the semiconductor device package 12 , e.g., at an upper surface of the semiconductor device package 12 .
  • the magnetic shielding layer 20 is spaced apart from the interior of the surface 402 a of the housing 402 of the electronic device 910 .
  • the distances between the magnetic shielding layer 20 , the semiconductor chip 16 , and the various surfaces of the housing 402 may be substantially the same as previously described herein with respect to the electronic device 410 shown in FIG. 4 .
  • the distance between the magnetic shielding layer 20 and the semiconductor chip 16 may be within a range from about 0.1 mm to about 5 mm in some embodiments.
  • the device 10 may be secured in a desired location within the housing 402 by any suitable technique, including, for example, by use of an adhesive material, mounting brackets, fasteners, or the like.
  • the semiconductor chip 16 may be disposed within the encapsulant 18 and may be mechanically and electrically coupled to the substrate 14 , which may be a PCB in some embodiments.
  • the magnetic shielding layer 20 may completely overlap the semiconductor chip 16 , for example, as shown and described with respect to FIG. 1B .
  • FIG. 10 illustrates an electronic device 1010 , in accordance with one or more embodiments of the present disclosure.
  • the electronic device 1010 is substantially the same as the electronic device 410 illustrated and described with respect to FIG. 4 , except that the device 110 is spaced apart from an interior of the surface 402 a of the housing 402 of the electronic device 1010 , and the magnetic shielding layer 20 is embedded within the semiconductor device package 12 .
  • the device 10 of the electronic device 1010 may be substantially the same as the device 10 previously described herein, except that the magnetic shielding layer 20 is embedded within the semiconductor device package 12 , instead of being attached to the surface of the semiconductor device package 12 .
  • the magnetic shielding layer 20 may be embedded within the semiconductor device package 12 by any suitable technique, including, for example, by forming the encapsulant 18 to at least partially surround the magnetic shielding layer 20 when the magnetic shielding layer 20 is positioned at a desired location.
  • the encapsulant 18 may be formed abutting upper and lower surfaces of the magnetic shielding layer 20 .
  • the magnetic shielding layer 20 may be completely surrounded by the encapsulant 18 , for example, with the encapsulant 18 abutting upper and lower surfaces, as well as side surfaces of the magnetic shielding layer 20 .
  • the magnetic shielding layer 20 is spaced apart from the interior of the surface 402 a of the housing 402 of the electronic device 1010 .
  • the distances between the magnetic shielding layer 20 , the semiconductor chip 16 , and the various surfaces of the housing 402 may be substantially the same as previously described herein with respect to the electronic device 410 shown in FIG. 4 .
  • the distance between the magnetic shielding layer 20 and the semiconductor chip 16 may be within a range from about 0.1 mm to about 5 mm in some embodiments.
  • the device 10 may be secured in a desired location within the housing 402 by any suitable technique, including, for example, by use of an adhesive material, mounting brackets, fasteners, or the like.
  • the semiconductor chip 16 may be disposed within the encapsulant 18 and may be mechanically and electrically coupled to the substrate 14 , which may be a PCB in some embodiments.
  • the magnetic shielding layer 20 may completely overlap the semiconductor chip 16 , for example, as shown and described with respect to FIG. 1B .
  • the electronic devices may include a plurality of magnetic shielding layers 20 .
  • magnetic shielding layers 20 may be provided on multiple surfaces of the housing of the electronic devices, on multiple surfaces of the semiconductor device package, or the like, which provides enhanced magnetic shielding of the semiconductor chip 16 from various different directions.
  • FIG. 11 is a graph illustrating experimental results of bit error rates due to a magnetic field for an unshielded device and for a device including a magnetic shielding layer, such as the device 10 shown in FIG. 1A .
  • the data points 1101 indicate bit error rates for the unshielded device, while the data points 1102 indicate bit error rates for the device including the magnetic shielding layer in accordance with embodiments of the present disclosure. More particularly, in the experiment, a magnet having a magnetic field strength of 3500 Oersted (Oe) was positioned at a distance of 1.5 mm from an MRAM chip for a period of time of over 100 hours.
  • Oe Oersted
  • the unshielded device experienced significant bit error rates nearly immediately in the presence of the magnetic field of the magnet. After 100 hours of exposure, the bit error rate of the unshielded device was nearly 1,000,000 parts per million (e.g., bit errors per million).
  • the device having the magnetic shielding layer included a magnetic shielding layer with a thickness about 0.3 mm.
  • the magnetic shielding layer was formed of silicon steel.
  • the same magnet was positioned at a distance of about 1.5 mm from the MRAM chip, and the magnetic shielding layer was positioned between the MRAM chip and the magnet.
  • the bit error rate of the device having the magnetic shielding layer was about 1 part per million, as shown at data points 1102 . This reflects a reduction of about 6 orders of magnitude with respect to the unshielded device (e.g., from 10 6 to 1 ppm).
  • FIG. 12 is a flowchart 1200 illustrating a method of manufacturing an electronic device having a magnetic shielding layer, in accordance with one or more embodiments of the present disclosure.
  • the method includes coupling a semiconductor device package 12 to a printed circuit board (PCB).
  • the semiconductor device package 12 may be electrically and mechanically coupled to the PCB.
  • the semiconductor device package 12 includes a semiconductor chip 16 at least partially surrounded by an encapsulant 18 .
  • the encapsulant may be an epoxy mold compound (EPC).
  • the method includes securing the semiconductor device package 12 within a housing 402 of an electronic device.
  • the electronic device may be any electronic device, and in some embodiments, may be any of the electronic devices previously described herein. In some embodiments, the electronic device may be at least one of: a smart phone, a display device or a tablet computer device.
  • the method includes attaching a magnetic shielding layer 20 to one of the housing 402 or the semiconductor device package 12 .
  • the magnetic shielding layer 20 is spaced apart from the semiconductor chip 16 by a distance less than 5 mm.
  • the magnetic shielding layer 20 is attached to a surface of the semiconductor device package 12 , and the magnetic shielding layer 20 is disposed between the housing 402 of the electronic device and the semiconductor chip 16 .
  • Embodiments of the present disclosure provide several advantages. For example, embodiments provided herein can protect magnetic sensitive devices (e.g., semiconductor chips) from harmful effects caused by interference from external magnetic fields. This may result in prevention or reduction of operational failures of such magnetic sensitive devices, including reading or writing failures and the like. Embodiments of the present disclosure may be provided in conjunction with, or may be include, semiconductor packages of various different types. Other advantages are described herein and still others will be apparent in view of the present disclosure.
  • a device includes a housing defining an exterior surface.
  • a semiconductor chip is within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing.
  • a magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.
  • a device includes a substrate.
  • a semiconductor device package is disposed on the substrate, and the semiconductor device package includes a magnetoresistive random-access memory (MRAM) chip at least partially surrounded by an encapsulant.
  • MRAM magnetoresistive random-access memory
  • a magnetic shielding layer is disposed on the semiconductor device package.
  • a method includes electrically and mechanically coupling a semiconductor device package to a printed circuit board (PCB), the semiconductor device package including a semiconductor chip at least partially surrounded by an encapsulant.
  • the semiconductor device package is secured within a housing of an electronic device.
  • a magnetic shielding layer is attached to one of the housing or the semiconductor device package, and the magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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US16/711,152 US11276649B2 (en) 2019-06-28 2019-12-11 Devices and methods having magnetic shielding layer
DE102019135181.2A DE102019135181A1 (de) 2019-06-28 2019-12-19 Vorrichtungen und verfahren mit einer magnetischen abschirmschicht
KR1020200031921A KR102378232B1 (ko) 2019-06-28 2020-03-16 자기 차폐 층을 가진 디바이스 및 방법
TW109121687A TWI774013B (zh) 2019-06-28 2020-06-24 具有磁屏蔽層的裝置及方法
TW111124385A TWI830269B (zh) 2019-06-28 2020-06-24 具有磁屏蔽層的裝置之製造方法
CN202010598072.6A CN112151668A (zh) 2019-06-28 2020-06-28 半导体器件及其形成方法

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Publication number Priority date Publication date Assignee Title
US11925009B2 (en) * 2021-03-09 2024-03-05 Hamilton Sundstrand Corporation Adaptive design and fabrication of radiation shielding inserts for electronic components
CN113242685A (zh) * 2021-05-18 2021-08-10 中国电子科技集团公司第五十八研究所 一种气密性磁存储器封装结构及其制备方法
US20230112673A1 (en) * 2021-10-11 2023-04-13 Globalfoundries Singapore Pte. Ltd. Magnetic shielding of semiconductor devices
KR102456095B1 (ko) * 2022-06-20 2022-10-18 주식회사 위앤아이티 Nd자석 및 자기장 차폐용 sts 구조물을 포함하는 진동 센서용 거치대 및 이를 이용한 용해로의 진동량 측정방법

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040126905A1 (en) 2002-04-18 2004-07-01 Bhattacharyya Manoj K Magnetic shielding for MRAM devices
TW200631159A (en) 2005-02-17 2006-09-01 Taiwan Semiconductor Mfg Co Ltd Magnetic shielding for magneticaly sensitive semiconductor devices
TW200635496A (en) 2005-03-25 2006-10-01 Taiwan Semiconductor Mfg Co Ltd Radiation shielding circuit, memory device, and manufacturing method thereof
US20150221598A1 (en) * 2014-02-05 2015-08-06 Byung Woo LEE Package substrate and semiconductor package including the same
US20150271911A1 (en) * 2014-03-18 2015-09-24 Apple Inc. Multi-layer thin-film coatings for system-in-package assemblies in portable electronic devices
US20180351078A1 (en) * 2017-05-31 2018-12-06 Globalfoundries Singapore Pte. Ltd. Shielded semiconductor devices and methods for fabricating shielded semiconductor devices
US20200006245A1 (en) * 2018-06-29 2020-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dc and ac magnetic field protection for mram device using magnetic-field-shielding structure
US20200075442A1 (en) * 2018-09-04 2020-03-05 Ningbo Semiconductor International Corporation Wafer-level system-in-package packaging method and package structure thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10142594A1 (de) * 2001-08-31 2003-03-27 Infineon Technologies Ag Kompensation eines magnetischen Biasfeldes in einer Speicherschicht einer magnetoresistiven Speicherzelle
US20090273044A1 (en) * 2008-05-05 2009-11-05 Rainer Leuschner Semiconductor Device, Memory Module, and Method of Manufacturing a Semiconductor Device
JP5425461B2 (ja) * 2008-12-26 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN102623482A (zh) * 2011-02-01 2012-08-01 飞思卡尔半导体公司 Mram器件及其装配方法
JP6182993B2 (ja) * 2013-06-17 2017-08-23 ソニー株式会社 記憶素子、記憶装置、記憶素子の製造方法、磁気ヘッド
JP6122353B2 (ja) * 2013-06-25 2017-04-26 ルネサスエレクトロニクス株式会社 半導体パッケージ
JP6010005B2 (ja) * 2013-09-09 2016-10-19 株式会社東芝 半導体装置及びその製造方法
JP6074345B2 (ja) * 2013-09-24 2017-02-01 株式会社東芝 半導体装置及びその製造方法
US9536841B2 (en) * 2014-08-01 2017-01-03 Cyntec Co., Ltd. Semiconductor package with conformal EM shielding structure and manufacturing method of same
JP6496036B2 (ja) * 2015-04-27 2019-04-03 東芝メモリ株式会社 磁気メモリ装置
CN207783410U (zh) * 2017-12-29 2018-08-28 广东欧珀移动通信有限公司 芯片、电路板组件及移动终端

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040126905A1 (en) 2002-04-18 2004-07-01 Bhattacharyya Manoj K Magnetic shielding for MRAM devices
TW200631159A (en) 2005-02-17 2006-09-01 Taiwan Semiconductor Mfg Co Ltd Magnetic shielding for magneticaly sensitive semiconductor devices
TW200635496A (en) 2005-03-25 2006-10-01 Taiwan Semiconductor Mfg Co Ltd Radiation shielding circuit, memory device, and manufacturing method thereof
US20150221598A1 (en) * 2014-02-05 2015-08-06 Byung Woo LEE Package substrate and semiconductor package including the same
US20150271911A1 (en) * 2014-03-18 2015-09-24 Apple Inc. Multi-layer thin-film coatings for system-in-package assemblies in portable electronic devices
US20180351078A1 (en) * 2017-05-31 2018-12-06 Globalfoundries Singapore Pte. Ltd. Shielded semiconductor devices and methods for fabricating shielded semiconductor devices
US20200006245A1 (en) * 2018-06-29 2020-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dc and ac magnetic field protection for mram device using magnetic-field-shielding structure
US20200075442A1 (en) * 2018-09-04 2020-03-05 Ningbo Semiconductor International Corporation Wafer-level system-in-package packaging method and package structure thereof

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KR20210002325A (ko) 2021-01-07
TW202243184A (zh) 2022-11-01
DE102019135181A1 (de) 2020-12-31
TWI830269B (zh) 2024-01-21
CN112151668A (zh) 2020-12-29
TWI774013B (zh) 2022-08-11
US20200411449A1 (en) 2020-12-31
TW202115860A (zh) 2021-04-16

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