US10783969B2 - Sense amplifier - Google Patents

Sense amplifier Download PDF

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Publication number
US10783969B2
US10783969B2 US16/200,064 US201816200064A US10783969B2 US 10783969 B2 US10783969 B2 US 10783969B2 US 201816200064 A US201816200064 A US 201816200064A US 10783969 B2 US10783969 B2 US 10783969B2
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Prior art keywords
transistor
inverter
sense amplifier
transmission gate
reference voltage
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US20190279717A1 (en
Inventor
Bin SHENG
Zhifeng MAO
Shengbo ZHANG
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a sensor amplifier.
  • a sensor amplifier i.e., a read amplifier
  • a sensor amplifier is a key component of a storage circuit.
  • a conventional single-ended sense amplifier as shown in FIG. 1 , including a storage unit 100 , a column decoder 200 and a current mirroring circuit 300 ) of a flash memory, as shown in FIG. 2 , a reference voltage node A′ of a second-stage sense amplifier 400 is pre-charged to a power supply voltage VDD during a time period T 1 .
  • the reference voltage node A′ cannot reach an invert enabling voltage of the second-stage sense amplifier 400 until being discharged by several hundred millivolts, resulting in the need for relatively long data read time (the entire time period T 2 ). This is particularly noticeable when a non-volatile flash memory unit, such as a NOR flash, is in a weak erase state and the read current is relatively small.
  • a mismatch between the performance indexes of transistors M 100 and M 200 therein will also cause changes in the invert enabling voltage of the sense amplifier.
  • the objective of the present invention is to provide a sense amplifier, in order to solve the problem in the existing flash memory of long data read time of the sense amplifier.
  • the present invention provides a sense amplifier for a flash memory, including a pre-charging circuit, a first capacitor, a first inverter, and a first transmission gate connected in parallel with the first inverter, wherein:
  • the pre-charging circuit is connectable to a reference voltage node of the flash memory and is able to pre-charge a word line of the flash memory via the reference voltage node, wherein a potential of the reference voltage node remains unchanged after the pre-charging is completed;
  • a potential of the reference voltage node is adjustable according to a state of the flash memory until an output voltage of the first inverter changes;
  • the first capacitor has a first end connectable to the reference voltage node, and a second end connected to an input of the first inverter and a first end of the first transmission gate;
  • an output of the first inverter is connected to a second end of the first transmission gate.
  • the sense amplifier further includes a second inverter and a third inverter, wherein an input of the second inverter is connected to the output of the first inverter, and an output of the second inverter is connected to an input of the third inverter.
  • the pre-charging circuit includes a first transistor and a second transmission gate, wherein:
  • the first transistor is a P-channel field effect transistor; a gate of the first transistor is connected to a drain of the first transistor, and a source of the first transistor is connected to a power supply voltage; a first end of the second transmission gate is connected to the drain of the first transistor, and a second end of the second transmission gate is connectable to the reference voltage node.
  • the first transmission gate is controlled by a first control signal; when a level of the first control signal is a ground level, the first and second ends of the first transmission gate have equal potentials; and when the level of the first control signal equals the power supply voltage, the first and second ends of the first transmission gate have different potentials.
  • the second transmission gate is also controlled by the first control signal; when the level of the first control signal is the ground level, the first and second ends of the second transmission gate have equal potentials; and when the level of the first control signal equals the power supply voltage, the first and second ends of the second transmission gate have different potentials.
  • the flash memory further includes a current mirroring circuit, a storage unit, and a column decoder, wherein the storage unit is connected to the column decoder, and the column decoder is connected to the current mirroring circuit.
  • the current mirroring circuit includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein:
  • a source of the second transistor and a source of the third transistor are connected to the power supply voltage
  • a gate of the second transistor is connected to a gate of the third transistor
  • the gate of the second transistor is connected to a drain of the second transistor and a source of the fourth transistor
  • a drain of the third transistor is connected to a source of the fifth transistor and the reference voltage node
  • a drain of the fourth transistor and a drain of the fifth transistor are connected to the column decoder.
  • the current mirroring circuit further includes a fourth inverter and a fifth inverter, where:
  • an input of the fourth inverter is connected to the drain of the fourth transistor, and an output of the fourth inverter is connected to a gate of the fourth transistor;
  • an input of the fifth inverter is connected to the drain of the fifth transistor, and an output of the fifth inverter is connected to a gate of the fifth transistor.
  • the potential of the reference voltage node continuously decreases until the output voltage of the first inverter changes.
  • the present invention provides another sense amplifier for a flash memory, including a first capacitor, a first inverter, a first transmission gate, a first transistor and a second transmission gate, wherein: the first transmission gate is connected in parallel with the first inverter; the first capacitor has a first end connectable to a reference voltage node of the flash memory, and a second end connected to an input of the first inverter and a first end of the first transmission gate; an output of the first inverter is connected to a second end of the first transmission gate; a gate of the first transistor is connected to a drain of the first transistor, and a source of the first transistor is connected to a power supply voltage; a first end of the second transmission gate is connected to the drain of the first transistor, and a second end of the second transmission gate is connectable to the reference voltage node.
  • the sense amplifier In the sense amplifier provided by the present invention, by connecting one end of the first capacitor with the reference voltage node and the other end with the input of the first inverter, and connecting the first inverter in parallel with the first transmission gate, the potential of the other end of the first capacitor will change correspondingly due to the coupling effect of the first capacitor; moreover, as the potential of the other end of the first capacitor is at an equilibrium level of the first inverter, the gain of the first inverter is maximum at this time. Therefore, a correct inversion at the output of the first inverter IN 1 can be achieved after merely a few tens of millivolts of change of the voltage of node B, and hence the corresponding data reading can be completed, which greatly reduces data read time, and thus improving the read speed.
  • the first inverter always obtains a maximum gain. Even if a performance index mismatch exists in the field effect transistors of the sense amplifier, because the difference between the input voltage and the output voltage of the first inverter in the second-stage sense amplifier is limited to the equilibrium level of the first inverter, the influence of the mismatch on the sense amplifier is eliminated and high resolution is achieved.
  • FIG. 1 is a schematic diagram of an existing sense amplifier and flash memory
  • FIG. 2 is a schematic diagram of a voltage waveform of an existing sense amplifier
  • FIG. 3 is a schematic diagram of a sense amplifier and a flash memory according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a voltage waveform of a sense amplifier according to an embodiment of the present invention.
  • 100 storage unit
  • 200 column decoder
  • 300 current mirroring circuit
  • 400 sense amplifier
  • 10 storage unit
  • 20 column decoder
  • 30 current mirroring circuit
  • 40 sense amplifier
  • the core idea of the present invention is to provide a sense amplifier, in order to solve the problem in the existing flash memory of long data read time of the sense amplifier.
  • the present invention provides a sense amplifier for use in a flash memory.
  • the sense amplifier includes a pre-charging circuit, a first capacitor, a first inverter, and a first transmission gate connected in parallel with the first inverter, where the pre-charging circuit is connectable to a reference voltage node of the flash memory and is able to pre-charge a bit line of the flash memory via the reference voltage node, and a potential of the reference voltage node remains unchanged after the pre-charging is completed; the potential of the reference voltage node is adjustable according to the state of the flash memory until the output voltage of the first inverter changes; one end of the first capacitor is connected to the reference voltage node, and the other end is connected to the input of the first inverter and a first end of the first transmission gate; and the output of the first inverter is connected to a second end of the first transmission gate.
  • the embodiment provides a sense amplifier 40 .
  • the sense amplifier 40 is used in a flash memory.
  • the sense amplifier 40 includes a pre-charging circuit, a first capacitor C 1 , a first inverter IN 1 , and a first transmission gate G 1 connected in parallel with the first inverter IN 1 .
  • the pre-charging circuit is connected between a power supply voltage VDD and a reference voltage node A of the flash memory. As shown in FIG. 4 , the VDD pre-charges a bit line (in FIG.
  • a potential of the reference voltage node A adjusts (i.e., the voltage level at the node A always changes within the time period T 2 ) according to the state of the flash memory (e.g. an erase reading “0” state, or an erase reading “1” state) until the output voltage of the first inverter changes.
  • the erase reading “0” state causes a rise of the voltage level at node A
  • the erase reading “1” state causes a drop of the voltage level at node A.
  • One end of the first capacitor C 1 is connected to the reference voltage node A, and the other end is connected to the input of the first inverter IN 1 and a first end (i.e., node B) of the first transmission gate G 1 . Due to the coupling effect of the first capacitor, there is a certain difference between the voltage of node A and the voltage of node B (i.e., representing that the voltage of node B does not need to be charged to a level equals VDD), and the changes in the levels of the nodes A and B at the same time instant are equal.
  • the output of the first inverter IN 1 is connected to a second end (node C) of the transmission gate G 1 .
  • the voltages thereof are associated with each other within the time period T 1 (at this time, the voltage of node D is at low level, and the first transmission gate G 1 is equivalent to be in a turn-on state), and the voltage of node C also rises to a certain value.
  • the voltage of node C does not change in real time with the voltage of node B within the time period T 2 (at this time, the voltage of node D is at high level, and the first transmission gate G 1 is equivalent to be in a turn-off state).
  • the gain of the first inverter IN 1 is maximum at this time. Moreover, as the voltage of node B changes with the voltage of node A, a correct inversion at the output of the first inverter IN 1 can be achieved after merely a few tens of millivolts of change, and hence the corresponding data reading can be completed, which greatly reduces data read time, and thus improving the read speed.
  • the first inverter IN 1 in the second-stage sense amplifier 40 As the difference between the input voltage and the output voltage of the first inverter IN 1 in the second-stage sense amplifier 40 is limited to the equilibrium level of the first inverter IN 1 when the pre-charging is finished, the first inverter IN 1 always obtains a maximum gain. Even if a performance index mismatch exists in the field effect transistors of the sense amplifier 40 , because the difference between the input voltage and the output voltage of the first inverter IN 1 in the second-stage sense amplifier is limited to the equilibrium level of the first inverter, the influence of the mismatch on the sense amplifier is eliminated and high resolution is achieved.
  • the sense amplifier 40 further includes a second inverter IN 2 and a third inverter IN 3 , where the input of the second inverter IN 2 is connected to the output (node C) of the first inverter IN 1 .
  • the output of the second inverter IN 2 is connected to the input of the third inverter IN 3 .
  • the output of the third inverter IN 3 outputs read data.
  • the pre-charging circuit includes a first transistor M 1 and a second transmission gate G 2 , where the first transistor M 1 is a P-channel field effect transistor.
  • the gate of the first transistor M 1 is connected to the drain of the first transistor M 1 .
  • the source of the first transistor M 1 is connected to the power supply voltage VDD.
  • One end of the second transmission gate G 2 is connected to the drain of the first transistor M 1 , and the other end is connected to the reference voltage node A.
  • the first transmission gate G 1 is controlled by a first control signal (the voltage of node D).
  • the level of the first control signal (the voltage of node D) is ground level (i.e., the time period T 1 )
  • the potentials of two ends of the first transmission gate G 1 are equal.
  • the level of the first control signal is the power supply voltage (i.e., the time period T 2 )
  • the potentials of the two ends of the first transmission gate G 1 are different.
  • the second transmission gate G 2 is controlled by the first control signal (the voltage of node D).
  • the level of the first control signal (the voltage of node D) is the ground level (i.e., the time period T 1 )
  • the potentials of two ends of the second transmission gate G 2 are equal.
  • the level of the first control signal is the power supply voltage (i.e., the time period T 2 )
  • the potentials of the two ends of the second transmission gate G 2 are different.
  • the flash memory further includes a current mirroring circuit 30 , a storage unit 10 , and a column decoder 20 , where the storage unit 10 is connected to the column decoder 20 , and the column decoder 20 is connected to the current mirroring circuit 30 .
  • the current mirroring circuit 30 includes a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , and a fifth transistor M 5 .
  • the source of the second transistor M 2 and the source of the third transistor M 3 are connected to the power supply voltage VDD.
  • the gate of the second transistor M 2 is connected to the gate of the third transistor M 3 .
  • the gate of the second transistor M 2 is connected to the drain of the second transistor M 2 and the source of the fourth transistor M 4 .
  • the drain of the third transistor M 3 is connected to the source of the fifth transistor M 5 and the reference voltage node A.
  • the drain of the fourth transistor M 4 and the drain of the fifth transistor M 5 are connected to the column decoder 20 .
  • the current mirroring circuit 30 further includes a fourth inverter IN 4 and a fifth inverter IN 5 , where the input of the fourth inverter IN 4 is connected to the drain of the fourth transistor M 4 .
  • the output of the fourth inverter IN 4 is connected to the gate of the fourth transistor M 4 ; the input of the fifth inverter IN 5 is connected to the drain of the fifth transistor M 5 , and the output of the fifth inverter IN 5 is connected to the gate of the fifth transistor M 5 .
  • read current current flowing into the source of the fifth transistor M 5
  • the potential of the reference voltage node causes the potential of the reference voltage node to continuously decrease until the output voltage of the first inverter changes, for example, being adjusted from the first level to the second level.
  • the first level is higher than the second level (when reading “1”); the first level is lower than the second level (when reading “0”).
  • the second transistor and the fourth transistor constitute a reference current generation circuit. Signals provided by the storage unit 10 and the column decoder 20 cause reference current flowing through the second transistor and the fourth transistor to remain unchanged.
  • the current mirroring circuit 30 copies the reference current to a column constituted by the third transistor and the fifth transistor.
  • the current on the storage unit will accordingly be different; and if the current is greater than or equal to the reference current on the third transistor in amplitude, the potential of the source of the fifth transistor changes, so that an external circuit obtains the state of the storage unit. It takes a period of time for the pre-charging circuit to pre-charge the word line of the storage unit 10 until the voltages on the word line and a bit line meet a set target value.
  • the sense amplifier 40 provided by the present invention, by connecting one end of the first capacitor C 1 with the reference voltage node A and the other end with the input of the first inverter IN 1 , and connecting the first inverter IN 1 in parallel with the first transmission gate G 1 , the potential of the other end of the first capacitor C 1 also changes correspondingly due to the coupling effect of the first capacitor C 1 ; moreover, as the potential of node B is at an equilibrium level of the first inverter IN 1 , the gain of the first inverter IN 1 is maximum at this time.
  • a correct inversion at the output of the first inverter IN 1 can be achieved after merely a few tens of millivolts of change of the voltage of node B, and hence the corresponding data reading can be completed, which greatly reduces data read time, and thus improving the read speed.
  • the first inverter IN 1 in the second-stage sense amplifier 40 As the difference between the input voltage and the output voltage of the first inverter IN 1 in the second-stage sense amplifier 40 is limited to the equilibrium level of the first inverter IN 1 when the pre-charging is finished, the first inverter IN 1 always obtains a maximum gain. Even if a performance index mismatch exists in the field effect transistors of the sense amplifier 40 , because the difference between the input voltage and the output voltage of the first inverter in the second-stage sense amplifier is limited to the equilibrium level of the first inverter, the influence of the mismatch on the sense amplifier is eliminated and high resolution is achieved.
  • the foregoing embodiments describe in detail different configurations of the sense amplifier.
  • the present invention includes, but is not limited to, the configurations listed in the foregoing embodiments. Any content that is transformed based on the configurations provided by the foregoing embodiments falls within the scope of protection of the present invention. Persons skilled in the art can draw inferences according to the contents of the foregoing embodiments.
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CN201810202084.5 2018-03-12
CN201810202084.5A CN108492840B (zh) 2018-03-12 2018-03-12 灵敏放大器

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11862285B2 (en) 2020-09-01 2024-01-02 Anhui University Sense amplifier, memory and control method of sense amplifier
US11887655B2 (en) 2020-08-13 2024-01-30 Anhui University Sense amplifier, memory, and method for controlling sense amplifier by configuring structures using switches
US11929111B2 (en) 2020-09-01 2024-03-12 Anhui University Sense amplifier, memory and method for controlling sense amplifier

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102652215B1 (ko) 2019-04-30 2024-03-27 양쯔 메모리 테크놀로지스 씨오., 엘티디. 판독 시간을 단축할 수 있는 메모리 시스템
CN111583975B (zh) * 2020-04-01 2022-06-17 上海华虹宏力半导体制造有限公司 灵敏放大器
CN111653299B (zh) * 2020-04-27 2022-07-01 中国科学院微电子研究所 灵敏放大器以及存储器
CN111933195B (zh) * 2020-09-01 2022-11-01 安徽大学 灵敏放大器、存储器和灵敏放大器的控制方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818268A (en) * 1995-12-27 1998-10-06 Lg Semicon Co., Ltd. Circuit for detecting leakage voltage of MOS capacitor
US20150194193A1 (en) * 2014-01-07 2015-07-09 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Memory and reading method thereof, and circuit for reading memory
US20160019972A1 (en) * 2013-03-15 2016-01-21 Silicon Storage Technology, Inc. Self-Timer For Sense Amplifier In Memory Device
US9267980B2 (en) * 2011-08-15 2016-02-23 Micron Technology, Inc. Capacitance evaluation apparatuses and methods
US9378834B2 (en) * 2014-07-22 2016-06-28 Silicon Storage Technology, Inc. Bitline regulator for high speed flash memory system
US10056152B2 (en) * 2016-09-23 2018-08-21 Samsung Electronics Co., Ltd. Methods of reading data in nonvolatile memory devices and nonvolatile memory devices
US10181354B2 (en) * 2016-09-09 2019-01-15 Silicon Storage Technology, Inc. Sense amplifier with bit line pre-charge circuit for reading flash memory cells in an array
US10193563B2 (en) * 2014-09-26 2019-01-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, wireless sensor, and electronic device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107464581B (zh) * 2017-08-09 2020-05-01 上海华虹宏力半导体制造有限公司 灵敏放大器电路

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818268A (en) * 1995-12-27 1998-10-06 Lg Semicon Co., Ltd. Circuit for detecting leakage voltage of MOS capacitor
US9267980B2 (en) * 2011-08-15 2016-02-23 Micron Technology, Inc. Capacitance evaluation apparatuses and methods
US20160019972A1 (en) * 2013-03-15 2016-01-21 Silicon Storage Technology, Inc. Self-Timer For Sense Amplifier In Memory Device
US9620235B2 (en) * 2013-03-15 2017-04-11 Silicon Storage Technology, Inc. Self-timer for sense amplifier in memory device
US20150194193A1 (en) * 2014-01-07 2015-07-09 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Memory and reading method thereof, and circuit for reading memory
US9378834B2 (en) * 2014-07-22 2016-06-28 Silicon Storage Technology, Inc. Bitline regulator for high speed flash memory system
US10193563B2 (en) * 2014-09-26 2019-01-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, wireless sensor, and electronic device
US10181354B2 (en) * 2016-09-09 2019-01-15 Silicon Storage Technology, Inc. Sense amplifier with bit line pre-charge circuit for reading flash memory cells in an array
US10056152B2 (en) * 2016-09-23 2018-08-21 Samsung Electronics Co., Ltd. Methods of reading data in nonvolatile memory devices and nonvolatile memory devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11887655B2 (en) 2020-08-13 2024-01-30 Anhui University Sense amplifier, memory, and method for controlling sense amplifier by configuring structures using switches
US11862285B2 (en) 2020-09-01 2024-01-02 Anhui University Sense amplifier, memory and control method of sense amplifier
US11929111B2 (en) 2020-09-01 2024-03-12 Anhui University Sense amplifier, memory and method for controlling sense amplifier

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