US10586836B2 - Display device and manufacturing method thereof - Google Patents

Display device and manufacturing method thereof Download PDF

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US10586836B2
US10586836B2 US15/838,624 US201715838624A US10586836B2 US 10586836 B2 US10586836 B2 US 10586836B2 US 201715838624 A US201715838624 A US 201715838624A US 10586836 B2 US10586836 B2 US 10586836B2
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conductive
region
display device
substrate
insulating layer
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US20180226459A1 (en
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Jung-Bae Bae
Won Kyu Kwak
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAE, JUNG-BAE, KWAK, WON KYU
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H01L27/3246—
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H01L27/3269—
    • H01L51/0023—
    • H01L51/5237—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • H01L51/5092—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/17—Carrier injection layers
    • H10K50/171—Electron injection layers

Definitions

  • Exemplary embodiments of the present invention relate to a display device, and more particularly to a manufacturing method thereof.
  • a display device may include a plurality of pixels which are units for displaying an image.
  • a pixel of the display device including an emission layer may include a light emitting diode (LED) including a cathode, an anode, and an emission layer; and a plurality of transistors and at least one capacitor for driving the light emitting diode.
  • LED light emitting diode
  • the light emitting diode may include two electrodes and an emission layer disposed therebetween. Electrons injected from a cathode may be combined in the emission layer to form excitons, and the excitons may emit light and energy.
  • Each of the transistors may include at least one switching transistor and a driving transistor.
  • the at least one switching transistor may receive a data signal depending on a scan signal, and may transfer a corresponding voltage to a driving transistor.
  • the driving transistor may be directly or indirectly connected with the light emitting diode to control an amount of a driving current to be transferred to the light emitting diode such that each of the pixels can emit light of desired luminance.
  • the capacitor may be connected with a driving gate electrode of the driving transistor to serve to maintain a voltage of the driving gate electrode.
  • a voltage of a driving gate electrode of a driving transistor included in a pixel of the display and/or a voltage of a conductor electrically connected thereto resonate by coupling with other signals, luminance of the pixel may be changed, thus reducing image quality.
  • image quality defects such as inter-pixel color deviation and crosstalk in a display image may be reduced or eliminated.
  • An exemplary embodiment of the present invention provides a display device including a substrate and an active pattern positioned above the substrate.
  • the active pattern includes a channel region and a conductive region having a higher carrier concentration than the channel region.
  • a first insulating layer is disposed on the active pattern.
  • a first conductive layer is disposed on the first insulating layer and includes a first conductor.
  • the channel region of the active pattern includes a first channel region overlapping the first conductor along a direction orthogonal to an upper surface of the substrate.
  • the conductive region of the active pattern includes a first conductive region overlapping the first conductor along the direction orthogonal to the upper surface of the substrate.
  • the first conductive region may include a first portion overlapping the first conductor along the direction orthogonal to the upper surface of the substrate and a second portion connected with the first portion and not overlapping the first conductor along the direction orthogonal to the upper surface of the substrate.
  • the channel region of the active pattern may include a second channel region overlapping a second conductor included in the first conductive layer along the direction orthogonal to the upper surface of the substrate. The second portion may be connected with the second channel region.
  • the first conductive layer may further include a third conductor that is separated from the first conductor and the second conductor, and the second portion of the first conductor may be insulated from and crosses the third conductor.
  • the first insulating layer may have a contact hole overlapping the first conductor along the direction orthogonal to the upper surface of the substrate.
  • the first conductive region may be electrically connected to the first conductor through the contact hole.
  • An exemplary embodiment of the present invention provides a display device including an active pattern including a plurality of channel regions and a conductive region having a higher carrier concentration than the channel regions.
  • a first insulating layer is disposed on the active pattern.
  • a first conductive layer disposed on the first insulating layer.
  • the first conductive layer includes a first gate electrode.
  • the channel regions of the active pattern include a first channel region overlapping the first gate electrode along a direction orthogonal to an upper surface of the substrate.
  • the conductive region of the active pattern includes a connector overlapping the first gate electrode along the direction orthogonal to the upper surface of the substrate and separated from the first channel region.
  • the channel regions of the active pattern further may include a second channel region which is separated from the first channel region and overlaps a second gate electrode included in the first conductive layer along the direction orthogonal to the upper surface of the substrate.
  • the connector may be connected with the second channel region or a portion of the conductive region connected with the second channel region.
  • the first insulating layer may have a first contact hole formed above the first gate electrode.
  • the connector may be electrically connected to the first gate electrode through the first contact hole.
  • the first conductive layer may further include a first scan line disposed between the first gate electrode and the second gate electrode.
  • the connector may be insulated from and cross the first scan line.
  • the channel regions of the active pattern may further include a third channel region which is separated from the first channel region and overlaps the first scan line along the direction orthogonal to the upper surface of the substrate.
  • the connector may be connected with the third channel region or a portion of the conductive region connected with the third channel region.
  • the active pattern may be physically continuous from the first channel region, via the third channel region, and to the connector.
  • the display device may include a second insulating layer disposed on the first conductive layer and a second conductive layer disposed on the second insulating layer.
  • the second conductive layer may include a storage line.
  • the storage line may include an expansion overlapping the first gate electrode along the direction orthogonal to the upper surface of the substrate with the second insulating layer disposed between the expansion and the first gate electrode to form a capacitor.
  • the expansion may have a continuous planar shape with no opening therein.
  • the display device may include a third insulating layer disposed on the second conductive layer and a third conductive layer disposed on the third insulating layer.
  • the third conductive layer may include a driving voltage line for transferring a driving voltage.
  • the third insulating layer may include a second contact hole overlapping the expansion along the direction orthogonal to the upper surface of the substrate.
  • the driving voltage line may be electrically connected to the expansion through the second contact hole.
  • the first insulating layer and the second insulating layer may have a third contact hole overlapping a portion of the conductive region of the active pattern along the direction orthogonal to the upper surface of the substrate.
  • the second conductive layer may include an initialization voltage line for transferring an initialization voltage.
  • the initialization voltage line may be electrically connected to a portion of the conductive region of the active pattern through the third contact hole.
  • the first conductive layer may further include a first scan line separated from the first gate electrode.
  • the channel regions of the active pattern may include a portion overlapping the first scan line along the direction orthogonal to the upper surface of the substrate.
  • the conductive region of the active pattern may include a portion overlapping the first scan line along the direction orthogonal to the upper surface of the substrate.
  • An exemplary embodiment of the present invention provides a manufacturing method of a display device, including forming a semiconductor pattern on a substrate.
  • the method includes forming a conductive connector by doping a portion of the semiconductor pattern.
  • the method includes forming a first insulating layer on the semiconductor pattern.
  • the method includes forming a first contact hole on the connector by patterning the first insulating layer.
  • the method includes forming a first conductive layer by stacking a conductive material on the first insulating layer and patterning the stacked conductive material.
  • the method includes forming an active pattern including a plurality of conductive regions and a plurality of channel regions by doping the semiconductor pattern using the first conductive layer as a mask.
  • the first conductive layer may include a first gate electrode electrically connected to the connector through the first contact hole.
  • the manufacturing method may include, after the forming of the active pattern, forming a second insulating layer on the first conductive layer.
  • a second contact hole overlapping a portion of the conductive region along the direction orthogonal to the upper surface of the substrate may be formed by patterning the first insulating layer and the second insulating layer.
  • the manufacturing method may include forming a second conductive layer by stacking a conductive material on the second insulating layer and patterning the stacked conductive material.
  • the second conductive layer may include an initialization voltage line electrically connected to a portion of the conductive region through the second contact hole.
  • the second conductive layer may include a storage line including an expansion overlapping the first gate electrode along the direction orthogonal to the upper surface of the substrate with the second insulating layer disposed between the expansion and the first gate electrode to form a capacitor.
  • the capacitance of the capacitor to which a driving gate electrode is connected it is possible to sufficiently secure the capacitance of the capacitor to which a driving gate electrode is connected, and it is possible to prevent the voltage of the driving gate electrode from undesirably varying by reducing or eliminating generation of a parasitic capacitance that can be formed by using the driving gate electrode and/or a first conductor electrically connected thereto and a second conductor that is adjacent to the first conductor.
  • image quality defects such as inter-pixel color deviation and crosstalk in a display image.
  • FIG. 1 is a layout view illustrating a portion of a display device according to an exemplary embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along a line IIa-IIb of the display device illustrated in FIG. 1 .
  • FIG. 3 is a circuit diagram illustrating a pixel of a display device according to an exemplary embodiment of the present invention.
  • FIG. 4 is a timing diagram of signals applied to a display device according to an exemplary embodiment of the present invention.
  • FIG. 5 is a layout view illustrating a pixel of a display device according to an exemplary embodiment of the present invention.
  • FIG. 6 is a cross-sectional view taken along a line IVa-IVb of the pixel of the display device illustrated in FIG. 5 .
  • FIG. 7 is a cross-sectional view taken along a line Va-Vb of the pixel of the display device illustrated in FIG. 5 .
  • FIG. 8 is a layout view illustrating a pixel of a display device at a manufacturing step in a manufacturing method of a display device according to an exemplary embodiment of the present invention.
  • FIG. 9 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 8 .
  • FIG. 10 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 8 .
  • FIG. 11 is a layout view illustrating a pixel of a display device at a manufacturing step after the manufacturing step illustrated in FIG. 8 .
  • FIG. 12 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 11 .
  • FIG. 13 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 11 .
  • FIG. 14 is a layout view additionally illustrating an opening shape of a photomask used in the manufacturing step illustrated in FIG. 11 to FIG. 13 .
  • FIG. 15 is a layout view of a pixel of the display device at a manufacturing step after the manufacturing step illustrated in FIG. 11 .
  • FIG. 16 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 15 .
  • FIG. 17 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 15 .
  • FIG. 18 is a layout view illustrating a pixel of a display device at a manufacturing step after the manufacturing step illustrated in FIG. 15 .
  • FIG. 19 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 18 .
  • FIG. 20 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 18 .
  • FIG. 21 is a layout view illustrating a pixel of a display device at a manufacturing step after the manufacturing step illustrated in FIG. 18 .
  • FIG. 22 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 21 .
  • FIG. 23 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 21 .
  • FIG. 24 is a layout view illustrating a pixel of a display device at a manufacturing step after the manufacturing step illustrated in FIG. 21 .
  • FIG. 25 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 24 .
  • FIG. 26 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 24 .
  • FIG. 1 is a layout view illustrating a portion of a display device according to an exemplary embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along a line IIa-IIb of the display device illustrated in FIG. 1 .
  • FIG. 1 and FIG. 2 a display device according to an exemplary embodiment of the present invention will be described in more detail below.
  • a display device may include a substrate, such as an insulating substrate 110 .
  • a buffer layer 120 including an inorganic insulating material such as a silicon nitride (SiNx) or a silicon oxide (SiOx) and/or an organic insulating material may be disposed on the substrate 110 . At least a portion of the buffer layer 120 may be omitted, and thus at least a portion of the insulating substrate 110 (e.g., an upper surface of the insulating substrate 110 might not be covered by the buffer layer 120 .
  • An active layer 10 including a semiconductor material such as polycrystalline silicon, or an oxide semiconductor may be disposed on the buffer layer 120 .
  • the active layer 10 may include channel regions 11 c , 12 c 1 , and 12 c 2 for forming channels of transistors as semiconductors, and conductive regions 11 a , 11 b , 12 a 1 , 12 a 2 , 12 b 1 , 12 b 2 , and 13 .
  • the conductive regions 11 a , 11 b , 12 a 1 , 12 a 2 , 12 b 1 , 12 b 2 , and 13 of the active layer 10 may have a higher carrier concentration than the channel regions 11 c , 12 c 1 , and 12 c 2 .
  • the conductive regions 11 a and 11 b may be positioned on opposite sides of the channel region 11 c with the channel region 11 c positioned between the conductive regions 11 a and 11 b .
  • the conductive regions 12 a 1 and 12 b 1 may be positioned on opposite sides of the channel region 12 c 1 with the channel region 12 c 1 positioned between the conductive regions 12 a 1 and 12 b 1 .
  • the conductive regions 12 a 2 and 12 b 2 may be positioned on opposite sides of the channel region 12 c 2 with the channel region 12 c 2 positioned between the conductive regions 12 a 2 and 12 b 2 .
  • the conductive region 13 may be positioned between the conductive region 12 a 2 and the conductive region 12 a 1 , and a first end and a second end of the conductive region 13 may be connected with the conductive region 12 a 2 and the conductive region 12 a 1 , respectively.
  • the conductive region 12 a 2 and the conductive region 12 a 1 may be connected with the conductive region 13 to form one continuous conductive region such that the conductive region 12 a 2 and the conductive region 12 a 1 may be included in the conductive region 13 .
  • the conductive region 13 may be directly connected with the channel region 12 c 1 and the channel region 12 c 2 .
  • a first insulating layer 141 may be disposed on the active layer 10 .
  • the first insulating layer 141 may include an inorganic insulating material such as a silicon nitride and a silicon oxide and/or an organic insulating material.
  • the first insulating layer 141 may include a contact hole 41 formed above the conductive region 13 .
  • a conductive layer including gate conductors 21 , 22 , and 23 that are separated from each other may be disposed on the first insulating layer 141 .
  • a portion of the active layer 10 overlapping the gate conductor 21 may be the channel region 11 c
  • a portion of the active layer 10 overlapping the gate conductor 22 may be the channel region 12 c 2
  • a portion of the active layer 10 overlapping the gate conductor 23 may be the channel region 12 c 1 .
  • the channel regions 11 c and the conductive regions 11 a and 11 b connected to each may form a transistor Q 1 together with the gate conductor 21 .
  • the conductive regions 11 a and 11 b on opposite sides of the channel region 11 c may respectively serve as a source region and a drain region of the transistor Q 1 .
  • the conductive regions 12 a 1 and 12 b 1 connected to each other may form a transistor Q 2 together with the gate conductor 23 .
  • the conductive regions 12 a 1 and 12 b 1 on opposite sides of the channel region 12 c 1 may respectively serve as a source region and a drain region of the transistor Q 1 .
  • the conductive regions 12 a 2 and 12 b 2 connected to each other may form a transistor Q 3 together with the gate conductor 22 .
  • the conductive regions 12 a 2 and 12 b 2 on opposite sides of the channel region 12 c 2 may respectively serve as a source region and a drain region of the transistor Q 3 .
  • the conductive region 13 may include a portion overlapping the gate conductor 21 along a direction orthogonal to an upper surface of the insulating substrate 110 , and a portion not overlapping the gate conductor 21 along the direction orthogonal to the upper surface of the insulating substrate 110 .
  • the active layer 10 overlying the conductive layer including the gate conductors 21 , 22 and 23 may also include the conductive region 13 in addition to the channel region.
  • the gate conductor 21 may be electrically connected to the conductive region 13 of the active layer 10 through the contact hole 41 of the first insulating layer 141 .
  • the gate conductor 21 of the transistor Q 1 and the source region or the drain region of the transistor Q 2 may be electrically connected, as desired.
  • Another gate conductor 22 may be positioned between the gate conductor 21 and the source or drain region of the transistor Q 2 that are spaced apart from each other, and thus it is possible to connect the source region or the drain region of the transistor Q 2 with the gate conductor 21 by using another conductor, which is disposed on the gate conductors 21 , 22 , and 23 , as a bridge.
  • the conductive region 13 of the active layer 10 may function as a conductive connector for connecting the gate conductor 21 and the source or drain region of the transistor Q 2 .
  • a portion of the conductive region 13 may overlap the gate conductors 21 and 22 along the direction orthogonal to the upper surface of the insulating substrate 110 , and thus another channel region may be formed.
  • the conductive region 13 has conductivity either with or without overlapping the gate conductors 21 and 22 .
  • an additional doping process for forming the conductive region 13 may be added before the doping process for forming a plurality of conductive regions 11 a , 11 b , 12 a 1 , 12 a 2 , 12 b 1 , and 12 b 2 of the active layer 10 in the manufacturing process of the display device according to an exemplary embodiment of the present invention.
  • a display device may include only the gate conductor 21 and the active layer 10 .
  • a structure in which the active layer 10 positioned between the gate conductor 21 and the substrate 110 forms the conductive region 13 instead of the channel region to function as a bridge for electrically connecting the gate conductor 21 with another conductive region 12 a 1 of the active layer 10 is possible.
  • a display device according to an exemplary embodiment of the present invention will be described with reference to FIG. 3 and FIG. 4 below.
  • FIG. 3 is a circuit diagram illustrating a pixel of a display device according to an exemplary embodiment of the present invention.
  • FIG. 4 is a timing diagram of signals applied to a display device according to an exemplary embodiment of the present invention.
  • a display device may include a plurality of pixels PX for displaying images, and a plurality of signal lines 151 , 152 , 153 , 154 , 171 , and 172 .
  • One pixel PX may include a plurality of transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7 , a capacitor Cst, and at least one light emitting diode ED, connected with the signal lines 151 , 152 , 154 , 153 , 171 , and 172 .
  • one pixel PX may include one light emitting diode ED.
  • the signal lines 151 , 152 , 154 , 153 , 171 , and 172 may include a plurality of scan lines 151 , 152 , and 154 , a plurality of control lines 153 , a plurality of data lines 171 , and a plurality of driving voltage lines 172 .
  • the scan lines 151 , 152 , and 154 may respectively transfer scan signals GWn, GIn, and GI(n+1).
  • the scan signals GWn, Gin, and GI(n+1) may include a gate-on voltage and a gate-off voltage for turning the transistors T 2 , T 3 , T 4 , and T 7 included in the pixel PX on and off.
  • the scan lines 151 , 152 , and 154 connected with one pixel PX may include a first scan line 151 for transferring a scan signal GWn, a second scan line 152 for transferring a scan signal Gin having the gate-on voltage at a different time from that of the first scan line 151 , and a third scan line 154 for transferring a scan signal GI(n+1).
  • a first scan line 151 for transferring a scan signal GWn a second scan line 152 for transferring a scan signal Gin having the gate-on voltage at a different time from that of the first scan line 151
  • a third scan line 154 for transferring a scan signal GI(n+1).
  • the scan signal GWn is the n th scan signal Sn (n is a natural number of 1 or more) among scan signals applied during one frame
  • the scan signal Gin may be a previous scan signal such as an (n ⁇ 1) th scan signal S(n ⁇ 1)
  • the scan signal GI(n+1) may be an n th scan signal Sn.
  • exemplary embodiments of the present invention are not limited thereto, and the scan signal GI(n+1) may be a scan signal other than the n th scan signal Sn.
  • the control line 153 may transmit a control signal, and for example, may transmit a light emitting control signal controlling light emitting of the light emitting diode ED included in the pixel PX.
  • the control signal transferred by the control line 153 may transmit the gate-on voltage and the gate-off voltage, and may have a different waveform from the scan signal transmitted by the scan lines 151 , 152 , and 154 .
  • the data line 171 may transmit a data signal Dm, and the driving voltage line 172 may transmit a driving voltage ELVDD.
  • the data signal Dm may have different voltage levels depending on the image signal input to the display device, and the driving voltage ELVDD may have a substantially constant level.
  • the display device may further include a driver transmitting signals to each of the plurality of signal lines 151 , 152 , 153 , 154 , 171 , and 172 .
  • the transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7 included in one pixel PX may include a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4 , a fifth transistor T 5 , a sixth transistor T 6 , and a seventh transistor T 7 .
  • the first scan line 151 may transmit the scan signal GWn to the second transistor T 2 and the third transistor T 3
  • the second scan line 152 may transmit the scan signal Gin to the fourth transistor T 4
  • the third scan line 154 may transmit the scan signal GI(n+1) to the seventh transistor T 7
  • the control line 153 may transmit a light emitting control signal EM to the fifth transistor T 5 and the sixth transistor T 6 .
  • a gate electrode G 1 of the first transistor T 1 may be connected to one terminal Cst 1 of the capacitor Cst through a driving gate node GN, a source electrode S 1 of the first transistor T 1 may be connected to the driving voltage line 172 through the fifth transistor T 5 , and a drain electrode D 1 of the first transistor T 1 may be electrically connected to an anode of the light emitting diode ED via the sixth transistor T 6 .
  • the first transistor T 1 may receive a data signal Dm transmitted by the data line 171 depending on a switching operation of the second transistor T 2 to supply a driving current Id to the light emitting diode ED.
  • a gate electrode G 2 of the second transistor T 2 may be connected to the first scan line 151 , a source electrode S 2 of the second transistor T 2 may be connected to the data line 171 , and a drain electrode D 2 of the second transistor T 2 may be connected to the source electrode S 1 of the first transistor T 1 and to the driving voltage line 172 via the fifth transistor T 5 .
  • the second transistor T 2 may be turned on depending on the scan signal GWn transmitted through the first scan line 151 such that the data signal Dm transmitted from the data line 171 may be transmitted to the source electrode S 1 of the first transistor T 1 .
  • a gate electrode G 3 of the third transistor T 3 may be connected to the first scan line 151 , and a source electrode S 3 of the third transistor T 3 may be connected to the drain electrode D 1 of the first transistor T 1 and to the anode of the organic light emitting diode OLED via the sixth transistor T 6 .
  • a drain electrode D 3 of the third transistor T 3 may be connected to each of a drain electrode D 4 of the fourth transistor T 4 , one terminal Cst 1 of the capacitor Cst, and the gate electrode G 1 of the first transistor T 1 .
  • the third transistor T 3 may be turned on depending on the scan signal GWn transmitted through the first scan line 151 to diode-connect the first transistor T 1 by connecting the gate electrode G 1 and the drain electrode D 1 of the first transistor T 1 to each other.
  • a gate electrode G 4 of the fourth transistor T 4 may be connected to the second scan line 152 , a source electrode S 4 of the fourth transistor T 4 may be connected to an initialization voltage Vint, and a drain electrode D 4 of the fourth transistor T 4 may be connected to one terminal Cst 1 of the capacitor Cst and the gate electrode G 1 of the first transistor T 1 through the drain electrode D 3 of the third transistor T 3 .
  • the fourth transistor T 4 may be turned on depending on the previous scan signal Gin transmitted through the previous scan line 152 to transmit the initialization voltage Vint to the gate electrode G 1 of the first transistor T 1 , thus performing an initialization operation of initializing the voltage of the gate electrode G 1 of the first transistor T 1 .
  • a gate electrode G 5 of the fifth transistor T 5 may be connected to the control line 153 , a source electrode S 5 of the fifth transistor T 5 may be connected to the driving voltage line 172 , and a drain electrode D 5 of the fifth transistor T 5 may be connected to the source electrode S 1 of the first transistor T 1 and the drain electrode D 2 of the second transistor T 12 .
  • a gate electrode G 6 of the sixth transistor T 6 may be connected to the control line 153 , a source electrode S 6 of the sixth transistor T 6 may be connected to the drain electrode D 1 of the first transistor T 1 and the source electrode S 3 of the third transistor T 3 , and a drain electrode D 6 of the sixth transistor T 6 may be electrically connected to the anode of the organic light emitting diode ED.
  • the fifth transistor T 5 and the sixth transistor T 6 may be substantially simultaneously turned on depending on the light emitting control signal EM transmitted through the control line 153 , and thus the driving voltage ELVDD may be compensated by the diode-connected driving transistor T 1 and then may be transmitted to the light emitting diode ED.
  • a gate electrode G 7 of the seventh transistor T 7 may be connected to the third scan line 154 , a source electrode S 7 of the seventh transistor T 7 may be connected to the drain electrode D 6 of the sixth transistor T 6 and the anode of the light emitting diode (LED) ED, and a drain electrode D 7 of the seventh transistor T 7 may be connected to the terminal of the initialization voltage Vint and the source electrode S 4 of the fourth transistor T 4 .
  • the transistors T 1 , T T 3 , T 4 , T 5 , T 6 , and T 7 may be P-type channel transistors such as a PMOS, however exemplary embodiments of the present invention are not limited thereto, and at least one among the transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7 may be an N-type channel transistor.
  • One terminal Cst 1 of the capacitor Cst may be connected to the gate electrode G 1 of the first transistor T 1 as described above, and another terminal Cst 2 thereof may be connected to the driving voltage line 172 .
  • a cathode of the light emitting diode (LED) ED may be connected to a common voltage ELVSS terminal transmitting a common voltage ELVSS to receive the common voltage ELVSS.
  • the structure of the pixel PX according to an exemplary embodiment of the present invention is not limited to the structure described with reference to FIG. 1 , and a number of transistors and a number of capacitors that are included in one pixel PX and a connection relationship thereof may be variously modified, as desired.
  • a driving method of the display device will be described in more detail below with reference to FIG. 4 along with FIG. 3 .
  • An example in which the transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7 are P-type channel transistors, and an operation of one frame will be described in more detail below; however, exemplary embodiments of the present invention are not limited thereto.
  • scan signals . . . , S(n ⁇ 2), S(n ⁇ 1), Sn, . . . of a low level may be sequentially applied to the plurality of first scan lines 151 connected to the pixels PX.
  • the scan signal Gin may be an (n ⁇ 1) th scan signal S(n ⁇ 1).
  • the second transistor T 2 and the third transistor T 3 are turned on in response to the scan signal GWn of the low level.
  • the scan signal GWn may be an (n th ) scan signal Sn.
  • the first transistor T 1 is diode-connected by the turned-on third transistor T 3 and is biased in a forward direction.
  • a compensation voltage (Dm+Vth, Vth is a negative value) decreased by a threshold voltage Vth of the first transistor T 1 from the data signal Dm supplied from the data line 171 is applied to the gate electrode G 1 of the first transistor T 1 .
  • the driving voltage ELVDD and the compensation voltage (Dm+Vth) may be respectively applied to both terminals of the capacitor Cst, and the capacitor Cst may be charged with a charge corresponding to a voltage difference of both terminals.
  • the light emitting control signal EM supplied from the control line 153 is changed from the high level to the low level during a light emitting period.
  • a time when the light emitting control signal EM is changed from the high level to the low level may be after the scan signal GWn is applied to all first scan lines 151 in one frame.
  • the fifth transistor T 5 and the sixth transistor T 6 are turned on by the light emitting control signal EM of the low level, a driving current Id is generated according to the voltage difference between the gate voltage of the gate electrode G 1 of the first transistor T 1 and the driving voltage ELVDD, and the driving current Id is supplied to the light emitting diode ED through the sixth transistor T 6 , thereby a current led flows to the light emitting diode ED.
  • the seventh transistor T 7 may receive the scan signal GI(n+1) of the low level through the third scan line 154 to be turned on.
  • the scan signal GI(n+1) may be an n th scan signal Sn.
  • a part of the driving current id may flow out through the seventh transistor T 7 as a bypass current Ibp by the turned-on seventh transistor T 7 .
  • a display device according to an exemplary embodiment of the present invention will be described in more detail below with reference to FIG. 5 to FIG. 7 along with the aforementioned accompanying drawings.
  • a plane structure of the display device according to an exemplary embodiment of the present invention is firstly described and then a cross-sectional structure is described.
  • FIG. 5 is a layout view illustrating a pixel of a display device according to an exemplary embodiment of the present invention.
  • FIG. 6 is a cross-sectional view taken along a line IVa-IVb of the pixel of the display device illustrated in FIG. 5 .
  • FIG. 7 is a cross-sectional view taken along a line Va-Vb of the pixel of the display device illustrated in FIG. 5 .
  • one pixel of the display device may include the plurality of transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7 and the capacitor Cst that are each connected with at least one of the plurality of scan lines 151 , 152 , and 154 , the control line 153 , the data line 171 and the driving voltage line 172 .
  • the scan lines 151 , 152 , and 154 and the control line 153 may extend in substantially a same direction in a plan view (e.g., a first direction Dr 1 ).
  • the first scan line 151 may be positioned between the second scan line 152 and the control line 153 in the plan view.
  • the third scan line 154 which may be substantially the same as the second scan line 152 , may transfer a next scan signal GI(n+1) after the scan signal GIn transmitted by the second scan line 152 .
  • the data line 171 and the driving voltage line 172 may extend substantially in a second direction Dr 2 perpendicular to the first direction Dr 1 in the plan view, and may cross the scan lines 151 , 152 , and 154 and the control line 153 .
  • the data line 171 may transfer a data signal Dm
  • the driving voltage line 172 may transfer a driving voltage ELVDD.
  • the driving voltage line 172 may include an expansion 178 .
  • the driving voltage line 172 may include the expansion 178 in each pixel.
  • the display device may further include a storage line 156 , and an initialization voltage line 159 .
  • the storage line 156 and the initialization voltage line 159 may extend substantially in the first direction Dr 1 in the plan view.
  • the storage line 156 may be positioned between the first scan line 151 and the control line 153 in the plan view, and may include an expansion 157 .
  • the expansion 157 may be included in each pixel.
  • the expansion 157 of the storage line 156 may be connected with the expansion 178 of the driving voltage line 172 to receive a driving voltage ELVDD.
  • the initialization voltage line 159 may be positioned between the first scan line 151 and the second scan line 152 in the plan view to transfer an initialization voltage Vint, but a position of the initialization voltage line 159 is not limited thereto.
  • the scan lines 151 , 152 , and 154 and the control line 153 may be included in the first conductive layer, may be disposed in a same layer in the sectional view, and may include a same material as each other.
  • the storage line 156 and the initialization voltage line 159 may be included in the second conductive layer that is different from the first conductive layers, may be disposed in a same layer in the plan view, and may include a same material as each other.
  • the second conductive layer may be disposed on a layer above the first conductive layer.
  • the data line 171 and the driving voltage line 172 may be included in a third conductive layer that is different from the first and second conductive layers, may be disposed in a same layer in the plan view, and may include a same material as each other.
  • the third conductive layer may be disposed on a layer above the second conductive layer.
  • Each channel of the transistors T 1 , T 2 , T 3 , T 4 , T 5 , T 6 , and T 7 may be formed in one active pattern 130 , and the active pattern 130 may be bent in various shapes.
  • the active pattern 130 may include a semiconductor material such as amorphous/polycrystalline silicon or an oxide semiconductor.
  • the active pattern 130 may include a channel region which is semiconductive, and a conductive region.
  • the channel region may include at least one of channel regions 131 a , 131 b , 131 c _ 1 , 131 c _ 2 , 131 d _ 1 , 131 d _ 2 , 131 e , 131 f , and 131 g in which channels of transistors T 1 , T 2 , T 3 _ 1 , T 3 _ 2 , T 4 _ 1 , T 4 _ 2 , T 5 , T 6 , and T 7 are formed.
  • Other regions than the channel regions 131 a , 131 b , 131 c _ 1 , 131 c _ 2 , 131 d _ 1 , 131 d _ 2 , 131 e , 131 f , and 131 g may be conductive regions in the active pattern 130 .
  • the conductive regions have a higher carrier concentration than that of the channel regions 131 a , 131 b , 131 c 1 , 131 c _ 2 , 131 d _ 1 , 131 d _ 2 , 131 e , 131 f , and 131 g .
  • the conductive regions may be positioned between opposite ends of the respective channel regions 131 a , 131 b , 131 c _ 1 , 131 c _ 2 , 131 d _ 1 , 131 d _ 2 , 131 e , 131 f , and 131 g to include regions serving as source regions and drain regions of the corresponding transistors T 1 , T 2 , T 3 _ 1 , T 3 _ 2 , T 4 _ 1 , T 4 _ 2 , T 5 , T 6 , and T 7 and connectors 138 .
  • the first transistor T 1 may include a channel region 131 a , a source region 136 a and a drain region 137 a which serve as conductive regions of the active patterns 130 positioned at opposite sides of the channel region 131 a , and a driving gate electrode 155 a which overlaps the channel region 131 a in the plan view.
  • the channel region 131 a of the first transistor T 1 may be bent at least once.
  • the channel region 131 a may have a meandering shape or a zigzag shape.
  • FIG. 5 illustrates an example in which the channel region 131 a is substantially vertically inverted; however, exemplary embodiments of the present invention are not limited thereto.
  • the driving gate electrode 155 a may be included in the first conductive layer, and may be connected with the connector 138 in the conductive regions of the active pattern 130 through a contact hole 48 .
  • the connector 138 may extend substantially in the second direction Dr 2 to cross the first scan line 151 .
  • the connector 138 may be in a position corresponding to a driving gate node GN (see, e.g., FIG. 3 ) along with the driving gate electrode 155 a.
  • the second transistor T 2 may include the channel region 131 b , a source region 136 b and a drain region 137 b which serve as conductive regions of the active pattern 130 positioned at opposite sides of the channel region 131 b , and a gate electrode 155 b which overlaps the channel region 131 b in the plan view.
  • the gate electrode 155 b is a portion of the first scan line 151 .
  • the source region 136 b may be connected with the data line 171 through a contact hole 62
  • the drain region 137 b is connected with the source region 136 a of the first transistor T 1 .
  • the third transistor T 3 illustrated in FIG. 3 may include two parts for preventing a leakage current.
  • the third transistor T 3 may include a first portion T 3 _ 1 of the third transistor T 3 and a third transistor second portion T 3 _ 2 which are adjacent to each other and connected to each other.
  • the first portion T 3 _ 1 of the third transistor T 3 may include the channel region 131 c _ 1 which overlaps the first scan line 151 in the plan view, a source region 136 c _ 1 and a drain region 137 c _ 1 which are conductive regions of the active pattern 130 positioned at opposite ends of the channel region 131 c _ 1 , and a gate electrode 155 c _ 1 which overlaps the channel region 131 c _ 1 .
  • the drain region 137 c _ 1 may be connected with the driving gate electrode 155 a through the connector 138 .
  • the third transistor second portion T 3 _ 2 may include the channel region 131 c _ 2 which overlaps the first scan line 151 in the plan view, a source region 136 c _ 2 and a drain region 137 c _ 2 which are conductive regions of the active pattern 130 positioned at opposite ends of the channel region 131 c _ 2 , and a gate electrode 155 c _ 2 which overlaps the channel region 131 c _ 2 .
  • the gate electrode 155 c _ 2 is a portion of the first scan line 151 .
  • the source region 136 c _ 2 of the third transistor second portion T 3 _ 2 is connected with the drain region 137 a of the first transistor T 1 , and the drain region 137 c _ 2 is connected with the source region 136 c _ 1 of the first portion T 3 _ 1 of the third transistor T 3 .
  • the fourth transistor T 4 may also include two parts for preventing a leakage current.
  • the fourth transistor T 4 may include a first portion T 4 _ 1 of the fourth transistor T 4 and a fourth transistor second portion T 4 _ 2 which are adjacent to each other and connected to each other.
  • a first portion T 4 _ 1 of the fourth transistor T 4 may include the channel region 131 d _ 1 which overlaps the second scan line 152 in the plan view, a source region 136 d _ 1 and a drain region 137 d _ 1 which are conductive regions of the active pattern 130 positioned at opposite ends of the channel region 131 d _ 1 , and a gate electrode 155 d _ 1 which overlaps the channel region 131 d _ 1 .
  • the gate electrode 155 d _ 1 may be a portion of a protruded part of the second scan line 152 .
  • the drain region 137 d _ 1 is connected with the drain region 137 c _ 1 of the first portion T 3 _ 1 of the third transistor T 3 and the driving gate electrode 155 a through the connector 138 .
  • a second portion T 4 _ 2 of the fourth transistor T 4 may include the channel region 131 d _ 2 which overlaps the second scan line 152 in the plan view, a source region 136 d _ 2 and a drain region 137 d _ 2 which are conductive regions of the active pattern 130 positioned at opposite ends of the channel region 131 d _ 2 , and a gate electrode 155 d _ 2 which overlaps the channel region 131 d _ 2 .
  • the gate electrode 155 d _ 2 may be a portion of a protruded part of the second scan line 152 .
  • the drain region 137 d _ 2 is connected with the source region 136 d _ 1 of the first portion T 4 _ 1 of the fourth transistor T 4 , and the source region 136 d _ 2 is connected with the initialization voltage line 159 through a contact hole 47 .
  • the fifth transistor T 5 may include the channel region 131 e , a source region 136 e and a drain region 137 e which are conductive regions of the active pattern 130 positioned at opposite ends of the channel region 131 e , and a gate electrode 155 e which overlaps the channel region 131 e .
  • the gate electrode 155 e is a portion of the control line 153 .
  • the source region 136 e is connected with the driving voltage line 172 through a contact hole 67
  • the drain region 137 e is connected with the source region 136 a of the first transistor T 1 .
  • the sixth transistor T 6 may include the channel region 131 f , a source region 136 f and a drain region 137 f which are conductive regions of the active pattern 130 positioned at opposite ends of the channel region 131 f , and a gate electrode 155 f which overlaps the channel region 131 f .
  • the gate electrode 155 f is a portion of the control line 153 .
  • the source region 136 f is connected with the drain region 137 a of the first transistor T 1
  • the drain region 137 f is connected with a connecting member 179 through a contact hole 69 .
  • the connecting member 179 may be included in the third conductive layer in the plan view.
  • the seventh transistor T 7 may include the channel region 131 g , a source region 136 g and a drain region 137 g which are conductive regions of the active pattern 130 positioned at opposite ends of the channel region 131 g , and a gate electrode 155 g which overlaps the channel region 131 g .
  • the gate electrode 155 g is a portion of the third scan line 154 .
  • the source region 136 g is connected with the drain region 137 f of the sixth transistor T 6
  • the drain region 137 g is connected with the initialization voltage line 159 through the contact hole 47 to receive the initialization voltage Vint.
  • the capacitor Cst may include the driving gate electrode 155 a and the expansion 157 of the storage line 156 which overlap each other in the plan view as two terminals.
  • the capacitor Cst may maintain a voltage difference between the driving gate electrode 155 a and the expansion 157 of the storage line 156 which receives the driving voltage ELVDD.
  • the expansion 157 of the storage line 156 may have a wider area in the plan view than the driving gate electrode 155 a to cover an entire area of the corresponding driving gate electrode 155 a.
  • the connector 138 may have a first end 38 a connected with the drain region 137 c _ 1 of the first portion T 3 _ 1 of the third transistor T 3 and a second end 38 b connected with the drain region 137 d _ 1 of the first portion T 4 _ 1 of the fourth transistor T 4 .
  • the connector 138 may form one continuous conductive region together with the drain region 137 c _ 1 of the first portion T 3 _ 1 of the third transistor T 3 and the drain region 137 d _ 1 of the first portion T 4 _ 1 of the fourth transistor T 4 .
  • the active patterns 130 positioned between opposite sides with respect to each of the first end 38 a and the second end 38 b are all conductive regions, the first end 38 a and the second end 38 b might not form a boundary. However, the active patterns 130 may be positioned between opposite sides with respect to each of the first end 38 a and the second end 38 b may have different carrier concentrations.
  • the first end 38 a of the connector 138 may be located at different positions, which range from a lower outer boundary of the driving gate electrode 155 a to a boundary between the channel region 131 c _ 1 and the drain region 137 c _ 1 of the first portion T 3 _ 1 of the third transistor T 3 .
  • the connector 138 may serve as a drain region of the first portion T 3 _ 1 of the third transistor T 3 .
  • the second end 38 b of the connector 138 may be located at different positions, which range from a lower outer boundary of the first scan line 151 to a boundary between the channel region 131 d _ 1 and the drain region 137 d _ 1 of the first portion T 4 _ 1 of the fourth transistor T 4 .
  • the connector 138 may serve as a drain region of the first portion T 4 . 1 of the fourth transistor T 4 .
  • the active pattern 130 which overlaps the driving gate electrode 155 a may include the channel region 131 a and the connector 138 , and regions other than the channel region 131 a in the active pattern 130 overlapping the driving gate electrode 155 a may all be conductive regions.
  • a region of the active pattern 130 which overlaps with the first conductive layer may be mostly a channel region that is a semiconductor, but may also include a conductive region.
  • the conductive region may be used as a connector for connecting two conductors (e.g., the driving gate electrode 155 a and the drain region 137 d _ 1 ) which are separated from each other and are positioned in different layers.
  • a cross-section of the display device according to an exemplary embodiment of the present invention will be described in more detail below with reference to FIG. 6 and FIG. 7 along with FIG. 5 .
  • the display device may include the substrate 110 .
  • the substrate 110 may include an inorganic insulating material such as glass or an organic insulating material such as plastic such as polyimide (PI), and may have varying degrees of flexibility.
  • PI polyimide
  • the buffer layer 120 may be disposed on the substrate 110 .
  • the buffer layer 120 may block the transfer of impurities from the substrate 110 to an upper layer of the buffer layer 120 , for example to the active pattern 130 , thus reducing or eliminating deterioration of the active pattern 130 and relieving stress.
  • the buffer layer 120 may include an inorganic or organic insulating material such as a silicon nitride or a silicon oxide. A portion or all of the buffer layer 120 may be omitted.
  • the active pattern 130 may be disposed on the buffer layer 120 , and the first insulating layer 141 may be disposed on the active pattern 130 .
  • a first conductive layer including the scan lines 151 , 152 , and 154 , the control line 153 , and the driving gate electrode 155 a may be disposed on the first insulating layer 141 .
  • a second insulating layer 142 may be disposed on the first conductive layer and the first insulating layer 141 , and a second conductive layer including the storage line 156 , and the initialization voltage line 159 may be disposed on the second insulating layer 142 .
  • the expansion 157 of the storage line 156 may overlap the driving gate electrode 155 a along the direction orthogonal to the upper surface of the insulating substrate 110 with the second insulating layer 142 therebetween to form a capacitor Cst.
  • a third insulating layer 160 may be disposed on the second conductive layer and the second insulating layer 142 .
  • At least one of the first insulating layer 141 , the second insulating layer 142 , and the third insulating layer 160 may include an inorganic insulating material such as a silicon nitride or a silicon oxide, and/or an organic insulating material.
  • the first insulating layer 141 may include a contact hole 48 positioned above the connector 138 of the active pattern 130 .
  • the first and second insulating layers 141 and 142 may include a contact hole 47 positioned above the drain region 137 g of the seventh transistor T 7 .
  • the first, second, and third insulating layers 141 , 142 , and 160 may include a contact hole 62 positioned above the source region 136 b of the second transistor T 2 .
  • a contact hole 67 may be positioned above the source region 136 e of the fifth transistor T 5
  • a contact hole 69 may be positioned above the drain region 137 f of the sixth transistor T 6 .
  • the third insulating layer 160 may include a contact hole 68 positioned above the expansion 157 of the storage line 156 .
  • the third conductive layer including the data line 171 , the driving voltage line 172 , and the connecting member 179 may be disposed on the third insulating layer 160 .
  • At least one of the first conductive layer, the second conductive layer, and the third conductive layer may include a conductive material such as a metal, e.g., copper (Cu), aluminum (AI), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy of at least two thereof.
  • a metal e.g., copper (Cu), aluminum (AI), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy of at least two thereof.
  • a passivation layer 180 may be disposed on the third conductive layer and the third insulating layer 160 .
  • the passivation layer 180 may include an organic insulating material such as a polyacryl-based resin or a polyimide-based resin, and a top surface of the passivation layer 180 may be substantially flat.
  • the passivation layer 180 may have a contact hole 89 formed in the connecting member 179 .
  • a fourth conductive layer including a plurality of pixel electrodes 191 may be disposed on the passivation layer 180 .
  • Each of the pixel electrodes 191 may be connected with the connecting member 179 through the contact hole 89 to receive a voltage.
  • the pixel electrodes 191 may be arranged in a pentile matrix structure.
  • a pixel definition layer (PDL) 350 may be disposed on the passivation layer 180 and the pixel electrode 191 .
  • the pixel definition layer 350 may include an opening 351 in each of the pixel electrodes 191 .
  • An emission layer 370 may be disposed on the pixel electrodes 191 .
  • the emission layer 370 may be positioned in the opening 351 .
  • the emission layer 370 may include an organic light emitting material or an inorganic light emitting material.
  • a common electrode 270 may be disposed on the emission layer 370 .
  • the common electrode 270 may also be formed on the pixel definition layer 350 to extend over a plurality of pixels.
  • the pixel electrode 191 , the emission layer 370 , and the common electrode 270 together may form a light emitting diode ED.
  • An encapsulation layer protecting the light emitting diode ED may be disposed on the common electrode 270 .
  • the encapsulation layer may include an inorganic layer and an organic layer which are alternately stacked.
  • a connecting member may electrically connect the driving gate electrode 155 a of the first transistor T 1 with the conductive region of the active pattern 130 (e.g., the drain region 137 d _ 1 of the first portion T 4 _ 1 of the fourth transistor) which are spaced apart from each other.
  • a conductor may be positioned between the driving gate electrode 155 a and the drain region 137 d _ 1 of the first portion T 4 _ 1 of the fourth transistor T 4 , such as the first scan line 151 .
  • the connecting member may cross the conductor and is insulated from to conductor.
  • the connecting member connecting the driving gate electrode 155 a with the drain region 137 d _ 1 of the first portion T 4 _ 1 of the fourth transistor T 4 may be positioned in a conductive layer disposed on the driving gate electrode 155 a .
  • the driving gate electrode 155 a overlaps the expansion 157 of the storage line 156 to form a capacitor Cst, and thus the connecting member is mainly disposed in a third conductive layer which is disposed at a different layer from that of the storage line 156 .
  • the connecting member is connected to the driving gate electrode 155 a through an opening formed in the expansion 157 of the storage line 156 .
  • an area of the expansion 157 may be reduced and the capacitance of the capacitor Cst may be reduced accordingly and the maintaining ability of the voltage of the driving gate electrode 155 a may be reduced. Further, a margin capable of reducing a pixel size may be reduced by an opening that is formed in the expansion 157 , and thus it may be difficult to manufacture a high-resolution display device.
  • the connecting member for connecting the driving gate electrode 155 a with the drain region 137 d _ 1 of the first portion T 4 _ 1 of the fourth transistor T 4 is disposed in the third conductive layer, a coupling capacitor may be generated between the connecting member and the fourth conductive layer such as the pixel electrode 191 thereabove.
  • color deviation may occur when deviation of the coupling capacitor occurs based on pixels.
  • the connecting member disposed in the third conductive layer may be relatively close to another third conductive layer such as the data line 171 , and thus a capacitance of the coupling capacitor between the driving gate node GN and the adjacent data line 171 may become relatively large.
  • a voltage of the driving gate electrode 155 a may be changed depending on a change of the data signal Dm, thus generating crosstalk, or signal contamination.
  • the connector 138 which is a portion of the active pattern 130 may connect the driving gate electrode 155 a with the drain region 137 d _ 1 of the first portion T 4 _ 1 of the fourth transistor.
  • a connecting member in the third conductive layer may be omitted, without an occurrence of side effects.
  • sufficient capacitance of the capacitor Cst can be achieved, a high-resolution display device can be realized, and the generation of color defects and image quality defects such as crosstalk can be reduced or eliminated.
  • the source region 136 d _ 2 of the fourth transistor T 4 and the drain region 137 g of the seventh transistor T 7 are connected to the initialization voltage line 159 .
  • an additional connecting member may be formed at a different layer from the active pattern 130 and the second conductive layer. According to an exemplary embodiment of the present invention, however, it is possible to connect the source region 136 d _ 2 of the fourth transistor T 4 and the drain region 137 g of the seventh transistor T 7 with an initialization voltage line 159 through a contact hole 47 , by allowing the active pattern 130 and the initialization voltage line 159 to overlap each other in the plan view and forming the contact hole 47 in the first and second insulating layers 141 and 142 .
  • a manufacturing method of a display device according to an exemplary embodiment of the present invention will be described in more detail below with reference to FIG. 8 to FIG. 26 along with the aforementioned drawings.
  • FIG. 8 is a layout view illustrating a pixel of a display device at a manufacturing step in a manufacturing method of a display device according to an exemplary embodiment of the present invention.
  • FIG. 9 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 8 .
  • FIG. 10 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 8 .
  • an inorganic insulating material and/or an organic insulating material may be stacked on the substrate 110 to form the buffer layer 120 .
  • a semiconductor material such as polycrystalline silicon or an oxide semiconductor may be stacked on the buffer layer 120 and patterned to form a semiconductor pattern 130 A.
  • the patterning process may include a photolithography process in which a photoresist is stacked on a target layer, a mask pattern is formed through an exposure and development process using a photomask, and then a target layer is etched.
  • An overall planar shape of the semiconductor pattern 130 A may be substantially the same as the planar shape of the active pattern 130 described above.
  • FIG. 11 is a layout view illustrating a pixel of a display device at a manufacturing step after the manufacturing step illustrated in FIG. 8 .
  • FIG. 12 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 11 .
  • FIG. 13 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 11 .
  • FIG. 14 is a layout view additionally illustrating an opening shape of a photomask used in the manufacturing step illustrated in FIG. 11 to FIG. 13 .
  • a photosensitive layer such as a photoresist may be stacked on the semiconductor pattern 130 A, and then exposed and developed to form a mask pattern 500 including an opening OP.
  • the opening OP may include an area corresponding to the connector 138 of the active pattern 130 described above.
  • the boundary line SA 1 may be in a position corresponding to a lower outer boundary line of the driving gate electrode 155 a to be formed later, and a boundary line SB 1 may be in a position corresponding to a boundary line between the channel region 131 c _ 1 and the drain region 137 c _ 1 of the third transistor first portion T 3 _ 1 to be formed later.
  • a position of the second end 38 b of the connector 138 may be changed according to the shape of the opening OP of the mask pattern 500 , and may range between, e.g., boundary lines SA 2 and SB 2 described with reference to FIG. 11 .
  • the boundary line SA 2 may be in a position corresponding to a lower outer boundary line of the first scan line 151 to be formed later, and the boundary line SB 2 may be in a position corresponding to a boundary line between the channel region 131 d _ 1 and the drain region 137 d _ 1 of the fourth transistor first portion T 41 to be formed later.
  • the shape of the opening OP of the mask pattern 500 may be variously changed depending on a region of the connector 138 to be formed.
  • a minimum area of an opening OP 1 of the mask pattern 500 according to an exemplary embodiment of the present invention may have an edge aligned with the boundary line SA 2 and the boundary line SA 1 described with reference to FIG. 11 and FIG. 14 .
  • a maximum area of the opening OP 2 of the mask pattern 500 according to an exemplary embodiment of the present invention may have an edge aligned with the boundary line SB 2 and the boundary line SB 1 described with reference to FIG. 11 and FIG. 14 .
  • FIG. 15 is a layout view of a pixel of the display device at a manufacturing step after the manufacturing step illustrated in FIG. 11 .
  • FIG. 16 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 15 .
  • FIG. 17 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 15 .
  • a first insulating layer 141 may be formed by stacking an inorganic insulating material such as a silicon nitride or a silicon oxide and/or an organic insulating material on the semiconductor pattern 130 A, and the first insulating layer 141 may be patterned to form a contact hole 48 above the connector 138 .
  • FIG. 18 is a layout view illustrating a pixel of a display device at a manufacturing step after the manufacturing step illustrated in FIG. 15 .
  • FIG. 19 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 18 .
  • FIG. 20 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 18 .
  • a first conductive layer including a plurality of scan lines 151 , 152 , and 154 , the control line 153 , and the driving gate electrode 155 a may be formed by stacking a conductive material such as a metal, e.g., copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy of at least two thereof on the first insulating layer 141 and patterning it.
  • the driving gate electrode 155 a is electrically connected to the connector 138 through the contact hole 48 .
  • the semiconductor pattern 130 A may be doped with N-type or P-type impurities by using the first conductive layer as a mask to form remaining conductive regions, thus completing the active pattern 130 as described above.
  • FIG. 21 is a layout view illustrating a pixel of a display device at a manufacturing step after the manufacturing step illustrated in FIG. 18 .
  • FIG. 22 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 21 .
  • FIG. 23 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 21 .
  • an inorganic insulating material such as a silicon nitride or a silicon oxide and/or an organic insulating material may be stacked on the first insulating layer 141 and the first conductive layer to form the second insulating layer 142 .
  • the contact hole 47 positioned above the source region 136 d _ 2 of the second portion T 4 _ 2 of the fourth transistor T 4 or the drain region 137 g of the seventh transistor T 7 may be formed by patterning the first and second insulating layers 141 and 142 by a photolithography process or the like.
  • FIG. 24 is a layout view illustrating a pixel of a display device at a manufacturing step after the manufacturing step illustrated in FIG. 21 .
  • FIG. 25 is a cross-sectional view taken along a line VIa-VIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 24 .
  • FIG. 26 is a cross-sectional view taken along a line VIIa-VIIb of the pixel of the display device according to the manufacturing step illustrated in FIG. 24 .
  • a second conductive layer including a storage line 156 and an initialization voltage line 159 may be formed by stacking a conductive material such as a metal, e.g., copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy of at least two thereof on the second insulating layer 142 and patterning it.
  • the initialization voltage line 159 may be electrically connected to the drain region 137 g of the seventh transistor T 7 or the source region 136 d _ 2 of the second portion T 4 _ 2 of the fourth transistor T 7 through the contact hole 47 .
  • an inorganic insulating material and/or an organic insulating material may be stacked on the second insulating layer 142 and the second conductive layer to form a third insulating layer 160 .
  • the contact hole 62 positioned above the source region 136 b of the second transistor T 2 , the contact hole 67 positioned above the source region 136 e of the fifth transistor T 5 , the contact hole 69 positioned above n the drain region 137 f of the sixth transistor T 6 , and the contact hole 68 positioned above the expansion 157 of the storage line 156 may be formed by patterning the first insulating layer 141 , the second insulating layer 142 , and the third insulating layer 160 .
  • a third conductive layer including the data line 171 , the driving voltage line 172 , and the connecting member 179 may be formed by stacking a conductive material such as a metal, e.g., copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy of at least two thereof on the third insulating layer 160 and patterning it.
  • a conductive material such as a metal, e.g., copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), or an alloy of at least two thereof on the third insulating layer 160 and patterning it.
  • the passivation layer 180 including the contact hole 89 positioned above the connecting member 179 may be formed by stacking an organic insulating material or the like on the third conductive layer and the third insulating layer 160 and patterning it.
  • a conductive material such as ITO may be stacked on the passivation layer 180 and patterned to form a fourth conductive layer including the pixel electrode 191 .
  • the pixel definition layer 350 is formed on the pixel electrode 191 and the passivation layer 180 , and the emission layer 370 and the common electrode 270 may be formed to form the light emitting diode ED.
  • an encapsulation layer protecting the light emitting diode ED may be formed.

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