US10217679B2 - Method for positioning a carrier with electronic components and electronic component produced with such method - Google Patents

Method for positioning a carrier with electronic components and electronic component produced with such method Download PDF

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Publication number
US10217679B2
US10217679B2 US15/027,712 US201415027712A US10217679B2 US 10217679 B2 US10217679 B2 US 10217679B2 US 201415027712 A US201415027712 A US 201415027712A US 10217679 B2 US10217679 B2 US 10217679B2
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carrier
solder
electronic components
solder mask
processing
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US20160240445A1 (en
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Jurgen Hendrikus Gerhardus Huisstede
Mark Hermans
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Besi Netherlands BV
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Besi Netherlands BV
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Assigned to BESI NETHERLANDS B.V. reassignment BESI NETHERLANDS B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUISSTEDE, JURGEN HENDRIKUS GERHARDUS, HERMANS, MARK
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bonding area, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a method of processing a carrier with electronic components, comprising the method steps: detecting at least one carrier related reference; processing the at least one detected carrier related reference into a position of the carrier and processing the solder masked carrier with electronic components.
  • the invention also relates to an electronic component produced with such a method.
  • the manufacturing electronic components usually takes place in larger quantities by making use of units of electronic components wherein the electronic components are integrated in/on larger component carriers.
  • a solder mask is applied to the carriers. After applying a solder mask normally contact elements like wires (or as an alternative small solder balls at BGA's) are attached to the electronic components (e.g. by “wire bounding” or “solder bathing”) while the electronic components are still integrated by/on the carrier.
  • the carrier which can also be seen as plural electronic component unit, may subsequently be processed to split up the larger number of combined electronic components into smaller units of one or several individual electronic components (this process is also referred to as separation, singulation or individualisation) or to at least partially isolate the electronic components.
  • Product examples are packages with a plurality of encapsulated electronic components placed on a carrier, and wafers consisting of a silicon carrier on which are arranged electronic components divided into smaller units.
  • the isolation or separation of the electronic components can be realized by means of different types of processes, such as machining (e.g. sawing with blades, liquids or light). This process enables the production of large numbers of electronic components but due to, among others, the trend of miniaturisation of the electronic components demands toward the required process precision increase and thus the demand arises to higher precision processing.
  • the US patent application 2005/0001299 discloses a substrate for a semiconductor package and a wire bonding method using such semiconductor package.
  • the wire bonding method not only calculates a changed wire bounding coordinate but also includes the steps of providing a substrate which includes one or more reference marks, imaging these reference marks and, calculating a solder mask shift. The calculated solder mask shift enables to calculate new wire bounding coordinates.
  • the present invention has for its object to however provide an alternative method of processing carriers with electronic components that enable to process the carriers with more accuracy.
  • the invention provides for this purpose a method of processing a solder masked carrier with electronic components, comprising the method steps: A) detecting at least one carrier related reference; B) processing the at least one detected carrier related reference into a position of the carrier; C) detecting a least one solder mask dependent reference; D) processing the at least one detected solder mask dependent reference into a position of the solder mask on the carrier; and E) processing the solder masked carrier with electronic components dependent on at least the position of the solder mask on the carrier, wherein the processing of the solder masked carrier with electronic components according step E) comprises the separation of the solder masked electronic components.
  • a carrier related reference is also referred to in the art as a “fiducial” or a “fiducial point” and is used as a point of reference in X-Y directions for imaging systems.
  • Common types of “fiducials” are graphical signs on a carrier (such as a BGA) and which is provided often tens of times on a single carrier.
  • solder mask references indicating the position of the solder mask can be named “fiducials”. Examples of solder mask position related “fiducials” are openings in a solder mask providing a vision system access to the underlying pattern in combination with the solder mask opening boundaries which enables to link the position of the solder mask to the carrier.
  • the processing accuracy of the solder masked board was dependent on the detected carrier related references (which references are often integrated placed with lining (wiring) on the board in combination with the outline of the carrier.
  • the processing accuracy of the solder masked board is thus independent of the actual position of the solder mask applied on the board. This provides evident benefits during further processing of the electronic component, since the solder mask is now outlined with the environment, e.g. the printed circuit board, it has to cooperate with.
  • One of the insights of the present invention is also that the solder mask position could also be important for accurate partial of complete separation of the electronic components (or groups of electronic components) of the solder masked board.
  • the isolation/separation may according the present invention be optimised to use the accurate information obtained in earlier stages of the manufacturing process of the electronic components for a later stage (step) in the processing of the electronic components.
  • the acquired accurate position information by calculating a solder mask shift was only used for wire bounding as for that processes there is a direct link between the solder mask position and the locations where wires have to be bounded.
  • the present invention however also uses the accurate position information of the solder mask shift for a subsequent production step in which strep position information acquired earlier in the process is normally lost and has to be generated again.
  • solder mask shift information of the earlier stages of the production process is utilised again in a subsequent processing step without any requirement of maintaining a specific accuracy in the product handling in between the relevant production steps. So even if the positon of the electronic components before the separation step is partially or totally lost (and thus has to be at least partially generated again) still the generated information of the solder mask shift may be used to enhance the accuracy of the separation process.
  • To use the high precision solder mask shift data in a later production stage that has from origin less requirements relating the accuracy than the earlier wire bounding step is the insight of the present invention. While in the process of successive production steps detailed information of the orientation of the product got lost now the high detailed orientation information of the solder mask on the carrier is re-used in a subsequent production step.
  • solder mask shift An example of such wiring detection is the detection of “bus lines” on semiconductor carriers. These “bus lines” provide electronic connections between the semiconductors that should be severed in a later process. In case of inaccuracy in the positioning of these “bus lines” later isolation of the semiconductors could be frustrated leading to higher rejection levels.
  • the inaccuracy of the solder mask positioning on the carrier can according the present invention however be taken out of the processing accuracy of the solder masked board. Leading towards higher product quality and less rejections. This is a feed forward process to enhance the over all accuracy.
  • a further advantage relates the possibility according the present invention to enhance the process accuracy by feed back correction on the solder mask applying process. In case of a returning solder mask shift the solder mask applying process can be corrected feed back providing more accurate subsequent products.
  • the processing steps A) and C) are combined in a single detection step.
  • a single detection step E.g. when detecting non solder mask-covered parts of a reference (“fiducial”) on the carrier after the solder mask has been applied on the carrier the position of the carrier (or carrier related elements like electronic components and/or wiring) can be determined in combination with the position of the solder mask. With such a combined measurement the solder mask shift can thus also be determined with only a single detection step. This further simplifies the method of processing a carrier with electronic components according the present invention.
  • solder mask position directly affects the step of attaching contacts to the solder masked carrier as the position of the solder mask may often dictate the position of the contacts attached.
  • An example is the attachment of contact balls (solder balls) as for instance is required for BGA's (Ball Grid Array boards) which may also be dictated by the solder mask position.
  • a solder mask shift may thus lead to a ball shift.
  • the option of measurement of ball position afterwards is of coarse also an option to enhance the processing accuracy but it is far more difficult to have an accurate visual ball position measurement (due to among others the 3D shape of the balls and the variations in shape and size of the individual balls) than an accurate visual solder mask position measurement.
  • the present invention also provides the option that the processing of the solder masked carrier with electronic components according step E) is steered dependent on the processed position of the solder mask on the carrier according step D).
  • Such steering is to be understood as a feed forward steering in that in subsequent processes adaptations can be made on product level to compensate detected individual solder mask shifts.
  • new carrier and/or solder mask dependent references are detected in subsequent manipulations during the processing of the solder masked carrier with electronic components according step E).
  • solder masked carrier may be lighted with co-axial light.
  • co-axial is to be understood as parallel to the line of detection. With such co-axial lighting the solder mask (dependent on the solder mask properties) the detection feasibility increases.
  • the invention also provides an electronic component as produced with the method according the present invention and as clarified above.
  • FIGS. 1A and 1B perspective views on carriers with electronic components before and after a solder mask has been applied onto the carrier;
  • FIGS. 2A and 2B top view on a detail of a carrier related reference and a solder mask dependent reference
  • FIGS. 3A-3C side views, on a carrier with electronic components, once before a solder mask has been applied onto the carrier, and twice after solder mask have been applied as well as solder balls have been attached;
  • FIG. 4 a top view of a solder mask applied to a carrier with electronic components
  • FIGS. 5A-5C show different mutual positions of a component and a PCB after separation but prior to further processing.
  • FIG. 1A shows a perspective view on carrier 1 which is provided from a pattern 2 of wiring and contact pads (seen only in general and indicated by the grey area's 3 ). On the carrier 1 are also carrier related references 4 that are often affixed together with the wiring and contact pads. In FIG. 1A is also shown that a vision camera 5 detects the carrier related references 4 .
  • FIG. 1B shows a perspective view on the carrier 1 from FIG. 1A but now after a solder mask 6 has been added to the carrier 1 leaving locally only minor openings free to enable the placing of contacts as will be explained in connection to FIGS. 3A-3C and 4 .
  • a vision camera 7 is shown now for the detection of solder mask dependent references as will be explained in connection to FIG. 2B .
  • the present invention also covers the detection of the carrier related references 4 after the solder mask 6 has been added to the carrier 1 . In practise this will even be more usual than the detecting the carrier related references 4 before the solder mask 6 has been added to the carrier 1 .
  • FIG. 2A shows a top view on a carrier related reference 10 by the detection of which information gets available on the position of a carrier 11 on which the carrier related reference 10 is placed.
  • FIG. 2B shows in top view a reference 12 which is placed on a carrier 13 but which is partially covered by a solder mask 14 . In the solder mask 14 an opening 15 is left blank.
  • a solder mask dependent reference is obtained however as explained already in reference to FIGS. 1A and 1B it is also possible according the present invention to detect the carrier related reference 10 after the carrier 13 is partially covered by the solder mask 14 .
  • FIG. 3A shows a side view on a carrier 20 with a contact pad 21 .
  • a solder mask 22 is placed on the carrier 20 and a (solder) ball 23 is subsequently placed on top of the contact pad 21 .
  • a solder mask 24 is placed on the same carrier 20 and also here a (solder) ball 25 is subsequently placed on top of the contact pad 21 .
  • the solder mask 22 in FIG. 3C is placed more to the left than the solder mask 24 in FIG. 3C .
  • Dependent on the specific measurements the position of the solder mask 22 , 24 may also influence the position of the solder balls 23 , 25 .
  • FIG. 3B is placed more to the left than the solder ball 25 shown in FIG. 3C as the openings in the solder masks 22 , 24 are such that they dictate the position of the balls.
  • FIGS. 3B and 3C show that knowledge of the relative position of the solder masks 22 and 24 provides information on the subsequent positioning of solder balls 23 , 25 .
  • FIG. 4 shows a top view of a solder mask 30 applied to a carrier 31 with electronic components.
  • the solder mask 30 is provided with a grid of apertures 32 that are open to accept solder balls (not shown here) to be place.
  • the X/Y positioning of the solder mask 30 may thus be relevant for the positioning of solder balls still to be placed in the situation as shown in FIG. 4 .
  • FIGS. 5A-5C show different mutual positions of a component and a PCB, prior to further processing.
  • FIG. 5A shows a theoretical optimal position of a component 40 with solder balls 41 , correctly positioned with respect to contact pads 42 .
  • FIG. 5B shows a practical situation, wherein there is a difference 43 between the centre of the solder ball 41 ′ and the contact pad 42 .
  • the difference 43 logically also occurs between the solder ball 41 ′ and the contact pad 45 of a PCB 44 , that is outlined with the component, without applying an anticipating correction according to the present invention.
  • FIG. 5C shows that, with the anticipation correction according to the present invention, solder ball 41 ′ and PCB contact pad 45 are correctly outlined.
  • inaccuracies in the positioning of the solder mask to the carrier are detected and as far as the influence the accuracy of the processing of the solder masked board can be compensated in the processing of the solder masked carrier.
  • An example of such wiring detection is the detection of “bus lines” on semiconductor carriers. These “bus lines” provide electronic connections between the semiconductors that should be severed in a later process. In case of inaccuracy in the positioning of these “bus lines” later isolation of the semiconductors could be frustrated leading to higher rejection levels.
  • the inaccuracy of the solder mask positioning on the carrier (also referred to as solder mask shift) can according the present invention however be taken out of the processing accuracy of the solder masked board.
US15/027,712 2013-10-08 2014-10-08 Method for positioning a carrier with electronic components and electronic component produced with such method Active 2034-12-17 US10217679B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
NL2011575A NL2011575C2 (en) 2013-10-08 2013-10-08 Method for positioning a carrier with electronic components and electronic component produced with such method.
NL2011575 2013-10-08
PCT/NL2014/050702 WO2015053628A1 (en) 2013-10-08 2014-10-08 Method for positioning a carrier with electronic components and electronic component produced with such method

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US20160240445A1 US20160240445A1 (en) 2016-08-18
US10217679B2 true US10217679B2 (en) 2019-02-26

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US (1) US10217679B2 (de)
JP (1) JP6697381B2 (de)
KR (1) KR102302345B1 (de)
CN (1) CN105580122B (de)
DE (1) DE112014004627B4 (de)
MX (1) MX354806B (de)
MY (1) MY186603A (de)
NL (1) NL2011575C2 (de)
PH (1) PH12016500469A1 (de)
SG (1) SG11201601577TA (de)
TW (1) TWI660437B (de)
WO (1) WO2015053628A1 (de)

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US9781362B1 (en) * 2016-03-22 2017-10-03 Omnivision Technologies, Inc. Flare-reducing imaging system and associated image sensor

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US6003753A (en) 1997-07-14 1999-12-21 Motorola, Inc. Air-blow solder ball loading system for micro ball grid arrays
US6671397B1 (en) 1998-12-23 2003-12-30 M.V. Research Limited Measurement system having a camera with a lens and a separate sensor
EP1259103A1 (de) 2000-02-25 2002-11-20 Ibiden Co., Ltd. Mehrschichtige leiterplatte und verfahren zu ihrer herstellung
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US20030000738A1 (en) 2001-06-25 2003-01-02 Rumsey Brad D. Solder resist opening to define a combination pin one indicator and fiducial
US20050001299A1 (en) 2003-07-04 2005-01-06 Amkor Technology, Inc. Substrate for semiconductor package wire bonding method using thereof
JP2005032910A (ja) 2003-07-10 2005-02-03 Renesas Technology Corp 半導体装置の製造方法およびそれに用いられる半導体製造装置
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