TWI840470B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI840470B
TWI840470B TW108145634A TW108145634A TWI840470B TW I840470 B TWI840470 B TW I840470B TW 108145634 A TW108145634 A TW 108145634A TW 108145634 A TW108145634 A TW 108145634A TW I840470 B TWI840470 B TW I840470B
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TW
Taiwan
Prior art keywords
pad
heat sink
pattern
chip
semiconductor package
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TW108145634A
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English (en)
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TW202038401A (zh
Inventor
金知晃
沈鍾輔
李章雨
孔永哲
玄榮勳
Original Assignee
南韓商三星電子股份有限公司
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Publication of TW202038401A publication Critical patent/TW202038401A/zh
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Publication of TWI840470B publication Critical patent/TWI840470B/zh

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Abstract

一種半導體封裝包括下部結構、位於下部結構上的上部結構以及位於下部結構與上部結構之間的連接圖案。連接圖案被配置成將下部結構與上部結構電性連接至彼此。下部結構包括下部基底及位於下部基底上的第一下部晶片。第一下部晶片包括晶片接合接墊、接墊結構及熱沉結構。連接圖案連接至上部結構，遠離上部結構延伸以連接至接墊結構。接墊結構的厚度大於晶片接合接墊的厚度。熱沉結構的至少一部分與接墊結構的至少一部分處於相同的高度水平。

Description

半導體封裝
本發明概念的例示性實施例是有關於半導體封裝，且更具體而言有關於包括一或多個熱沉（heat sink）結構的半導體封裝。 [相關申請案的交叉參考]
本申請案主張於2018年12月14日在韓國智慧財產局中提出申請的韓國專利申請案第10-2018-0161564號的優先權權益，所述韓國專利申請案的揭露內容全文併入本案供參考。
隨著對包括電子裝置在內的電子產品的高容量、薄化及小型化的需求的增加，已開發出不同類型的半導體封裝。在此種不同類型的半導體封裝中，已開發出用於在單一封裝中包含多個晶片的封裝技術。在一些情形中，在包含多個晶片的半導體封裝內產生的熱量可能難以釋放至半導體封裝的外部。因此，此種熱量的產生可能導致封裝效能等降級。
本發明概念的態樣旨在提供一種具有改進的熱沉特性的半導體封裝。
根據一些例示性實施例，一種半導體封裝可包括下部結構、位於所述下部結構上的上部結構以及位於所述下部結構與所述上部結構之間的連接圖案。所述下部結構可包括下部基底及位於所述下部基底上的第一下部晶片。所述第一下部晶片可包括晶片接合接墊、接墊結構及熱沉結構。所述接墊結構的厚度可大於所述晶片接合接墊的厚度。所述熱沉結構的至少一部分可與所述接墊結構的至少一部分處於相同的高度水平。所述連接圖案可被配置成將所述下部結構與所述上部結構電性連接至彼此。所述連接圖案可連接至所述上部結構。所述連接圖案可遠離所述上部結構延伸以連接至所述接墊結構。
根據一些例示性實施例，一種半導體封裝可包括下部結構、位於所述下部結構上的上部結構以及位於所述下部結構與所述上部結構之間的連接圖案。所述下部結構可包括下部基底、位於所述下部基底上的下部晶片及位於所述下部基底上的下部模具層，使得所述下部模具層覆蓋所述下部晶片。所述下部晶片可包括接墊結構及熱沉結構。所述熱沉結構的至少一部分可與所述接墊結構的至少一部分處於相同的高度水平。所述下部模具層所具有的頂表面的高度水平可高於所述接墊結構的頂表面及所述熱沉結構的頂表面二者。所述下部模具層可具有第一開口，所述第一開口延伸穿過所述下部模具層的至少一部分以暴露出所述接墊結構的所述頂表面的至少一部分。所述連接圖案可被配置成將所述下部結構與所述上部結構電性連接至彼此。所述連接圖案可連接至所述上部結構。所述連接圖案可遠離所述上部結構延伸，以連接至所述接墊結構的所述頂表面的藉由所述第一開口暴露出的所述部分。
根據一些例示性實施例，一種半導體封裝可包括下部結構、位於所述下部結構上的上部結構以及位於所述下部結構與所述上部結構之間的連接圖案。所述下部結構可包括下部基底、位於所述下部基底上的第一下部晶片、位於所述第一下部晶片與所述下部基底之間的第二下部晶片以及覆蓋所述第一下部晶片的下部模具層。所述第一下部晶片可包括基板、位於所述基板上的晶片接合接墊、接墊結構及熱沉結構。所述熱沉結構的至少一部分可與所述接墊結構的至少一部分處於相同的高度水平。所述下部模具層所具有的頂表面的高度水平可高於所述接墊結構的頂表面及所述熱沉結構的頂表面二者。所述下部模具層可具有第一開口，所述第一開口延伸穿過所述下部模具層的至少一部分以暴露出所述接墊結構的所述頂表面的至少一部分。所述上部結構可被隔離而免於與所述下部結構直接接觸。所述連接圖案可被配置成將所述下部結構與所述上部結構電性連接至彼此。所述連接圖案可被配置成將所述接墊結構的所述頂表面的所述部分與所述上部結構連接至彼此。
在下文中，將參照圖1、圖2、圖3及圖4闡述根據本發明概念一些例示性實施例的半導體封裝的例子。圖1是示出根據本發明概念一些例示性實施例的半導體封裝的例子的剖視圖，圖2是示出根據本發明概念一些例示性實施例的半導體封裝的一些組件的例子的平面圖，圖3是示出設置於圖2中部分「A」的放大區域中的一些組件的例子的放大圖，圖4A是沿圖3中的線I-I'、II-II'及III-III'截取的區域的局部放大剖視圖，且圖4B是沿圖3中的線IV-IV'截取的區域的局部放大剖視圖。
參照圖1至圖4，半導體封裝1可包括下部結構10a、位於下部結構10a上（例如，上方）的上部結構110a以及位於下部結構10a與上部結構110a之間的連接圖案140。
將理解，位於另一元件「上」的元件可位於另一元件上方或下方。另外，位於另一元件「上」的元件可與另一元件直接接觸，或者可藉由一或多個中介空間及/或結構進行隔離而免於與另一元件直接接觸。
將進一步理解，本文中被闡述為連接至另一元件的元件可直接接觸另一元件或可直接連接至另一元件。本文中被闡述為連接至另一元件的元件可電性連接及/或物理連接至另一元件。本文中被闡述為電性連接至另一元件的元件可直接物理連接至另一元件。本文中被闡述為物理連接至另一元件的元件可電性連接至另一元件。本文中被闡述為將兩個或更多個元件電性連接於一起的元件可將所述兩個或更多個元件物理連接於一起。本文中被闡述為將兩個或更多個元件物理連接於一起的元件可將所述兩個或更多個元件電性連接於一起。本文中被闡述為將兩個或更多個元件連接於一起的元件可將所述兩個或更多個元件電性連接及/或物理連接於一起。
如至少在圖1中所示，下部結構10a可包括下部基底15及位於下部基底15上（例如，上方）的第一下部晶片25。
第一下部晶片25可包括晶片接合接墊34、接墊結構37及熱沉結構44a。接墊結構37可包括第一接墊39及位於第一接墊39上的第二接墊41。接墊結構37的厚度37T可大於晶片接合接墊34的厚度34T。第二接墊41的厚度可大於第一接墊39的厚度。晶片接合接墊34可設置於與第一接墊39相同的水平高度（「相同的高度水平」）上，且可包含與第一接墊39相同的材料。第一下部晶片25可更包括位於基板28上的重佈線53，其中重佈線53被配置成將晶片接合接墊34與接墊結構37電性連接至彼此。如至少在圖3中所示，重佈線53可被配置成將第一接墊39與晶片接合接墊34電性連接至彼此。
熱沉結構44a的至少一部分可設置於與接墊結構37的至少一部分相同的水平高度上。
在一些例示性實施例中，用語「水平高度」可指相對於某一基準（例如，下部基底15的頂表面15u或基板28的頂表面28u）的高度水平。因此，在下文中，即使未另外闡述，用語「水平高度」亦將被理解為相對於某一基準的高度水平。
熱沉結構44a可包括熱沉圖案。熱沉結構44a的熱沉圖案可包含與接墊結構37的第一接墊39、第二接墊41或者第一接墊39和第二接墊41二者相同的材料。舉例而言，熱沉結構44a可包括第一熱沉圖案46及位於第一熱沉圖案46上的第二熱沉圖案48。熱沉結構44a的至少一部分可與接墊結構37的至少一部分處於相同的高度水平。熱沉結構44a可包括與第一接墊39、第二接墊41或者第一接墊39和第二接墊41二者處於相同的高度水平的熱沉圖案。舉例而言，如至少在圖1中所示，第一熱沉圖案46可設置於與第一接墊39相同的水平高度處。第一熱沉圖案46可包含與第一接墊39相同的材料。舉例而言，第一熱沉圖案46及第一接墊39可至少部分地包含鋁或者可替代鋁的導電材料。第二熱沉圖案48可設置於與第二接墊41的至少一部分相同的水平高度處，第二熱沉圖案48可為包括第一熱沉圖案46及第二熱沉圖案48的單一熱沉圖案的至少一部分。第二熱沉圖案48可包含與第二接墊41相同的材料。在一些例示性實施例中，第一熱沉圖案46與第二熱沉圖案48可統稱為單一熱沉圖案。第二熱沉圖案48及第二接墊41可至少部分地包含與第一熱沉圖案46及第一接墊39的材料不同的材料。舉例而言，第二熱沉圖案48及第二接墊41可至少部分地包含銅或者可替代銅的導電材料。
熱沉結構44a可更包括位於第一熱沉圖案46及第二熱沉圖案48上的頂蓋圖案50。頂蓋圖案50可至少部分地包含與第一熱沉圖案46及第二熱沉圖案48的材料不同的材料。連接圖案140可至少部分地包含與頂蓋圖案50相同的材料。連接圖案140及頂蓋圖案50可包含與熱沉圖案（例如，第一熱沉圖案46及/或第二熱沉圖案48）及第二接墊41的材料不同的材料。頂蓋圖案50可具有向上凸起的形狀或修圓的頂表面，所述修圓的頂表面可至少部分地包括熱沉結構44a的頂表面44u。舉例而言，頂蓋圖案50可至少部分地包含焊接材料或者可替代焊接材料的熱沉材料。舉例而言，頂蓋圖案50可至少部分地包含錫-銀（SnAg）材料。熱沉結構44a可包括第一熱沉圖案46、第二熱沉圖案48及頂蓋圖案50。
在一些例示性實施例中，熱沉結構44a可設置於由接墊結構37環繞的虛設區域DR中。
第一下部晶片25可更包括基板28、位於基板28上的下部層31、位於下部層31上的上部層63及位於下部層31與上部層63之間的中間層56。如至少在圖1中所示，晶片接合接墊34、接墊結構37及熱沉結構44a可位於下部層31上。在一些例示性實施例中，第一下部晶片25可包括基板28、位於基板28上的晶片接合接墊34、接墊結構37及熱沉結構44a。
基板28可為半導體基板。舉例而言，基板28可為矽基板。下部層31可包含絕緣材料（例如氧化矽等）。中間層56可具有單層結構或多層式結構。舉例而言，中間層56可包括第一絕緣層58及位於第一絕緣層58上的第二絕緣層60。第一絕緣層58與第二絕緣層60可至少部分地包含彼此不同的材料。舉例而言，第一絕緣層58可包含氧化矽，且第二絕緣層60可包含氮化矽。上部層63可至少部分地包含絕緣材料。舉例而言，上部層63可至少部分地包含聚醯亞胺材料或者可替代聚醯亞胺材料的絕緣材料。
晶片接合接墊34、接墊結構37、重佈線53及熱沉結構44a可設置於下部層31上。
如至少在圖4A至圖4B中所示，上部層63及中間層56可具有第一開口65a及第二開口65b，第一開口65a延伸穿過上部層63與中間層56二者，以自上部層63及中間層56暴露出晶片接合接墊34的至少一部分，第二開口65b延伸穿過上部層63與中間層56二者，以自上部層63及中間層56暴露出接墊結構37的至少一部分，例如暴露出第一接墊39。上部層63及中間層56可進一步具有第三開口65c，第三開口65c延伸穿過上部層63與中間層56二者，以自上部層63及中間層56暴露出第一熱沉圖案46的至少一部分。
在一些例示性實施例中，晶片接合接墊34、重佈線53及第一接墊39可形成為單一本體。晶片接合接墊34、重佈線53及第一接墊39可無邊界地連續連接。晶片接合接墊34、重佈線53及第一接墊39可一體地且連續地形成。再次重申，晶片接合接墊34、重佈線53及第一接墊39可包括於單一連續的材料實例（「組件」、「部件」等）中。
下部基底15可為印刷電路板（printed circuit board，PCB）。如至少在圖1中所示，下部基底15可包括設置於下部基底15的頂表面上的第一基底接墊15p1、第二基底接墊15p2以及設置於下部基底15的底表面上的第三基底接墊15p3。下部基底15可包括設置於下部基底15中的內部配線15i。
如至少在圖1中所示，下部結構10a可更包括導線68，導線68被配置成將第一下部晶片25的晶片接合接墊34與下部基底15的第一基底接墊15p1電性連接至彼此。
下部結構10a可更包括位於第一下部晶片25與下部基底15之間的第二下部晶片80。如圖1中所示，第二下部晶片80可位於下部基底15上。如圖1中所示，第二下部晶片80可安裝於下部基底15上。第二下部晶片80可包括設置於被設置成與下部基底15相對的表面上的接墊82。
儘管可能使用例如「第一（first）」及「第二（second）」等用語來闡述各種組件，然而此種組件不應被理解為受限於以上用語。以上用語僅用於區分一個組件與另一組件。舉例而言，在不背離本發明概念的權利範圍的條件下，第一組件可被稱為第二組件，且同樣，第二組件可被稱為第一組件。在一些例示性實施例中，用語「第一」及「第二」等可以「下部」及「上部」等來替代。因此，用語「第一下部晶片」及「第二下部晶片」可分別以「第二下部晶片」及「第一下部晶片」來替代。
下部結構10a可更包括導電凸塊85，導電凸塊85將第二下部晶片80的接墊82與下部基底15的第二基底接墊15p2連接至彼此。因此，第二下部晶片80可以倒裝晶片方式安裝於下部基底15上。下部結構10a可更包含填充第二下部晶片80與下部基底15之間的間隙的底部填充材料88。
下部結構10a可更包括黏合層91，黏合層91設置於第一下部晶片25的面對下部基底15的表面上。黏合層91可設置於第一下部晶片25與第二下部晶片80之間，以將第一下部晶片25與第二下部晶片80接合至彼此。
下部結構10a可更包括下部模具層71。下部模具層71可位於下部基底15上，使得下部模具層71至少覆蓋第一下部晶片25。下部模具層71可包含例如環氧模製化合物（epoxy molding compound）等聚合物樹脂。下部模具層71可覆蓋安裝於下部基底15上的第一下部晶片25及第二下部晶片80。下部模具層71可覆蓋第一下部晶片25的上部部分，且可覆蓋導線68。下部模具層71可具有第一開口73a，第一開口73a延伸穿過下部模具層71的至少一部分，以自下部模具層71暴露出接墊結構37的頂表面37u的至少一部分，且因此自下部模具層71暴露出接墊結構37的至少一部分。如至少在圖1及圖4A中所示，連接圖案140可遠離上部結構110a延伸（例如，向下），以直接物理連接至接墊結構37的包括接墊結構37的頂表面37u的藉由第一開口73a暴露出的部分在內的部分。連接圖案140可被配置成將接墊結構37的頂表面37u的藉由第一開口73a暴露出的部分連接至上部結構110a。
在一些例示性實施例中，下部模具層71可覆蓋熱沉結構44a的頂表面44u。如至少在圖1及圖4A中所示，下部模具層71的頂表面71u的高度水平可高於接墊結構37的頂表面37u及熱沉結構44a的頂表面44u二者（例如，可相對於接墊結構37的頂表面37u及熱沉結構44a的頂表面44u二者遠離下部基底15）。
焊球94可設置於下部基底15上（例如，下方），以電性連接至下部基底15的第三基底接墊15p3。
上部結構110a可包括上部基底115及位於上部基底115上（例如，上方）的上部晶片120。上部基底115包括設置於被設置成與下部結構10a相對的表面上的第一上部接墊115p1、設置於被設置成與上部晶片120相對的表面上的第二上部接墊115p2以及位於上部基底115中的內部配線115i。
上部結構110a可更包括位於上部晶片120與上部基底115之間的黏合層126。上部結構110a可更包括覆蓋位於上部基底115上的上部晶片120的上部模具層132。
上部晶片120可包括設置於上部晶片120的頂表面上的上部接合接墊123。上部結構110a更包括上部導線129，上部導線129被配置成將上部晶片120的上部接合接墊123與上部基底115的第二上部接墊115p2電性連接至彼此。因此，上部晶片120可藉由打線接合（wire bonding）安裝於上部基底115上。本發明概念的例示性實施例不限於藉由打線接合將上部晶片120安裝於上部基底115上的情形。舉例而言，上部晶片120可以倒裝晶片方式安裝於上部基底115上。
連接圖案140可被配置成將下部結構10a與上部結構110a電性連接至彼此。連接圖案140可被配置成將下部結構10a與上部結構110a物理連接至彼此。連接圖案140可設置於下部結構10a與上部結構110a之間。連接圖案140可與下部結構10a的接墊結構37及上部結構110a的第一上部接墊115p1接觸（例如，可直接位於下部結構10a的接墊結構37及上部結構110a的第一上部接墊115p1上、可直接物理連接至下部結構10a的接墊結構37及上部結構110a的第一上部接墊115p1等）。連接圖案140可向上延伸（例如，遠離下部基底15），同時與接墊結構37接觸，以與上部結構110a的第一上部接墊115p1接觸。連接圖案140可至少部分地包括焊接材料。連接圖案140可被稱為「焊料凸塊」。
在一些例示性實施例中，下部結構10a與上部結構110a可彼此間隔開（例如，可被隔離而免於彼此直接接觸），且可藉由連接圖案140連接至彼此。如至少在圖1中所示，連接圖案140可連接至上部結構110a，且可遠離上部結構110a延伸（例如，向下），以直接物理連接至接墊結構37。如至少在圖1及圖4A中所示，可在下部結構10a與上部結構110a之間形成空白空間143，以暴露出連接圖案140的側表面140s的至少一部分。
在一些例示性實施例中，連接圖案140可與接墊結構37的頂表面接觸，同時填充下部模具層71的第一開口73a，第一開口73a暴露出接墊結構37的頂表面的至少一部分。下部模具層71的第一開口73a的至少一部分的寬度可小於接墊結構37的第二接墊41的寬度。
如至少在圖4A中所示，下部模具層71的第一開口73a可包括在自下部模具層71的頂表面指向接墊結構37的方向上變窄且接著變寬的部分。因此，在下部模具層71的第一開口73a中，連接圖案140可包括曲折部分140p，曲折部分140p在自與接墊結構37的第二接墊41的頂表面接觸的部分指向上部結構110a的方向上變窄且接著變寬。再次重申，且如至少在圖4A中所示，連接圖案140的位於第一開口73a中的一部分可包括曲折部分140p，曲折部分140p與距接墊結構37的頂表面37u的距離成比例地變窄且接著變寬。
接下來，將參照圖5至圖25各別地或以組合形式闡述根據本發明概念一些例示性實施例的半導體封裝1的各種經修改例子。
在圖5至圖25中，圖5、圖6、圖7、圖8、圖10、圖11、圖12、圖13、圖14、圖16、圖18、圖19及圖20中的每一者是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖，且圖24及圖25中的每一者是示出根據本發明概念一些例示性實施例的半導體封裝的上部結構的經修改例子的剖視圖。在圖5至圖25中，圖9及圖21中的每一者是沿圖3中的線I-I'、II-II'及III-III'截取的區域的局部放大剖視圖，其示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子，圖15、圖17A、圖17B及圖17C中的每一者是示出根據本發明概念一些例示性實施例的半導體封裝的一些組件的經修改例子的平面圖，圖22是沿圖3中的線IV-IV'截取的區域的局部放大剖視圖，且圖23是示出根據本發明概念一些例示性實施例的半導體封裝的下部結構的經修改例子的局部放大剖視圖。
在經修改例子中，參照圖5，半導體封裝1的下部結構10b可包括熱沉結構44a，其中頂蓋圖案50的頂表面被暴露出。舉例而言，下部模具層71可進一步具有第二開口73b，第二開口73b暴露出熱沉結構44a的頂蓋圖案50的頂表面的至少一部分，且因此暴露出熱沉結構44a的至少一部分。因此，由於熱沉結構44a的頂蓋圖案50可藉由下部模具層71的第二開口73b暴露出，因此可改進下部結構10b的熱沉特性。
在經修改例子中，參照圖6，半導體封裝1的下部結構10c可包括熱沉結構44b，熱沉結構44b包括與接墊結構37的第一接墊39對應的第一熱沉圖案46及與接墊結構37的第二接墊41對應的第二熱沉圖案48。熱沉結構44b的第二熱沉圖案48的頂表面可與下部模具層71直接接觸。
在經修改例子中，參照圖7，半導體封裝1的下部結構10d可包括熱沉結構44b，其中第二熱沉圖案48的頂表面被暴露出。舉例而言，下部模具層71可包括第二開口73b，第二開口73b暴露出熱沉結構44b的第二熱沉圖案48的頂表面的至少一部分。因此，由於熱沉結構44a的第二熱沉圖案48可藉由下部模具層71的第二開口73b暴露出，因此可改進下部結構10d的熱沉特性。
在經修改例子中，參照圖8及圖9，半導體封裝1的下部結構10e可包括接墊結構37，接墊結構37具有至少一部分被暴露出的側表面37s。舉例而言，下部模具層71可具有第一開口73a'，第一開口73a'的寬度大於接墊結構37的第二接墊41的寬度，使得第一開口73a'自下部模具層71暴露出接墊結構37的頂表面37u，且進一步自下部模具層71暴露出接墊結構37的側表面37s的至少一部分。接墊結構37的第二接墊41的側表面可藉由下部模具層71的第一開口73a'暴露出。下部模具層71的第一開口73a'可暴露至位於下部結構10a與上部結構110a之間的空白空間143。
連接圖案140'可與上部結構110a的第一上部接墊115p1接觸，同時與接墊結構37的第二接墊41的側表面的一部分及第二接墊41的頂表面接觸。
接墊結構37的第二接墊41的側表面及連接圖案140'的側表面可藉由下部模具層71的第一開口73a'及空白空間143暴露出。因此，包括下部結構10e及連接圖案140'的半導體封裝1的熱沉特性可與熱沉結構44a一起改進。
在經修改例子中，參照圖10，半導體封裝1的下部結構10f包括接墊結構37及熱沉結構44a，接墊結構37具有至少一部分被暴露出的側表面，熱沉結構44a具有至少一部分被暴露出的頂表面。舉例而言，下部模具層71可包括第一開口73a'及第二開口73b'，第一開口73a'的寬度大於接墊結構37的第二接墊41的寬度，第二開口73b'的寬度大於熱沉結構44a的第二熱沉圖案48的寬度。因此，接墊結構37的第二接墊41的側表面以及第二熱沉圖案48的側表面及頂蓋圖案50的頂表面可藉由下部模具層71的第一開口73a'暴露出。
下部模具層71的第一開口73a'及第二開口73b'暴露至位於下部結構10a與上部結構110a之間的空白空間143。因此，熱沉結構44a及接墊結構37可藉由下部模具層71的第一開口73a'及第二開口73b'暴露出，以改進熱沉特性。
在經修改例子中，參照圖11，半導體封裝1的下部結構10g包括接墊結構37及熱沉結構44b，接墊結構37具有至少一部分被暴露出的側表面，熱沉結構44b具有第二熱沉圖案48，第二熱沉圖案48具有被下部模具層71覆蓋的頂表面。下部模具層71可具有第一開口73a'，第一開口73a'的寬度大於接墊結構37的第二接墊41的寬度，且暴露出第二接墊41的側表面，且可直接覆蓋熱沉結構44b的第二熱沉圖案48的頂表面及側表面。
在經修改例子中，參照圖12，半導體封裝1的下部結構10h包括接墊結構37及熱沉結構44b，接墊結構37具有至少一部分被暴露出的側表面，熱沉結構44b具有第二熱沉圖案48，第二熱沉圖案48具有被暴露出的側表面及被暴露出的頂表面。舉例而言，下部模具層71具有第一開口73a'及第二開口73b'，第一開口73a'的寬度大於接墊結構37的第二接墊41的寬度且暴露出第二接墊41的側表面，第二開口73b'的寬度大於熱沉結構44b的第二熱沉圖案48的寬度且暴露出第二熱沉圖案48的側表面及頂表面。接墊結構37的第二接墊41的側表面及第二熱沉圖案48的側表面及頂表面可藉由下部模具層71的第一開口73a'暴露出。
在經修改例子中，參照圖13，半導體封裝1可更包括位於下部結構10i與上部結構110a之間的虛設圖案140d。虛設圖案140d可與下部結構10i的熱沉結構44b接觸並連接（例如，直接物理連接），以釋放下部結構10i的熱量。上部結構110a的上部基底115可更包括虛設接墊115p3。虛設接墊115p3可與虛設圖案140d接觸。虛設圖案140d可具有與連接圖案140相同的結構。虛設圖案140d可包含與連接圖案140相同的材料。虛設圖案140d可至少部分地包含與連接圖案140相同的材料。熱沉結構44b可包括第一熱沉圖案46及第二熱沉圖案48。第二熱沉圖案48可與虛設圖案140d接觸。
當一元件在本文中被闡述為包含與另一元件「相同」的材料時，或者當一元件在本文中被闡述為至少部分地包含與另一元件「相同」的材料時，將理解，所述元件的總材料組成可與另一元件的總材料組成相同。相似地，當一元件在本文中被闡述為包含與另一元件「不同」的材料，或者至少部分地包含與另一元件「不同」的材料，將理解，所述元件的總材料組成可與另一元件的總材料組成不同。
在經修改例子中，參照圖14，半導體封裝1可包括圖13中闡述的熱沉結構44b及虛設圖案140d。半導體封裝1的下部結構10j包括接墊結構37及熱沉結構44b，接墊結構37具有至少一部分被暴露出的側表面，熱沉結構44b包括具有被暴露出的側表面的第二熱沉圖案48。舉例而言，下部模具層71具有第一開口73a'及第二開口73b'，第一開口73a'的寬度大於接墊結構37的第二接墊41的寬度且暴露出第二接墊41的側表面，第二開口73b'的寬度大於熱沉結構44b的第二熱沉圖案48的寬度且暴露出第二熱沉圖案48的側表面。由於下部模具層71的第一開口73a'及第二開口73b'可暴露至位於下部結構10j與上部結構110a之間的空白空間143，因此連接圖案140的側表面及虛設圖案140d的側表面可被暴露出。因此，可改進半導體封裝1的熱沉特性。
返回至圖2，多個接墊結構37可被設置成環繞虛設區域DR。在下文中，將參照圖15闡述接墊結構37及虛設區域DR的平面設置的經修改例子。
在經修改例子中，參照圖15，多個接墊結構37可設置於虛設區域DR'的兩側上。虛設結構44可設置於虛設區域DR'中。虛設結構44可為包括上述第一熱沉圖案46、第二熱沉圖案48及頂蓋圖案50的熱沉結構44a或者包括第一熱沉圖案46及第二熱沉圖案48的熱沉結構44a。虛設區域DR'不限於以上例子。
在第一下部晶片25中，晶片接合接墊34及接墊結構37可根據半導體封裝1的類型或用途進行各種修改及設置，且熱沉結構44a可以各種形式設置於未設置晶片接合接墊34及接墊結構37的虛設區域DR'中。
在經修改例子中，參照圖16，半導體封裝1的下部結構10k包括具有第一熱沉圖案46'及第二熱沉圖案48'的熱沉結構44c。第一熱沉圖案46'可形成於與接墊結構37的第一接墊39相同的水平高度上。第一熱沉圖案46'可包含與第一接墊39相同的材料。第一熱沉圖案46'可至少部分地包含與第一接墊39相同的材料。第二熱沉圖案48'可設置於與接墊結構37的第二接墊41相同的水平高度上。第二熱沉圖案48'可包含與第二接墊41相同的材料。第二熱沉圖案48'可至少部分地包含與第二接墊41相同的材料。熱沉結構44c中任一者的大小可大於接墊結構37中任一者的大小。將參照圖17A至圖17C闡述熱沉結構44c的例子。
在經修改例子中，參照圖17A，熱沉結構44c_1可具有板形狀。熱沉結構44c_1可具有較接墊結構37中的任一者大的平面面積。熱沉結構44c可具有較接墊結構37中的任一者大的寬度。
在經修改例子中，參照圖17B，在平面中，熱沉結構44c_2可呈彼此間隔開的線的形式。熱沉結構44c_2中的任一者可呈長度大於接墊結構37中任一者的長度的線的形式。
在經修改例子中，參照圖17C，在平面中，熱沉結構44c_3可具有網格形狀。
在經修改例子中，參照圖18，半導體封裝1的下部結構10l可設置於與接墊結構37的第一接墊39相同的水平高度上，且可包括由與第一接墊39相同的材料形成的熱沉結構44d。熱沉結構44d的頂表面可被中間層56及上部層63覆蓋。
在經修改例子中，參照圖19，半導體封裝1的下部結構10m可包括設置於上部層63上的熱沉結構44e。熱沉結構44e的底表面可與上部層63接觸。熱沉結構44e包括熱沉圖案48e及位於熱沉圖案48e上的頂蓋圖案50，熱沉圖案48e設置於與接墊結構37的第二接墊41相同的水平高度上，且由與第二接墊41相同的材料形成。
在經修改例子中，參照圖20、圖21及圖22，半導體封裝1的下部結構10n包括晶片接合接墊34'，晶片接合接墊34'包括第一接合接墊34_1及位於第一接合接墊34_1上的第二接合接墊34_2。上述導線68可接合至晶片接合接墊34'的第二接合接墊34_2。
第二接合接墊34_2的厚度可小於接墊結構37的第二接墊41的厚度。
上述重佈線53可與第一接合接墊34_1及第一接墊39一體形成。因此，重佈線53、第一接合接墊34_1及第一接墊39可設置於相同的水平高度上，且可至少部分地包含相同的材料。
在參照圖1至圖22闡述的例示性實施例中，第一下部晶片25可設置於基板28上，且可包括晶片接合接墊34、接墊結構37及設置於重佈線53及熱沉結構44a上（例如，下方）的下部層31。將參照圖23闡述第一下部晶片25的例子。
參照圖23，在一例子中，第一下部晶片25的下部層31可包含絕緣材料。下部層31可至少部分地包含絕緣材料（例如氧化矽等），以將晶片接合接墊34、接墊結構37及熱沉結構44a與基板28絕緣。第一下部晶片25可為中介晶片。
在另一例子中，第一下部晶片25可更包括設置於下部層31中的下部晶片圖案32。下部晶片圖案32中的一些下部晶片圖案32可電性連接至接墊結構37。下部晶片圖案32可構成積體電路或電路配線。因此，第一下部晶片25可為半導體晶片。
在另一例子中，下部晶片圖案32可構成例如電容器、電阻器、電感器等被動元件。因此，第一下部晶片25可為包括被動元件的中介晶片。
在參照圖1至圖22闡述的實施例中，上部結構110a可包括藉由打線接合安裝於上部基底115上的上部晶片120。將參照圖24闡述上部結構110a的經修改例子。
在經修改例子中，參照圖24，上部結構110b可包括上部基底115'及以倒裝晶片方式安裝於上部基底115'上的上部晶片120a、120b、120c及120d。
在一例子中，可堆疊多個上部晶片120a、120b、120c及120d。舉例而言，上部晶片120a、120b、120c及120d可包括依序堆疊的第一上部晶片120a、第二上部晶片120b、第三上部晶片120c及第四上部晶片120d。上部結構110b可包括第一凸塊124a及第二凸塊124b，第一凸塊124a設置於第一上部晶片120a與上部基底115'之間以將第一上部晶片120a的接墊121a與上部基底115'的接墊115p2'連接至彼此，第二凸塊124b設置於第一上部晶片至第四上部晶片120a、120b、120c及120d之間以將相鄰的上部晶片連接至彼此。第二凸塊124b可與彼此相鄰的上部晶片的接墊121b接觸。第一上部晶片至第四上部晶片120a、120b、120c及120d可藉由第一上部晶片至第三上部晶片120a、120b及120c中的貫通電極（through-electrode）125電性連接。
上部結構110b可更包括黏合層127，黏合層127設置於第一上部晶片120a與上部基底115'之間，且設置於第一上部晶片至第四上部晶片120a、120b、120c及120d之間。上部結構110b可更包括覆蓋位於上部基底115'上的上部晶片120a、120b、120c及120d的上部模具層132'。
在經修改例子中，參照圖25，上部結構110c可為半導體晶片。舉例而言，上部結構110c可包括半導體基板112及前部結構113。前部結構113可包括半導體積體電路。前部結構113可包括與上述連接圖案140接觸的上部接墊115p'。
圖26A至圖26C、圖27A及圖27B是示出根據本發明概念一些例示性實施例的製作半導體封裝的方法的例子的剖視圖。
首先，將參照圖26A至圖26C闡述形成第一下部晶片25的方法的例子。
參照圖26A，可在基板28上形成下部層31。基板28可為具有多個晶片區域CA的半導體晶圓。舉例而言，基板28可為矽基板。可在下部層31上形成晶片接合接墊34、第一接墊39及第一熱沉圖案46。晶片接合接墊34、第一接墊39及第一熱沉圖案46可同時形成，且可至少部分地包含相同的材料（例如鋁）。
可在下部層31上依序形成中間層56及上部層63，以覆蓋晶片接合接墊34，在下部層31上依序形成第一接墊39及第一熱沉圖案46。中間層56可至少部分地包含例如氧化矽及氮化矽等絕緣材料。上部層63可至少部分地包含例如聚醯亞胺等材料。
參照圖26B，將上部層63及中間層56圖案化，以形成暴露出晶片接合接墊34的頂表面的第一開口65a、暴露出第一接墊39的頂表面的第二開口65b及暴露出第一熱沉圖案46的第三開口65c。可在第一接墊39及第一熱沉圖案46上分別形成第二接墊41及第二熱沉圖案48。第二接墊41與第二熱沉圖案48可至少部分地包含相同的材料（例如，銅等）。
參照圖26C，可在第二接墊41的頂表面及第二熱沉圖案48的頂表面上形成頂蓋圖案50。頂蓋圖案50可至少部分地包含焊料材料。因此，可形成包括第一熱沉圖案46、第二熱沉圖案48及頂蓋圖案50的熱沉結構44a。可在基板28上形成包括第一接墊39及第二接墊41的接墊結構37。可使用位於接墊結構37上的頂蓋圖案50將接墊結構37連接至另一結構。
可藉由實行切割基板28的切割製程來分離所述多個晶片區域（圖26A及圖26B中的CA）。因此，可形成分離的第一下部晶片25。因此，可製備出第一下部晶片25。
參照圖27A，可在上面形成有焊球94的下部基底15上安裝第二下部晶片80。第二下部晶片80可以倒裝晶片方式安裝於下部基底15上。
可將第一下部晶片25接合至第二下部晶片80上。舉例而言，可將黏合層91黏合至第一下部晶片25的底表面及第二下部晶片80的頂表面。在一例子中，可在圖26C中闡述的分離所述多個晶片區域（圖26A及圖26B所示CA）的切割製程之前在基板28的底表面上形成黏合層91。
可以如下方式實行打線接合製程：形成導線68，以將第一下部晶片25的晶片接合接墊34與下部基底15的第一基底接墊15p1連接至彼此。
參照圖27B，可在下部基底15上形成下部模具層71，以覆蓋第一下部晶片25的上部部分、第一下部晶片25的側表面及第二下部晶片80的側表面以及導線68。因此，可在下部基底15上形成延伸至下部模具層71的下部結構10a。
返回至圖1，可以如下方式將下部模具層71圖案化：形成第一開口73a，以暴露出位於接墊結構37上的頂蓋圖案（圖27B中的50）。可製備出與圖1中闡述的相同的上部結構110a。上部結構110a可為半導體封裝或半導體晶片。
在上部結構110a的下部部分上形成焊球之後，可將位於上部結構110a的下部部分上的焊球與接墊結構37的藉由下部模具層71的第一開口73a暴露出的頂蓋圖案（圖27B中的50）連接至彼此。舉例而言，可藉由焊料迴流製程（solder reflow process）將位於上部結構110a的下部部分上的焊球及接墊結構37的藉由下部模具層71的第一開口73a暴露出的頂蓋圖案（圖27B中的50）形成為連接圖案140。因此，可形成包括藉由連接圖案140連接至彼此的下部結構10a與上部結構110a的半導體封裝1。
在一些例示性實施例中，如上所述，上述半導體封裝1可包括熱沉結構44a、44b、44c、44d及44e。熱沉結構44a至44e可將在下部結構10a至10n中產生的熱量釋放至下部結構10a至10n的外部。舉例而言，熱沉結構44a至44e可用於高效地將第一下部晶片25中的熱量釋放至位於下部結構10a與上部結構110a至110c之間的空白空間143。
位於下部結構10a至10n中的第二下部晶片80可被第一下部晶片25、下部基底15及下部模具層71環繞。在第二下部晶片80中產生的此種熱量可藉由熱沉結構44a至44e更有效地釋放。因此，在一些例示性實施例中，熱沉結構44a至44e可更有效地將在半導體封裝1中的下部結構10a中產生的熱量釋放至外部。因此，可防止或顯著減少由在半導體封裝1中產生的熱量引起的半導體封裝1的效能劣化。
在本發明概念的一些例示性實施例中，在包括下部結構及上部結構的半導體封裝中，可在下部結構中包括熱沉結構，以高效地釋放在下部結構中產生的熱量。可使用熱沉結構釋放下部結構中的熱量，以防止或顯著減少半導體封裝的效能劣化。
儘管以上已示出並闡述一些例示性實施例，然而對於熟習此項技術者而言將顯而易見，在不背離如由隨附申請專利範圍所界定的本發明概念的範圍的條件下，可進行修改及變化。
1：半導體封裝 10a、10b、10c、10d、10e、10f、10g、10h、10i、10j、10k、10l、10m、10n:下部結構 15:下部基底 15i、115i:內部配線 15p1:第一基底接墊 15p2:第二基底接墊 15p3:第三基底接墊 15u、28u、37u、44u、71u:頂表面 25:第一下部晶片 28:基板 31:下部層 32:下部晶片圖案 34、34':晶片接合接墊 34_1:第一接合接墊 34_2:第二接合接墊 34T、37T:厚度 37:接墊結構 37s、140s:側表面 39:第一接墊 41:第二接墊 44:虛設結構 44a、44b、44c、44c_1、44c_2、44c_3、44d、44e:熱沉結構 46、46':第一熱沉圖案 48、48':第二熱沉圖案 50:頂蓋圖案 53:重佈線 56:中間層 58:第一絕緣層 60:第二絕緣層 63:上部層 65a、73a、73a':第一開口 65b、73b、73b':第二開口 65c:第三開口 68:導線 71:下部模具層 80:第二下部晶片 82:接墊 85:導電凸塊 88:底部填充材料 91:黏合層 94:焊球 110a、110b、110c:上部結構 112:半導體基板 113:前部結構 115、115':上部基底 115p':上部接墊 115p1:第一上部接墊 115p2:第二上部接墊 115p2'、121a、121b:接墊 115p3:虛設接墊 120:上部晶片 120a:上部晶片/第一上部晶片 120b:上部晶片/第二上部晶片 120c:上部晶片/第三上部晶片 120d:上部晶片/第四上部晶片 123:上部接合接墊 124a:第一凸塊 124b:第二凸塊 125:貫通電極 126、127:黏合層 129:上部導線 132、132':上部模具層 140、140':連接圖案 140d:虛設圖案 140p:曲折部分 143:空白空間 A:部分 CA:晶片區域 DR、DR':虛設區域 I-I'、II-II'、III-III'、IV-IV':線
結合附圖閱讀以下詳細說明，將更清楚地理解本揭露的以上及其他態樣、特徵及優點，在附圖中： 圖1是示出根據本發明概念一些例示性實施例的半導體封裝的例子的剖視圖。 圖2是示出根據本發明概念一些例示性實施例的半導體封裝的一些組件的例子的平面圖。 圖3是示出設置於圖2中部分「A」的放大區域中的一些組件的例子的放大圖。 圖4A是沿圖3中的線I-I'、II-II'及III-III'截取的區域的局部放大剖視圖。 圖4B是沿圖3中的線IV-IV'截取的區域的局部放大剖視圖。 圖5是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖6是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖7是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖8是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖9是沿圖3中的線I-I'、II-II'及III-III'截取的區域的局部放大剖視圖，其示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子。 圖10是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖11是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖12是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖13是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖14是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖15是示出根據本發明概念一些例示性實施例的半導體封裝的一些組件的經修改例子的平面圖。 圖16是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖17A是示出根據本發明概念一些例示性實施例的半導體封裝的一些組件的經修改例子的平面圖。 圖17B是示出根據本發明概念一些例示性實施例的半導體封裝的一些組件的經修改例子的平面圖。 圖17C是示出根據本發明概念一些例示性實施例的半導體封裝的一些組件的經修改例子的平面圖。 圖18是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖19是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖20是示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子的剖視圖。 圖21是沿圖3中的線I-I'、II-II'及III-III'截取的區域的局部放大剖視圖，其示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子。 圖22是沿圖3中的線IV-IV'截取的區域的局部放大剖視圖，其示出根據本發明概念一些例示性實施例的半導體封裝的經修改例子。 圖23是示出根據本發明概念一些例示性實施例的半導體封裝的下部結構的經修改例子的部分放大剖視圖。 圖24是示出根據本發明概念一些例示性實施例的半導體封裝的上部結構的經修改例子的部分放大剖視圖。 圖25是示出根據本發明概念一些例示性實施例的半導體封裝的上部結構的經修改例子的部分放大剖視圖。 圖26A、圖26B、圖26C、圖27A及圖27B是示出根據本發明概念一些例示性實施例的製作半導體封裝的方法的例子的剖視圖。
1:半導體封裝
10a:下部結構
15:下部基底
15i、115i:內部配線
15p1:第一基底接墊
15p2:第二基底接墊
15p3:第三基底接墊
15u、28u:頂表面
25:第一下部晶片
28:基板
31:下部層
34:晶片接合接墊
37:接墊結構
39:第一接墊
41:第二接墊
44a:熱沉結構
46:第一熱沉圖案
48:第二熱沉圖案
50:頂蓋圖案
56:中間層
63:上部層
68:導線
71:下部模具層
73a:第一開口
80:第二下部晶片
82:接墊
85:導電凸塊
88:底部填充材料
91:黏合層
94:焊球
110a:上部結構
115:上部基底
115p1:第一上部接墊
115p2:第二上部接墊
120:上部晶片
123:上部接合接墊
126:黏合層
129:上部導線
132:上部模具層
140:連接圖案
140s:側表面
143:空白空間

Claims (19)

  1. 一種半導體封裝，包括：下部結構，所述下部結構包括下部基底及在所述下部基底上的第一下部晶片，所述第一下部晶片包括晶片接合接墊、接墊結構及熱沉結構，所述接墊結構具有大於所述晶片接合接墊的厚度的厚度，所述熱沉結構的至少一部分與所述接墊結構的至少一部分在相同的高度水平處；上部結構，在所述下部結構上；以及連接圖案，在所述下部結構與所述上部結構之間，所述連接圖案被配置成將所述下部結構與所述上部結構電性連接至彼此，所述連接圖案連接至所述上部結構，所述連接圖案遠離所述上部結構延伸以連接至所述接墊結構，其中所述接墊結構包括第一接墊以及在所述第一接墊上的第二接墊，且所述晶片接合接墊設置於與所述第一接墊相同的高度水平上。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述熱沉結構包括第一熱沉圖案及在所述第一熱沉圖案上的第二熱沉圖案，所述第一熱沉圖案與所述第一接墊在相同的高度水平處，所述第一熱沉圖案包含與所述第一接墊相同的材料，所述第二熱沉圖案與所述第二接墊在相同的高度水平處，且 所述第二熱沉圖案包含與所述第二接墊相同的材料。
  3. 如申請專利範圍第1項所述的半導體封裝，更包括：重佈線，被配置成將所述晶片接合接墊與所述接墊結構電性連接至彼此。
  4. 如申請專利範圍第3項所述的半導體封裝，其中所述晶片接合接墊、所述重佈線及所述第一接墊被包括於單一連續的材料中，且所述熱沉結構設置於由所述接墊結構環繞的虛設區域中。
  5. 一種半導體封裝，包括：下部結構，所述下部結構包括下部基底及在所述下部基底上的第一下部晶片，所述第一下部晶片包括晶片接合接墊、接墊結構及熱沉結構，所述接墊結構具有大於所述晶片接合接墊的厚度的厚度，其中所述熱沉結構的至少一部分與所述接墊結構的至少一部分在相同的高度水平處；上部結構，在所述下部結構上；以及連接圖案，在所述下部結構與所述上部結構之間，所述連接圖案被配置成將所述下部結構與所述上部結構電性連接至彼此，所述連接圖案連接至所述上部結構，所述連接圖案遠離所述上部結構延伸以連接至所述接墊結構，其中所述第一下部晶片更包括重佈線，所述重佈線被配置成將所述晶片接合接墊與所述接墊結構電性連接至彼此，其中所述接墊結構包括第一接墊以及在所述第一接墊上的第 二接墊，且其中所述熱沉結構包括第一熱沉圖案及在所述第一熱沉圖案上的第二熱沉圖案，其中所述第一下部晶片更包括：矽基板；下部層，在所述矽基板上；上部層，在所述下部層上；以及中間層，在所述下部層與所述上部層之間，其中所述晶片接合接墊、所述接墊結構及所述熱沉結構在所述下部層上，其中所述上部層及所述中間層具有：第一開口，延伸穿過所述上部層與所述中間層二者，以暴露出所述晶片接合接墊的至少一部分；第二開口，延伸穿過所述上部層與所述中間層二者，以暴露出所述接墊結構的所述第一接墊；以及第三開口，延伸穿過所述上部層與所述中間層二者，以暴露出所述熱沉結構的所述第一熱沉圖案，其中所述第一熱沉圖案與所述第一接墊及所述重佈線在相同的高度水平處，其中所述第一熱沉圖案包含與所述第一接墊及所述重佈線相同的材料，其中所述第二熱沉圖案與所述第二接墊在相同的高度水 平處，其中所述第二熱沉圖案包含與所述第二接墊相同的材料，其中所述第二熱沉圖案的所述材料不同於所述第一熱沉圖案的所述材料，其中所述第二熱沉圖案及所述第二接墊的頂表面在高於所述上部層的頂表面的水平處，且其中所述第二熱沉圖案及所述第二接墊中的每一者具有大於所述第一熱沉圖案、所述第一接墊、所述晶片接合接墊及所述重佈線中的每一者的厚度的厚度。
  6. 如申請專利範圍第5項所述的半導體封裝，其中所述下部基底包括第一基底接墊，所述下部結構更包括被配置成將所述晶片接合接墊與所述第一基底接墊電性連接至彼此的導線，且所述下部結構更包括覆蓋所述第一下部晶片及所述導線的下部模具層，所述下部模具層具有第四開口，所述第四開口延伸穿過所述下部模具層以暴露出所述接墊結構的至少一部分，且所述下部模具層的頂表面在高於所述接墊結構及所述熱沉結構的頂表面的高度水平處。
  7. 如申請專利範圍第6項所述的半導體封裝，更包括：第二下部晶片，在所述第一下部晶片與所述下部基底之間；黏合層，在所述第一下部晶片與所述第二下部晶片之間； 導電凸塊，連接所述第二下部晶片的另一接墊和所述下部基底的第二基底接墊，其中所述黏合層接觸所述矽基板的底表面及所述第二下部晶片的頂表面。
  8. 如申請專利範圍第6項所述的半導體封裝，其中所述連接圖案遠離所述上部結構延伸，以連接至所述接墊結構的藉由所述下部模具層的所述第四開口暴露出的所述第二接墊的至少一部分。
  9. 一種半導體封裝，包括：下部結構，所述下部結構包括下部基底、在所述下部基底上的下部晶片及在所述下部基底上的下部模具層，使得所述下部模具層覆蓋所述下部晶片，所述下部晶片包括接墊結構及熱沉結構，所述熱沉結構的至少一部分與所述接墊結構的至少一部分在相同的高度水平處，所述下部模具層所具有的頂表面的高度水平高於所述接墊結構的頂表面及所述熱沉結構的頂表面二者，所述下部模具層具有第一開口，所述第一開口延伸穿過所述下部模具層的至少一部分以暴露出所述接墊結構的所述頂表面的至少一部分；上部結構，在所述下部結構上；以及連接圖案，在所述下部結構與所述上部結構之間，所述連接圖案被配置成將所述下部結構與所述上部結構電性連接至彼此，所述連接圖案連接至所述上部結構，所述連接圖案遠離所述上部 結構延伸，以連接至藉由所述第一開口所暴露出的所述接墊結構的所述頂表面的所述部分，其中所述接墊結構包括第一接墊以及在所述第一接墊上的第二接墊。
  10. 如申請專利範圍第9項所述的半導體封裝，其中所述熱沉結構包括熱沉圖案，所述熱沉圖案與所述第一接墊、所述第二接墊或者所述第一接墊與所述第二接墊二者在相同的高度水平處。
  11. 如申請專利範圍第10項所述的半導體封裝，其中所述熱沉結構包括在所述熱沉圖案上的頂蓋圖案，所述熱沉圖案的至少一部分與所述第二接墊的至少一部分在相同的高度水平處，所述熱沉圖案包括與所述第二接墊相同的材料，所述連接圖案包括與所述頂蓋圖案相同的材料，且所述連接圖案及所述頂蓋圖案包含與所述熱沉圖案及所述第二接墊的材料不同的材料。
  12. 如申請專利範圍第9項所述的半導體封裝，其中設置於所述第一開口中的所述連接圖案的至少一部分包括曲折部分，所述曲折部分與距所述接墊結構的所述頂表面的距離成比例地變窄且接著變寬。
  13. 如申請專利範圍第9項所述的半導體封裝，其中所述第一開口進一步暴露出所述接墊結構的側表面的至少一部分。
  14. 如申請專利範圍第9項所述的半導體封裝，其中所述下部模具層覆蓋所述熱沉結構的整個頂表面。
  15. 如申請專利範圍第9項所述的半導體封裝，其中所述下部模具層進一步具有第二開口，所述第二開口暴露出所述熱沉結構的至少部分。
  16. 如申請專利範圍第9項所述的半導體封裝，更包括：虛設圖案，在所述下部結構與所述上部結構之間，其中所述虛設圖案連接至所述上部結構的虛設接墊與所述下部結構的所述熱沉結構二者，其中所述虛設圖案包含與所述連接圖案相同的材料。
  17. 一種半導體封裝，包括：下部結構，所述下部結構包括下部基底、在所述下部基底上的第一下部晶片、在所述第一下部晶片與所述下部基底之間的第二下部晶片以及覆蓋所述第一下部晶片的下部模具層，所述第一下部晶片包括基板、在所述基板上的晶片接合接墊、接墊結構及熱沉結構，所述熱沉結構的至少一部分與所述接墊結構的至少一部分在相同的高度水平處，所述下部模具層所具有的頂表面在高於所述接墊結構的頂表面及所述熱沉結構的頂表面二者的高度水平處，所述下部模具層具有第一開口，所述第一開口延伸穿過所述下部模具層的至少一部分以暴露出所述接墊結構的所述頂表面的至少一部分；上部結構，在所述下部結構上，所述上部結構被隔離而免於 與所述下部結構直接接觸；以及連接圖案，在所述下部結構與所述上部結構之間，所述連接圖案被配置成將所述下部結構與所述上部結構電性連接至彼此，所述連接圖案被配置成將所述接墊結構的所述頂表面的所述部分與所述上部結構連接至彼此，其中所述接墊結構包括第一接墊以及在所述第一接墊上的第二接墊。
  18. 如申請專利範圍第17項所述的半導體封裝，更包括：空白空間，在所述下部結構與所述上部結構之間，且其中所述空白空間暴露出所述連接圖案的側表面的至少一部分。
  19. 如申請專利範圍第17項所述的半導體封裝，其中所述第一下部晶片更包括在所述基板上的重佈線，所述重佈線被配置成將所述晶片接合接墊與所述接墊結構電性連接至彼此，所述下部結構更包括導線，所述導線被配置成將所述第一下部晶片的所述晶片接合接墊與所述下部基底的基底接墊電性連接，所述熱沉結構包括熱沉圖案及在所述熱沉圖案上的頂蓋圖案，所述重佈線被配置成將所述第一接墊與所述晶片接合接墊電性連接至彼此， 所述熱沉圖案包含與所述第二接墊相同的材料，且所述連接圖案包含與所述頂蓋圖案相同的材料。
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