TWI831138B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
- Publication number
- TWI831138B TWI831138B TW111107025A TW111107025A TWI831138B TW I831138 B TWI831138 B TW I831138B TW 111107025 A TW111107025 A TW 111107025A TW 111107025 A TW111107025 A TW 111107025A TW I831138 B TWI831138 B TW I831138B
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- Taiwan
- Prior art keywords
- semiconductor device
- wafer
- sealing
- sealing portion
- terminals
- Prior art date
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Classifications
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
根據實施方式,提供一種具有支持體、複數個第1晶片、第1密封部、第2晶片、複數個第1端子及第2端子之半導體裝置。複數個第1晶片積層於支持體上。第1密封部將複數個第1晶片密封。第1密封部於與支持體為相反側之表面具有凹部。凹部包含與複數個第1晶片分離之底面。第2晶片配置於凹部。複數個第1端子對應於複數個第1晶片。複數個第1端子各自從第1晶片之與支持體為相反側之面沿著積層方向延伸並貫通第1密封部。第2端子配置於第2晶片之與支持體為相反側之面。
Description
本實施方式係關於一種半導體裝置。
半導體裝置中,有時會將複數個晶片積層,使端子從各晶片沿著積層方向延伸而構成。半導體裝置中,期望除了複數個晶片以外,還能適當地配置其他晶片。
一實施方式提供一種能夠適當地配置複數個第1晶片及第2晶片之半導體裝置。
實施方式之半導體裝置提供一種具有支持體、複數個第1晶片、第1密封部、第2晶片、複數個第1端子及第2端子之半導體裝置。複數個第1晶片積層於支持體上。第1密封部將複數個第1晶片密封。第1密封部於與支持體為相反側之表面具有凹部。凹部包含與複數個第1晶片分離之底面。第2晶片配置於凹部中。複數個第1端子對應於複數個第1晶片。複數個第1端子各自從第1晶片之與支持體為相反側之面沿著積層方向延伸並貫通第1密封部。第2端子配置於第2晶片之與支持體為相反側之面。
根據上述構成,可提供一種能夠適當地配置複數個第1晶片及第2晶
片之半導體裝置。
1:半導體裝置
2:支持體
2a:面
3a:正面
3-1~3-8:複數個晶片
4:密封部
4a:正面
4a1:凹部
4a11:底面
4a12:側面
4ai:正面
4a1i:凹部
4i:密封部
4b:背面
5:晶片
5a:正面
5b:背面
6-1~6-8:複數個端子
7-1~7-4:複數個端子
8:電極
9:焊球凸塊
10:基板
10a:正面
10b:背面
11:電極圖案
12:通孔電極
13:導電層
14:通孔電極
15:預浸體層
16:核心層
20:上部構造體
21:密封部
22:密封部
23:外部電極
30:下部構造體
40:緩衝構件
101:半導體裝置
107-1~107-4:複數個端子
120:上部構造體
122:密封部
123:密封部
123a:正面
123ai:正面
123i:密封部
130:下部構造體
201:半導體裝置
240:再配線層
241:配線層
242:插塞層
243:配線層
244:插塞層
245:配線層
246:層間絕緣膜
圖1係表示第1實施方式之半導體裝置之構成之剖視圖。
圖2A~圖2D係表示第1實施方式之半導體裝置之製造方法之剖視圖。
圖3係表示第1實施方式之半導體裝置之製造方法之俯視圖。
圖4A~圖4C係表示第1實施方式之半導體裝置之製造方法之剖視圖。
圖5A~圖5C係表示第1實施方式之半導體裝置之製造方法之剖視圖。
圖6A~圖6C係表示第1實施方式之第1變化例之半導體裝置之製造方法的剖視圖。
圖7係表示第1實施方式之第2變化例之半導體裝置之製造方法之俯視圖。
圖8係表示第1實施方式之第3變化例之半導體裝置之製造方法之俯視圖。
圖9係表示第1實施方式之第4變化例之半導體裝置之製造方法之俯視圖。
圖10係表示第2實施方式之半導體裝置之構成之剖視圖。
圖11A及圖11B係表示第2實施方式之半導體裝置之製造方法之剖視圖。
圖12A~圖12C係表示第2實施方式之半導體裝置之製造方法之剖視圖。
圖13A~圖13C係表示第2實施方式之半導體裝置之製造方法的剖視圖。
圖14係表示第3實施方式之半導體裝置之構成之剖視圖。
以下,參照附圖,對實施方式之半導體裝置詳細地進行說明。再者,本發明並不受該等實施方式限定。
第1實施方式之半導體裝置係將複數個晶片積層,使端子(縱交線
(vertical wire))從各晶片沿著積層方向延伸而構成。半導體裝置1例如按圖1所示之方式構成。
圖1係表示半導體裝置1之構成之剖視圖。以下,將與支持體2之主面垂直之方向設為Z方向,將在與Z方向垂直之面內相互正交之2個方向設為X方向及Y方向。
半導體裝置1具有支持體2、複數個晶片3-1~3-8、密封部4、晶片5、複數個端子6-1~6-8、複數個端子7-1~7-4、密封部22、外部電極23、基板10及密封部21。
支持體2係於XY方向上延伸之板狀構件。支持體2於沿著XY平面觀察時具有矩形形狀。支持體2具有適於支持複數個晶片3-1~3-8之剛性。支持體2可由適於具有規定剛性之材料(例如,玻璃、玻璃布、矽)等形成。
複數個晶片3-1~3-8配置於支持體2之-Z側,分成相等之兩部分呈階梯狀積層。複數個晶片3-1~3-4於複數個晶片3-5~3-8之-Y側呈階梯狀積層。複數個晶片3-5~3-8於複數個晶片3-5~3-8之+Y側呈階梯狀積層。各晶片3-1~3-8之功能與晶片5不同,例如為能夠記憶資料之記憶體晶片。
密封部4將複數個晶片3-1~3-8密封。密封部4可由塑模樹脂等具有
熱塑性之第1絕緣物形成。密封部4具有正面4a及背面4b。背面4b與支持體2相接。正面4a係與支持體2為相反側之主面。密封部4於正面4a具有凹部4a1。凹部4a1係密封部4中從正面4a向+Z側凹陷之空間。凹部4a1只要能收容晶片5,則可採用任意形狀。凹部4a1配置於能收容晶片5之位置,亦可配置於例如沿著XY平面觀察時正面4a之中央附近(參照圖3)。
凹部4a1之深度較晶片3-4、3-8相對於正面4a之Z方向深度小。背面4b之Z位置較晶片3-4、3-8之表面(-Z側之面)之Z位置更靠-Z側。
凹部4a1具有底面4a11及側面4a12。底面4a11沿著XY方向延伸。底面4a11與複數個晶片3-1~3-8於Z方向上分離。底面4a11與複數個晶片3-1~3-4中最靠-Z側之晶片3-4於Z方向上分離,與複數個晶片3-5~3-8中最靠-Z側之晶片3-8於Z方向上分離。底面4a11可與晶片3-4之正面3a大致平行,亦可與晶片3-8之正面3a大致平行。凹部4a1可為例如大致長方體形狀之孔,亦可於沿著XY平面觀察時具有大致矩形形狀。凹部4a1之開放端之面積大於底面4a11之面積。凹部4a1之開放端之X方向寬度大於底面4a11之X方向寬度。凹部4a1之開放端之Y方向寬度大於底面4a11之Y方向寬度。
凹部4a1之開放端之面積大於晶片5之面積。凹部4a1之開放端之X方向寬度大於晶片5之X方向寬度。凹部4a1之開放端之Y方向寬度大於晶片5之Y方向寬度。
底面4a11之面積大於晶片5之面積。底面4a11之X方向寬度大於晶片5之X方向寬度。底面4a11之Y方向寬度大於晶片5之Y方向寬度。
複數個端子6-1~6-8對應於複數個晶片3-1~3-8。各端子6-1~6-8從對應之晶片3中與支持體2為相反側之面(-Z側之面)3a沿著-Z方向延伸,貫通密封部4而到達正面4a。各端子6-1~6-8亦可複數個連接於對應之晶片3。各端子6-1~6-8亦可沿著-Z方向直線延伸。各端子6-1~6-8亦可為直立型端子,具有能夠維持直線形狀之剛性。
例如,各端子6-1~6-8之直徑可較用於打線接合型安裝之金屬線之直徑粗。各端子6-1~6-8係垂直延伸之金屬線,亦被稱為縱交線。藉由將各端子6-1~6-8以直立型構成,可容易實現各端子6-1~6-8間之配置間距之窄間距化。
於將複數個晶片3-1~3-8分成兩半部分呈階梯狀積層之情形時,複數個端子6-1~6-8亦可分成兩半部分使長度呈階梯狀不同。複數個端子6-1~6-4之+Z側端部之Z位置於複數個端子6-5~6-8之-Y側呈階梯狀變低。複數個端子6-5~6-8之+Z側端部之Z位置於複數個端子6-5~6-8之+Y側呈階梯狀變低。複數個端子6-1~6-8之-Z側端部之Z位置亦可相互均等。各端子6-1~6-8之-Z側端部經由電極8及焊球凸塊(ball bump)9而連接於基板10之電極圖案11。各端子6-1~6-8可由以金屬(例如金)為主成分之導電物形成。
晶片5配置於支持體2之-Z側,且配置於複數個晶片3-1~3-8之-Z側。晶片5之功能與晶片3不同,例如係能夠控制複數個晶片3-1~3-8之控制器晶片。晶片5電性連接於複數個晶片3-1~3-8。晶片5較理想為配置於半導體裝置1中沿著XY平面觀察時之中央附近,以此使得朝向各晶片3-1~3-8之配線長度一樣長。因此,晶片5配置於凹部4a1內。
晶片5之背面(+Z側之面)5b亦可與凹部4a1之底面4a11於-Z方向上稍微分離。如此,晶片5與複數個晶片3-1~3-8中最靠-Z側之晶片3-4、3-8於-Z方向上分離。
複數個端子7-1~7-4配置於晶片5之正面(-Z側之面)5a。各端子7-1~7-4亦可沿著-Z方向呈柱狀延伸。各端子7-1~7-4之XY方向上之最大寬度較各端子6-1~6-8之XY方向上之最大寬度大。各端子7-1~7-4可由複數個層之積層而形成。複數個層可分別由焊料合金層、銅合金層等以合金為主成分之導電物形成。複數個層可包含組成互不相同之層,亦可為不同組成之層與相同組成之層混合存在。
複數個端子7-1~7-4之+Z側端部與晶片5之正面5a耦合。複數個端子7-1~7-4之-Z側端部之Z位置亦可相互均等。複數個端子7-1~7-4之-Z側端部距離支持體2之Z方向高度可與複數個端子6-1~6-8之-Z側端部距離支持體2之Z方向高度均等。各端子7-1~7-4之-Z側端部經由電極8及焊球凸塊9而連接於基板10之電極圖案11。各端子7-1~7-4係柱狀凸塊,亦被稱為柱形凸塊。藉由將各端子7-1~7-4以柱狀構成,可容易實現各端子7-
1~7-4間之配置間距之窄間距化。
密封部22填滿凹部4a1,且將晶片5密封。密封部22填滿密封部4與基板10之間隙,並將電極8、焊球凸塊9及電極圖案11密封。密封部22覆蓋密封部4之-Z側之面,並且覆蓋基板10之正面10a。密封部22可由塑模樹脂等具有熱塑性之第2絕緣物形成。第2絕緣物之組成與第1絕緣物不同。
密封部21從外側覆蓋支持體2、密封部4、密封部22並進行密封。密封部21可到達基板10之正面10a。密封部21可由塑模樹脂等具有熱塑性之第3絕緣物形成。第3絕緣物之組成與第1絕緣物不同,與第2絕緣物亦不同。
密封部4、密封部21、密封部22亦可為在絕緣性樹脂中包含無機物填料所得者。此時,密封部4、密封部21之填料之含量可較密封部22之填料之含量多。
密封部4、密封部21之熱膨脹率可分別小於密封部22之熱膨脹率。
密封部4、密封部21之楊氏模數可分別大於密封部22之楊氏模數。
基板10具有複數個電極圖案11、複數個通孔電極12、導電層13、複數個通孔電極14、預浸體層15及核心層16。複數個電極圖案11分別露出於基板10之正面10a,複數個通孔電極14分別露出於基板10之背面10b。
各電極圖案11、各通孔電極12、導電層13、各通孔電極14可分別由以導電物(例如銅)為主成分之材料形成。預浸體層15、核心層16可分別由以絕緣物(例如塑料等有機系物質)為主成分之材料形成。
再者,圖1中,為了簡化表示,示出了導電層13連接於複數個電極圖案11、複數個通孔電極12、複數個通孔電極14之形態,但實際上可形成規定之配線,選擇性地連接規定之電極圖案11、規定之通孔電極12、規定之通孔電極14。
複數個外部電極23配置於基板10之背面10b,且分別與通孔電極14接合。複數個外部電極23之X方向之配置間距大於複數個端子6-1~6-8之X方向之配置間距。複數個外部電極23之X方向之配置間距大於複數個端子7-1~7-4之X方向之配置間距。同樣,複數個外部電極23之Y方向之配置間距大於複數個端子6-1~6-8之Y方向之配置間距。複數個外部電極23之Y方向之配置間距大於複數個端子7-1~7-4之Y方向之配置間距。由此,能夠實現各端子6-1~6-8間之配置間距、各端子7-1~7-4間之配置間距之窄間距化,同時容易將半導體裝置1連接於寬間距之外部端子(例如母板上之端子)。
繼而,使用圖1~圖5C對半導體裝置1之製造方法進行說明。圖1係表示半導體裝置1之構成之剖視圖,亦用作表示半導體裝置1之製造方法之剖視圖。圖2A~圖2D、圖4A~圖4C、圖5A~圖5C係表示半導體裝置1之製造方法之剖視圖。圖3係表示半導體裝置1之製造方法之俯視圖。
圖2A所示之步驟中,準備支持體2。支持體2係沿著XY方向延伸之板狀構件。支持體2可由適於具有規定剛性之材料(例如,玻璃、玻璃布、矽)等形成。複數個晶片3-1~3-8呈階梯狀積層於支持體2之-Z側之面2a。
例如,於支持體2之-Z側之面2a中之-Y側區域,可經由接著劑或接著膜等接著晶片3-1。晶片3-2可以XY平面位置例如向+Y側偏移之狀態接著於晶片3-1之-Z側。晶片3-3可以XY平面位置例如向+Y側偏移之狀態經由接著劑或接著膜等接著於晶片3-2之-Z側。晶片3-4可以XY平面位置例如向+Y側偏移之狀態接著於晶片3-3之-Z側。
藉此,於支持體2之面2a之-Y側區域,複數個晶片3-1~3-4以Y位置向+Y側依次偏移之方式呈階梯狀積層。各晶片3-1~3-4以正面3a為-Z側之狀態面朝上安裝。複數個晶片3-1~3-4之正面3a距離支持體2之Z方向高度依次變高。同樣,於支持體2之面2a之+Y側區域,複數個晶片3-5~3-8以Y位置向-Y側依次偏移之方式呈階梯狀積層。各晶片3-5~3-8以正面3a為-Z側之狀態面朝上安裝。複數個晶片3-5~3-8之正面3a距離支持體2之Z方向高度依次變高。
圖2B所示之步驟中,複數個端子6-1~6-8與複數個晶片3-1~3-8耦合。複數個端子6-1~6-8對應於複數個晶片3-1~3-8。複數個端子6-1~6-8之長度對應於複數個晶片3-1~3-8距離支持體2之Z方向高度(例如,用於吸收Z方向高度之差異),可互不相同。各端子6-1~6-8於豎立在Z方向
之姿勢下,其+Z側之端部可與所對應之晶片3之正面3a上之電極墊耦合。再者,亦可從各晶片3延伸出複數個端子6(參照圖3)。
例如,對應於複數個晶片3-1~3-4之正面3a距離支持體2之Z方向高度依次變高,複數個端子6-1~6-4之長度會依次變短。藉此,複數個端子6-1~6-4於已與複數個晶片3-1~3-4耦合之狀態下,其-Z側端部之Z位置相互靠近。同樣,對應於複數個晶片3-5~3-8之正面3a距離支持體2之Z方向高度依次變高,複數個端子6-5~6-8之長度會依次變短。藉此,複數個端子6-5~6-8於已與複數個晶片3-5~3-8耦合之狀態下,其-Z側端部之Z位置相互靠近。
圖2C所示之步驟中,於支持體2之-Z側形成密封部4i。即,利用第1絕緣物覆蓋複數個晶片3-1~3-8之正面及側面,並且利用第1絕緣物覆蓋複數個端子6-1~6-8之側面及端面,以此形成密封部4i。密封部4i可由塑模樹脂等具有熱塑性之第1絕緣物形成。密封部4i距離支持體2之Z方向高度較最靠-Z側之晶片3-4、3-8之Z方向高度高,且較各端子6-1~6-8之Z方向高度高。
圖2D所示之步驟中,於密封部4i之-Z側之正面4ai形成凹部4a1i。凹部4a1i之形成深度與規定深度和後續步驟之研磨厚度之合計相對應。規定深度形成為小於晶片3-4、3-8相對於正面4ai之Z方向深度。規定深度亦可為後續步驟中將晶片5安裝於基板10之狀態下之晶片5距離基板10之Z方向高度以上。凹部4a1i亦可形成為在分別沿著XZ剖面觀察及沿著YZ剖面觀
察時呈錐形,即,以越靠近底面4a11開口寬度越小之方式使側面4a12傾斜。例如,凹部4a1i可由模具成形而形成。準備模具,該模具包含有在XY方向中央附近具有基座部之平坦部,使第1絕緣物加熱熔融後流入模具中,冷卻後進行脫模,由此可形成在表面之XY方向中央附近具有凹部4a1i之密封部4i。此時,藉由使基座部為錐形,可容易進行脫模,能夠提高形成密封部4i之處理之處理量。或者,凹部4a1i亦可藉由雷射加工而形成。於形成具有平坦表面之密封部4i之後,一面藉由NC(Numerical Control,數位控制)控制等在其表面將照射位置控制為矩形,一面對上述表面照射雷射,藉此可形成在表面之中央附近具有凹部4a1i之密封部4i。此時,就雷射加工之特性而言,凹部4a1i可形成為錐形。
如圖3所示,凹部4a1i在沿著XY平面觀察時形成於正面4ai之中央附近。圖3中,例示了凹部4a1i形成為大致長方體形狀之孔(沿著XY平面觀察時為大致矩形)之構成。凹部4a1i以其X方向寬度大於晶片5之X方向寬度之方式形成。凹部4a1i以其Y方向寬度大於晶片5之Y方向寬度之方式形成。藉由將凹部4a1i以此種方式構成,能夠於後續步驟中將晶片5收容在凹部4a1i內。
圖4A所示之步驟中,對密封部4i之正面4ai進行研磨。例如,將研磨裝置之研磨機抵接於密封部4i之正面4ai,研磨機以與接觸面垂直之軸為中心而旋轉,使研磨機連續旋轉直至各端子6-1~6-8之-Z側端部露出於密封部4之正面4a為止。密封部4之Z方向厚度比密封部4i變薄相當於研磨之厚度。凹部4a1之深度比凹部4a1i減小相當於研磨之厚度。
圖4B所示之步驟中,於密封部4之正面4a形成複數個電極8。複數個電極8對應於複數個端子6-1~6-8。各電極8連接於所對應之端子6之-Z側之端部。各電極8由金屬(例如銅)等導電物形成。藉此,可獲得複數個晶片3-1~3-8呈階梯狀積層且面朝上安裝並被密封之上部構造體20。
在圖4C所示之步驟中,準備基板10。露出於基板10之正面10a之複數個電極圖案11分別與焊球凸塊9耦合。沿著XY平面觀察時基板10之中央附近之複數個焊球凸塊9分別與電極8耦合。
另一方面,準備晶片5。於晶片5之正面5a配置複數個電極墊。準備與複數個電極墊對應之複數個端子7-1~7-4。複數個端子7-1~7-4各自之一端與晶片5之正面5a上之對應之電極墊耦合。又,複數個端子7-1~7-4與沿著XY平面觀察時基板10之中央附近之複數個電極8相對應。複數個端子7-1~7-4各自之另一端與電極8耦合。即,晶片5以正面5a為-Z側之狀態面朝下安裝於基板10。藉此,獲得將晶片5面朝下安裝於基板10之下部構造體30。
以正面4a與正面10a相對之方式使上部構造體20與下部構造體30對向配置。從Z方向透視時,以上部構造體20中之電極8與下部構造體30中之焊球凸塊9重疊之方式,使上部構造體20與下部構造體30之相對位置對準。此時,從Z方向透視時,晶片5包含於凹部4a1之內側(參照圖3)。
圖5A所示之步驟中,上部構造體20及下部構造體30於Z方向上相對靠近。上部構造體20中之電極8與下部構造體30中之焊球凸塊9相互耦合。晶片5被收容於密封部4之凹部4a1內。
圖5B所示之步驟中,上部構造體20與下部構造體30之間隙被密封部22密封。密封部22以填滿凹部4a1並且填滿密封部4及基板10之間隙之方式填充。密封部22可由塑模樹脂等具有熱塑性之第2絕緣物形成。藉此,晶片5被密封部22密封,並且電極8、焊球凸塊9被密封部22密封。
圖5C所示之步驟中,上部構造體20之外側被密封部21密封。密封部21形成為從外側覆蓋支持體2、密封部4、密封部22。密封部21亦可形成為到達基板10之正面10a。密封部21可由塑模樹脂等具有熱塑性之第3絕緣物形成。第3絕緣物之組成與第1絕緣物不同,與第2絕緣物亦不同。
圖1所示之步驟中,於基板10之背面10b安裝複數個外部電極23。可對露出於基板10之背面10b之通孔電極14接合外部電極23。然後,藉由切削進行單片化,從而獲得半導體裝置1。
如上所述,於第1實施方式中,在半導體裝置1中,於將積層之複數個晶片3-1~3-8密封之密封部4之正面4a之沿著XY平面觀察時的中央附近設置凹部4a1。於凹部4a1內收容晶片5。藉此,容易將晶片5相對於複數個晶片3-1~3-8以大致等距離配線,從而能夠提供一種具有適於將複數個晶片3-1~3-8及晶片5分別適當配置之構造之半導體裝置1。
此處,當製造半導體裝置1時,考慮將複數個晶片3-1~3-8呈階梯狀積層於支持體2上,於最上方(最靠-Z側)之晶片3-4、3-8上接著晶片5的情況。此種情形時,可能會因接著時之應力等而導致晶片3-4、3-8彎曲,使得晶片5從恰當之平面方向傾斜。
對此,於第1實施方式中,在半導體裝置1中,收容晶片5之凹部4a1之底面4a11與被密封部4密封之複數個晶片3-1~3-8中之最上方(最靠-Z側)之晶片3-4、3-8之正面3a於Z方向上分離。藉此,能夠提供一種具有適於將晶片5在不會從恰當之平面方向傾斜的情況下安裝而製造之構造的半導體裝置1。
此處,當製造半導體裝置1時,考慮利用密封部4一併密封連接於晶片3-1~3-8之直立型端子6-1~6-8與安裝於晶片5之柱狀端子7-1~7-4。此種情形時,於端子6-1~6-8與端子7-1~7-4之間,前端之高度存在差異。為了吸收此種差異,將端子6-1~6-8及端子7-1~7-4形成得較高,然後藉由研磨使高度一致。即,因增高了具有較端子6-1~6-8複雜之構造(複數個膜之積層構造)之端子7-1~7-4,有可能會導致半導體裝置1之成本增加。
對此,於第1實施方式中,在半導體裝置1中,直立型端子6-1~6-8與作為連接目標之晶片3-1~3-8均被密封部4密封,其-Z側端部露出於密封部4之正面4a。柱狀端子7-1~7-4安裝於密封部4之凹部4a1內所收容之
晶片5上。藉此,能夠抑制密封部4之密封對端子6-1~6-8及端子7-1~7-4間之不均之影響,從而能夠將端子7-1~7-4抑制得較低。即,能夠提供一種適於降低製造成本之半導體裝置1。
再者,如圖6C所示,亦可於晶片5與凹部4a1之底面4a11之間介置緩衝構件40。圖6A~圖6C分別係表示第1實施方式之第1變化例之半導體裝置之製造方法的剖視圖。
例如,於半導體裝置1之製造方法中,亦可在進行圖2A~圖2D所示之步驟之後,進行圖6A所示之步驟。於圖6A所示之步驟中,在凹部4a1之底面4a11配置緩衝構件40。緩衝構件40係於XY方向上延伸之板狀構件。緩衝構件40亦可由樹脂系黏著劑等具有柔軟性、彈性之絕緣材料形成。緩衝構件40以覆蓋底面4a11之主要部分之方式配置。
如圖3中兩點鏈線所示,緩衝構件40以沿著XY平面觀察時包含於底面4a11之內側並且內側包含晶片5之方式配置。緩衝構件40之XY面積小於底面4a11之XY面積,大於晶片5之XY面積。緩衝構件40之X方向寬度小於底面4a11之X方向寬度,大於晶片5之X方向寬度。緩衝構件40之Y方向寬度小於底面4a11之Y方向寬度,大於晶片5之Y方向寬度。
於進行圖4A~圖4C所示之步驟之後,代替圖5A所示之步驟,而進行圖6B所示之步驟。於圖6B所示之步驟中,上部構造體20及下部構造體30於Z方向上相對靠近。與第1實施方式相同的是,上部構造體20中之電極8
與下部構造體30中之焊球凸塊9相互耦合。晶片5之背面與緩衝構件40接觸,並且晶片5被收容於密封部4之凹部4a1內。此時,晶片5稍微壓抵於緩衝構件40,但由於緩衝構件40具有彈性,故能抑制對晶片5之應力。
代替圖5B所示之步驟而進行圖6C所示之步驟。於圖6C所示之步驟中,當利用密封部22將上部構造體20與下部構造體30之間隙密封時,覆蓋緩衝構件40及晶片5之露出面並且填滿凹部4a1。此時,凹部4a1之底面4a11之主要部分被緩衝構件40覆蓋,因此,能夠抑制密封部22中產生空隙,提高安裝品質。
然後,進行圖5C所示之步驟、圖1所示之步驟,以與第1實施方式相同之方式來製造半導體裝置1。
如此,於第1實施方式之第1變化例之半導體裝置中,在晶片5與凹部4a1之底面4a11之間介置緩衝構件40。由此,能夠提供具有適於提高安裝品質之構造之半導體裝置1。
又,凹部4a1i只要能夠收容晶片5,則可為任意形狀,例如亦可形成為圖7所示之橫I字狀之溝槽(沿著XY平面觀察時為大致橫I字狀)。圖7係表示第1實施方式之第2變化例之半導體裝置1之製造方法之俯視圖。圖7中,例示了凹部4a1i形成為橫I字狀之溝槽之構成。此種情形時,與第1實施方式不同的是,凹部4a1之開放端之Y方向寬度與底面4a11之Y方向寬度均等。再者,與第1實施方式相同的是,凹部4a1i之開放端之面積大於底
面4a11之面積,凹部4a1i之開放端之X方向寬度大於底面4a11之X方向寬度。
端子6-1~6-8露出於凹部4a1i之底面。端子露出面之高度較低。因此,亦可另外形成電極來補足端子之高度。或者,亦可將電極8或焊球凸塊9形成得較高。
凹部4a1i亦可形成為當沿著XZ剖面觀察時呈錐形,即,以越接近底面4a11開口寬度越小之方式使側面4a12傾斜。例如,凹部4a1i亦可利用切割加工來形成。於形成具有平坦表面之密封部4i之後,一面藉由NC控制等在其表面上控制接觸位置一面使切割刀於X方向上接觸上述表面並旋轉,由此,可形成在表面之X方向中央附近具有槽狀凹部4a1i之密封部4i。此時,就切割加工之特性而言,凹部4a1i可形成為當沿著XZ剖面觀察時呈錐形。或者,凹部4a1i亦可藉由模具成形而形成。準備模具,該模具包含有於X方向中央附近具有橫I字狀基座部之平坦部,使第1絕緣物加熱熔融後流入模具,冷卻後進行脫模,由此,可形成在表面之X方向中央附近具有凹部4a1i之密封部4i。此時,藉由使基座部為錐形,可容易進行脫模,從而可提高形成密封部4i之處理之處理量。或者,凹部4a1i亦可利用雷射加工而形成。於形成具有平坦表面之密封部4i之後,一面藉由NC控制等在其表面將照射位置控制為橫條紋狀,一面對上述表面照射雷射,由此,可形成在表面之X方向中央附近具有凹部4a1i之密封部4i。此時,就雷射加工之特性而言,凹部4a1i可形成為錐形。
又,凹部4a1i例如亦可形成為圖8所示之縱I字狀之溝槽(沿著XY平面
觀察時為大致縱I字狀)。圖8係表示第1實施方式之第3變化例之半導體裝置1之製造方法的俯視圖。圖8中,例示了凹部4a1i形成為縱I字狀之溝槽之構成。此種情形時,與第1實施方式不同的是,凹部4a1之開放端之X方向寬度與底面4a11之X方向寬度均等。再者,與第1實施方式相同的是,凹部4a1i之開放端之面積大於底面4a11之面積,凹部4a1i之開放端之Y方向寬度大於底面4a11之Y方向寬度。
凹部4a1i亦可形成為當沿著YZ剖面觀察時呈錐形,即,以越接近底面4a11開口寬度越小之方式使側面4a12傾斜。例如,凹部4a1i亦可利用切割加工而形成。於形成具有平坦表面之密封部4i之後,一面藉由NC控制等在其表面控制接觸位置,一面使切割刀於Y方向上接觸上述表面並旋轉,由此,可形成在表面之Y方向中央附近具有槽狀凹部4a1i之密封部4i。此時,就切割加工之特性而言,凹部4a1i可形成為當沿著YZ剖面觀察時呈錐形。或者,凹部4a1i亦可藉由模具成形而形成。準備模具,該模具包含有在Y方向中央附近具有縱I字狀基座部之平坦部,使第1絕緣物加熱熔融後流入模具,冷卻後進行脫模,由此,可形成在表面之Y方向中央附近具有凹部4a1i之密封部4i。此時,藉由使基座部為錐形,可容易進行脫模,從而可提高形成密封部4i之處理之處理量。或者,凹部4a1i亦可利用雷射加工而形成。於形成具有平坦表面之密封部4i之後,一面藉由NC控制等在其表面將照射位置控制為縱條紋狀,一面照射雷射,由此,可形成在表面之Y方向中央附近具有凹部4a1i之密封部4i。此時,就雷射加工之特性而言,凹部4a1i可形成為錐形。
又,凹部4a1i例如亦可形成為圖9所示之十字狀之溝槽(沿著XY平面觀察時為大致十字狀)。圖9係表示第1實施方式之第4變化例之半導體裝置1之製造方法的俯視圖。圖9中,例示了凹部4a1i形成為十字狀溝槽之構成。此種情形時,與第1實施方式不同的是,凹部4a1之開放端之X方向寬度於Y方向中央附近與底面4a11之X方向寬度均等,於Y方向兩端附近大於底面4a11之X方向寬度,凹部4a1之開放端之Y方向寬度於X方向中央附近與底面4a11之Y方向寬度均等,於X方向兩端附近大於底面4a11之Y方向寬度。再者,與第1實施方式相同的是,凹部4a1i之開放端之面積大於底面4a11之面積。
端子6-1~6-8露出於凹部4a1i之底面。端子露出面之高度較低。因此,亦可另外形成電極以補足端子之高度。或者,亦可將電極8或焊球凸塊9形成得較高。
凹部4a1i之X方向兩端附近之部分亦可形成為當沿著YZ剖面觀察時呈錐形,即,以越接近底面4a11開口寬度越小之方式使側面4a12傾斜。凹部4a1i之Y方向兩端附近之部分亦可形成為當沿著XZ剖面觀察時呈錐形,即,以越接近底面4a11開口寬度越小之方式使側面4a12傾斜。例如,凹部4a1i亦可利用切割加工來形成。於形成具有平坦表面之密封部4i之後,一面藉由NC控制等在其表面控制接觸位置,一面使切割刀於X方向上接觸上述表面並旋轉,並且使切割刀於Y方向上接觸上述表面並旋轉,由此,可形成表面具有交叉槽狀之凹部4a1i之密封部4i。此時,就切割加工之特性而言,凹部4a1i之X方向兩端附近之部分可形成為當沿著YZ剖面觀察時呈錐形,且Y方向兩端附近之部分形成為當沿著XZ剖面觀察時
呈錐形。或者,凹部4a1i亦可藉由模具成形而形成。準備模具,該模具包含具有十字狀基座部之平坦部,使第1絕緣物加熱熔融後流入模具,冷卻後進行脫模,由此,可形成表面具有十字狀凹部4a1i之密封部4i。此時,藉由使基座部為錐形,可容易進行脫模,從而可提高形成密封部4i之處理之處理量。或者,凹部4a1i亦可利用雷射加工而形成。於形成具有平坦表面之密封部4i之後,一面藉由NC控制等在其表面將照射位置控制為十字狀,一面對上述表面照射雷射,由此,可形成表面具有十字狀凹部4a1i之密封部4i。此時,就雷射加工之特性而言,凹部4a1i之X方向兩端附近之部分可形成為當沿著YZ剖面觀察時呈錐形,Y方向兩端附近之部分形成為當沿著XZ剖面觀察時呈錐形。
繼而,對第2實施方式之半導體裝置進行說明。以下,以與第1實施方式不同之部分為中心進行說明。
於第1實施方式中,例示了包含晶片5之背面與凹部4a1之底面4a11分離之構造的半導體裝置1,但於第2實施方式中,例示包含晶片5之背面與凹部4a1之底面4a11接觸之構造的半導體裝置101。
具體而言,如圖10所示,半導體裝置101中,晶片5之背面5b與凹部4a1之底面4a11接觸。圖10係表示第2實施方式之半導體裝置101之構成之剖視圖。與第1實施方式相比,晶片5與複數個晶片3-1~3-8中最上方之晶片3-4、3-8之Z方向距離變得更小,因此,能夠實現半導體裝置101之低背
化。
再者,於晶片5與晶片3-4、3-8之間介置有密封部4。藉此,與第1實施方式相同的是,能夠將晶片5在沿著XY平面觀察時沿著XY方向安裝於密封部4之中央附近。
半導體裝置101具有複數個端子107-1~107-4、密封部122來代替複數個端子7-1~7-4、密封部22(參照圖1),亦具有密封部123。複數個端子107-1~107-4之-Z側端部之Z位置與複數個端子6-1~6-8之-Z側端部之Z位置大致相同。密封部123填滿凹部4a1並且密封晶片5。密封部123之-Z側之面123a與密封部4之-Z側之面4a形成連續面,且Z位置大致相同。密封部123可由塑模樹脂等具有熱塑性之第4絕緣物形成。第4絕緣物之組成與第1絕緣物不同。第4絕緣物之組成可與第2絕緣物不同,亦可與第3絕緣物不同。
密封部122及密封部123亦可為在絕緣性樹脂中包含無機物填料所得者。此時,密封部4、密封部21、密封部122之填料之含量可多於密封部123之填料之含量。密封部4、密封部21之填料之含量亦可多於密封部122之填料之含量。
密封部4、密封部21、密封部122之熱膨脹率可小於密封部123之熱膨脹率。密封部4、密封部21之熱膨脹率亦可小於密封部122之熱膨脹率。
密封部4、密封部21、密封部122之楊氏模數可大於密封部123之楊氏模數。密封部4、密封部21之楊氏模數亦可大於密封部122之楊氏模數。
再者,與第1實施方式相同的是,各端子6-1~6-8之-Z側端部經由電極8及焊球凸塊9而連接於基板10之電極圖案11,各端子7-1~7-4之-Z側端部經由電極8及焊球凸塊9而連接於基板10之電極圖案11。
又,如圖11A~圖13C所示,半導體裝置101之製造方法於以下方面與第1實施方式不同。圖11A~圖11B、圖12A~圖12C、圖13A~圖13C係表示半導體裝置101之製造方法之剖視圖。
例如,於半導體裝置101之製造方法中,亦可在進行圖2A~圖2D所示之步驟之後,進行圖11A所示之步驟。於圖11A所示之步驟中,準備晶片5及複數個端子107-1~107-4。複數個端子107-1~107-4各自之一端與晶片5之表面上所對應之電極墊耦合。於凹部4a1i之底面4a11配置與複數個端子107-1~107-4耦合之晶片5。如圖3中單點鏈線所示,晶片5以沿著XY平面觀察時包含於底面4a11之內側之方式配置。晶片5亦可為其背面5b經由接著劑或接著膜等而接著於底面4a11。
此時,於凹部4a1i內配置有晶片5之狀態下,各端子6-1~6-8之-Z側端部之Z位置與各端子107-1~107-8之-Z側端部之Z位置可在能夠藉由研磨而對齊之範圍內互不相同。
於圖11B所示之步驟中,在凹部4a1i內填充第4絕緣物質。即,利用第4絕緣物覆蓋晶片5之表面及側面,並且利用第4絕緣物覆蓋複數個端子107-1~107-8之側面及端面,以此形成密封部123i。藉此,形成填滿凹部4a1i之密封部123i。第4絕緣物質之組成與第1絕緣物不同。第4絕緣物之組成可與第2絕緣物不同,亦可與第3絕緣物不同。
此時,密封部4之正面4ai之Z位置與密封部123之正面123ai之Z位置亦可在能夠藉由研磨而對齊之範圍內互不相同。
於圖12A所示之步驟中,對密封部4i之正面4ai及密封部123i之正面123ai進行研磨。例如,研磨裝置之研磨機抵接於密封部4i之正面4ai及密封部123i之正面123ai,研磨機以與接觸面垂直之軸為中心旋轉,使研磨機連續旋轉,直至各端子6-1~6-8之-Z側端部露出於密封部4之正面4a並且各端子107-1~107-8之-Z側端部露出於密封部123之正面123a為止。凹部4a1之深度相比凹部4a1i(參照圖2D)減小了相當於研磨厚度之量。密封部4之Z方向厚度相比密封部4i薄了相當於研磨厚度之量。凹部4a1之深度相比凹部4a1i減小了相當於研磨厚度之量。密封部123之Z方向厚度相比密封部123i薄了相當於研磨厚度之量。
此時,各端子6-1~6-8之-Z側端部之Z位置與各端子107-1~107-8之-Z側端部之Z位置大致相同。
於圖12B所示之步驟中,在密封部4之正面4a形成複數個電極8,在密
封部123之正面123a形成複數個電極8。形成於密封部4之正面4a之複數個電極8與第1實施方式相同。形成於密封部123之正面123a之複數個電極8對應於複數個端子107-1~107-4。形成於正面123a之各電極8電性連接於所對應之端子107之-Z側之端部。藉此,可獲得複數個晶片3-1~3-8呈階梯狀積層且面朝上安裝並被密封、同時晶片5以能夠面朝下安裝之狀態被密封之上部構造體120。
於圖12C所示之步驟中,準備基板10。露出於基板10之正面10a之複數個電極圖案11分別與焊球凸塊9耦合。可獲得構成為晶片5能夠面朝下安裝之狀態之下部構造體130。
以正面4a、123a與正面10a相對之方式將上部構造體120與下部構造體130對向配置。從Z方向透視時,以上部構造體120中之電極8與下部構造體130中之焊球凸塊9重疊之方式,進行上部構造體120與下部構造體130之相對位置對準。
於圖13A所示之步驟中,上部構造體120與下部構造體130於Z方向上相對接近。上部構造體120中之電極8與下部構造體130中之焊球凸塊9相互耦合。
於圖13B所示之步驟中,利用密封部122將上部構造體120與下部構造體130之間隙密封。密封部122以填滿密封部4、123及基板10之間隙之方式填充。密封部122可由塑模樹脂等具有熱塑性之第2絕緣物形成。藉
此,電極8、焊球凸塊9被密封部122密封。
於圖13C所示之步驟中,上部構造體120之外側被密封部21密封。密封部21形成為從外側覆蓋支持體2、密封部4、密封部122。密封部21亦可形成為到達基板10之正面10a。密封部21可由塑模樹脂等具有熱塑性之第3絕緣物形成。第3絕緣物之組成與第1絕緣物不同,與第2絕緣物亦不同。
於圖10所示之步驟中,在基板10之背面10b安裝複數個外部電極23。外部電極23可與露出於基板10之背面10b之通孔電極14接合。然後,藉由切削進行單片化,獲得半導體裝置101。
如上所述,於第2實施方式中,在半導體裝置101中,於將積層之複數個晶片3-1~3-8密封之密封部4之正面4a之沿著XY平面觀察時之中央附近設置凹部4a1。於凹部4a1內收容晶片5。藉此,容易將晶片5相對於複數個晶片3-1~3-8以大致等距離配線,因此,能夠提供一種具有適於將複數個晶片3-1~3-8及晶片5分別恰當地配置之構造之半導體裝置101。
繼而,對第3實施方式之半導體裝置進行說明。以下,以與第1實施方式及第2實施方式不同之部分為中心進行說明。
於第2實施方式中,例示了包含將端子6-1~6-8、107-1~107-4經由
基板10連接於外部電極23之構造的半導體裝置101,但於第3實施方式中,例示包含將端子6-1~6-8、107-1~107-4經由再配線層240連接於外部電極23之構造的半導體裝置201。
具體而言,如圖14所示,半導體裝置201省略了電極8、焊球凸塊9、密封部21(參照圖10),且配置再配線層240以代替基板10。圖14係表示第3實施方式之半導體裝置201之構成之剖視圖。與第2實施方式相比,端子6-1~6-8、107-1~107-4與外部電極23之Z方向距離變得更小,並且Z高度降低了相當於密封部21之厚度之量,因此,可實現半導體裝置201之更低背化。
再者,於晶片5與晶片3-4、3-8之間介置有密封部4。藉此,與第1實施方式及第2實施方式相同的是,能夠將晶片5在沿著XY平面觀察時沿著XY方向安裝於密封部4之中央附近。
於半導體裝置201中,再配線層240包含用以將端子6-1~6-8、107-1~107-4與外部電極23連接之複數層配線。再配線層240例如包含3層配線層,且包含配線層241、插塞層242、配線層243、插塞層244、配線層245、層間絕緣膜246。
複數個端子6-1~6-8之-Z側端部分別連接於配線層241中之電極圖案。複數個端子107-1~107-4之-Z側端部分別連接於配線層241中之電極圖案。
複數個外部電極23分別連接於配線層245中之電極圖案。
配線層241中之電極圖案與配線層245中之電極圖案可經由插塞層242中之插塞、配線層243中之線圖案、插塞層244中之插塞等而連接。藉此,端子6-1~6-8、107-1~107-4經由再配線層240而連接於外部電極23。
又,如圖14所示,半導體裝置201之製造方法於以下方面與第2實施方式不同。圖14係表示半導體裝置201之構成之剖視圖,但亦可用作表示半導體裝置201之製造方法之剖視圖。
例如,於半導體裝置201之製造方法中,亦可在以與第2實施方式相同之方式進行至圖12A所示之步驟之後,進行圖14所示之步驟。於圖14所示之步驟中,藉由蒸鍍法或濺鍍法等,於密封部4之正面4a及密封部123之正面123a堆積導電層241i。於該導電層241i上,形成選擇性地覆蓋複數個端子6-1~6-8之-Z側端部與複數個端子107-1~107-4之-Z側端部之抗蝕圖案RP1。將抗蝕圖案RP1作為遮罩對導電層241i進行蝕刻加工。藉此,形成包含選擇性地覆蓋複數個端子6-1~6-8之-Z側端部與複數個端子107-1~107-4之-Z側端部之電極圖案之配線層241。
繼而,堆積覆蓋配線層241之絕緣膜246i。於該絕緣膜246i上,形成在配線層241中之電極圖案之位置具有開口之抗蝕圖案RP2。將抗蝕圖案
RP2作為遮罩對絕緣膜246i進行蝕刻加工。形成選擇性地使配線層241中之電極圖案露出之孔。於孔中埋入鎢等導電物質。藉此,形成與配線層241中之電極圖案連接之插塞層242之插塞。
以相同之方式形成配線層243、插塞層244、配線層245。
然後,於再配線層240之-Z側之面安裝複數個外部電極23。外部電極23與配線層245中之電極圖案耦合。然後,藉由切削進行單片化,獲得半導體裝置201。
如上所述,於第3實施方式中,在半導體裝置201中,於將積層之複數個晶片3-1~3-8密封之密封部4之正面4a之沿著XY平面觀察時的中央附近設置凹部4a1。於凹部4a1內收容晶片5。藉此,容易將晶片5相對於複數個晶片3-1~3-8以大致等距離配線,因此,能夠提供一種具有適於將複數個晶片3-1~3-8及晶片5分別恰當地配置之構造之半導體裝置201。
(a)於第1實施方式及第2實施方式中,亦可設置密封部4來代替密封部22及密封部122。例如,於圖5B中,不設置密封部22,而利用密封部4直接進行密封。於第2實施方式中,同樣地,可刪除圖13B中設置密封部122之步驟。藉此,能夠降低製造成本。此時,於密封部4與基板10之間設置密封部21。
(b)於第1實施方式中,晶片5以面朝下狀態藉由倒裝晶片接合將晶片5之端子連接於設置在基板10之端子。此時,晶片5之電路面朝向基板10側而形成。亦可取而代之,將晶片5之端子藉由打線接合而連接於設置在基板10之端子。此時,晶片5之電路面形成為與基板10為相反方向側之面。藉由利用打線接合進行連接,能夠以低成本形成。
對本發明之若干實施方式進行了說明,但該等實施方式係作為示例提出,並不意圖限定發明之範圍。該等新穎之實施方式能夠以其他各種形態加以實施,且可於不脫離發明之主旨之範圍內進行各種省略、替換、變更。該等實施方式及其變化包含於發明之範圍或主旨中,並且包含於申請專利範圍所記載之發明及其均等之範圍內。
本申請案享有2021年9月14日提出申請之日本專利申請號2021-149156之優先權之權益,上述日本專利申請案之全部內容被引用至本申請案中。
1:半導體裝置
2:支持體
3a:正面
3-1~3-8:複數個晶片
4:密封部
4a:正面
4a1:凹部
4a11:底面
4a12:側面
3b:背面
5:晶片
5a:正面
5b:背面
6-1:端子
6-4:端子
6-5:端子
6-8:端子
7-1:端子
7-4:端子
8:電極
9:焊球凸塊
10:基板
10a:正面
10b:背面
11:電極圖案
12:通孔電極
13:導電層
14:通孔電極
15:預浸體層
16:核心層
21:密封部
22:密封部
23:外部電極
Claims (20)
- 一種半導體裝置,其具備: 支持體; 複數個第1晶片,其等積層於上述支持體上; 第1密封部,其將上述複數個第1晶片密封,於與上述支持體相反側之表面具有凹部,該凹部包含與上述複數個第1晶片分離之底面; 第2晶片,其配置於上述凹部,功能與上述第1晶片不同; 複數個第1端子,其等對應於上述複數個第1晶片,各自從上述第1晶片之與上述支持體為相反側之面朝向積層方向延伸並貫通上述第1密封部;及 第2端子,其配置於上述第2晶片之與上述支持體為相反側之面。
- 如請求項1之半導體裝置,其中 上述第1晶片為記憶體晶片, 上述第2晶片為控制器晶片, 上述第1密封部於俯視下在上述表面之中央附近具有上述凹部。
- 如請求項1之半導體裝置,其中 上述凹部於俯視下在內側包含上述第2晶片。
- 如請求項3之半導體裝置,其中 上述第2晶片於俯視下具有大致矩形形狀, 上述凹部於俯視下具有大致矩形形狀。
- 如請求項3之半導體裝置,其中 上述第2晶片於俯視下具有大致矩形形狀, 上述凹部於俯視下具有大致I字狀。
- 如請求項3之半導體裝置,其中 上述第2晶片於俯視下具有大致矩形形狀, 上述凹部於俯視下具有大致十字狀。
- 如請求項1之半導體裝置,其中 上述凹部之底面與上述第2晶片之背面分離。
- 如請求項1之半導體裝置,其中 上述凹部之底面與上述第2晶片之背面接觸。
- 如請求項1之半導體裝置,其進而具備第2密封部, 該第2密封部至少填滿上述凹部並將上述第2晶片密封。
- 如請求項9之半導體裝置,其進而具備基板, 該基板配置於上述積層方向上隔著上述第2密封部與上述第1密封部相反側。
- 如請求項10之半導體裝置,其中 上述第2密封部填滿上述凹部並且覆蓋上述第1密封部, 上述基板覆蓋上述第2密封部。
- 如請求項10之半導體裝置,其進而具備第3密封部, 該第3密封部配置於上述第2密封部與上述基板之間,且覆蓋上述第1密封部。
- 如請求項9之半導體裝置,其進而具備配線層, 該配線層覆蓋上述第1密封部之表面及上述第2密封部之表面,將上述複數個第1端子及上述第2端子電性連接。
- 如請求項1之半導體裝置,其進而具備緩衝構件, 該緩衝構件介置於上述凹部之底面與上述第2晶片之間。
- 如請求項1之半導體裝置,其中 上述第1端子之前端距離上述支持體之高度,與上述第1密封部之表面距離上述支持體之高度相等。
- 如請求項9之半導體裝置,其中 上述第2端子從上述第2晶片沿著上述積層方向延伸, 上述第2端子之前端距離上述支持體之高度,與上述第2密封部之表面距離上述支持體之高度相等。
- 如請求項1之半導體裝置,其中 上述第2端子從上述第2晶片沿著上述積層方向延伸, 上述第2端子之前端距離上述支持體之高度,與上述第1端子之前端距離上述支持體之高度相等。
- 如請求項17之半導體裝置,其中 上述第1端子之前端距離上述支持體之高度,與上述第1密封部之表面距離上述支持體之高度相等, 上述第2端子之前端距離上述支持體之高度,與上述第2密封部之表面距離上述支持體之高度相等。
- 如請求項17之半導體裝置,其進而具備: 第2密封部,其至少填滿上述凹部,並將上述第2晶片密封;及 基板,其配置於積層方向上隔著上述第2密封部與上述第1密封部相反側; 上述第1端子及上述第2端子分別連接於上述基板。
- 如請求項17之半導體裝置,其進而具備: 第2密封部,其至少填滿上述凹部,並將上述第2晶片密封;及 配線層,其覆蓋上述第1密封部之表面及上述第2密封部之表面,將上述複數個第1端子及上述第2端子電性連接; 上述第1端子及上述第2端子分別連接於上述配線層。
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US20150069632A1 (en) * | 2013-09-06 | 2015-03-12 | Kabushiki Kaisha Toshiba | Semiconductor package |
TW201919176A (zh) * | 2017-10-31 | 2019-05-16 | 南韓商三星電機股份有限公司 | 扇出型半導體封裝 |
US20200051957A1 (en) * | 2018-08-07 | 2020-02-13 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing same |
TW202008529A (zh) * | 2018-08-03 | 2020-02-16 | 日商東芝記憶體股份有限公司 | 半導體裝置及其製造方法 |
TW202011546A (zh) * | 2018-08-31 | 2020-03-16 | 日商東芝記憶體股份有限公司 | 半導體裝置 |
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US20150069632A1 (en) * | 2013-09-06 | 2015-03-12 | Kabushiki Kaisha Toshiba | Semiconductor package |
TW201919176A (zh) * | 2017-10-31 | 2019-05-16 | 南韓商三星電機股份有限公司 | 扇出型半導體封裝 |
TW202008529A (zh) * | 2018-08-03 | 2020-02-16 | 日商東芝記憶體股份有限公司 | 半導體裝置及其製造方法 |
US20200051957A1 (en) * | 2018-08-07 | 2020-02-13 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing same |
TW202011546A (zh) * | 2018-08-31 | 2020-03-16 | 日商東芝記憶體股份有限公司 | 半導體裝置 |
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