CN115810588A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN115810588A CN115810588A CN202210177120.3A CN202210177120A CN115810588A CN 115810588 A CN115810588 A CN 115810588A CN 202210177120 A CN202210177120 A CN 202210177120A CN 115810588 A CN115810588 A CN 115810588A
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- chip
- semiconductor device
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- sealing part
- terminal
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Abstract
根据实施方式,提供一种具有支撑体、多个第1芯片、第1密封部、第2芯片、多个第1端子及第2端子的半导体装置。多个第1芯片积层在支撑体上。第1密封部将多个第1芯片密封。第1密封部在与支撑体为相反侧的表面具有凹部。凹部包含与多个第1芯片分离的底面。第2芯片配置在凹部。多个第1端子对应于多个第1芯片。多个第1端子分别从第1芯片的与支撑体为相反侧的面沿着积层方向延伸并贯通第1密封部。第2端子配置在第2芯片的与支撑体为相反侧的面上。
Description
[相关申请的引用]
本申请享有2021年9月14日提出申请的日本专利申请号2021-149156的优先权的权益,所述日本专利申请的全部内容被引用到本申请中。
技术领域
本实施方式涉及一种半导体装置。
背景技术
半导体装置中,有时会将多个芯片积层,使端子从各芯片沿着积层方向延伸而构成。半导体装置中,期望除了多个芯片以外,还能适当地配置其它芯片。
发明内容
一实施方式提供一种能够适当地配置多个第1芯片及第2芯片的半导体装置。
实施方式的半导体装置提供一种具有支撑体、多个第1芯片、第1密封部、第2芯片、多个第1端子及第2端子的半导体装置。多个第1芯片积层在支撑体上。第1密封部将多个第1芯片密封。第1密封部在与支撑体为相反侧的表面具有凹部。凹部包含与多个第1芯片分离的底面。第2芯片配置在凹部中。多个第1端子对应于多个第1芯片。多个第1端子分别从第1芯片的与支撑体为相反侧的面沿着积层方向延伸并贯通第1密封部。第2端子配置在第2芯片的与支撑体为相反侧的面上。
根据所述构成,可提供一种能够适当地配置多个第1芯片及第2芯片的半导体装置。
附图说明
图1是表示第1实施方式的半导体装置的构成的剖视图。
图2A~图2D是表示第1实施方式的半导体装置的制造方法的剖视图。
图3是表示第1实施方式的半导体装置的制造方法的俯视图。
图4A~图4C是表示第1实施方式的半导体装置的制造方法的剖视图。
图5A~图5C是表示第1实施方式的半导体装置的制造方法的剖视图。
图6A~图6C是表示第1实施方式的第1变化例的半导体装置的制造方法的剖视图。
图7是表示第1实施方式的第2变化例的半导体装置的制造方法的俯视图。
图8是表示第1实施方式的第3变化例的半导体装置的制造方法的俯视图。
图9是表示第1实施方式的第4变化例的半导体装置的制造方法的俯视图。
图10是表示第2实施方式的半导体装置的构成的剖视图。
图11A及图11B是表示第2实施方式的半导体装置的制造方法的剖视图。
图12A~图12C是表示第2实施方式的半导体装置的制造方法的剖视图。
图13A~图13C是表示第2实施方式的半导体装置的制造方法的剖视图。
图14是表示第3实施方式的半导体装置的构成的剖视图。
具体实施方式
以下,参照附图,对实施方式的半导体装置详细地进行说明。此外,本发明并不受这些实施方式限定。
(第1实施方式)
第1实施方式的半导体装置是将多个芯片积层,使端子(纵交线(vertical wire))从各芯片沿着积层方向延伸而构成。半导体装置1例如按图1所示的方式构成。
图1是表示半导体装置1的构成的剖视图。以下,将与支撑体2的主面垂直的方向设为Z方向,将在与Z方向垂直的面内相互正交的2个方向设为X方向及Y方向。
半导体装置1具有支撑体2、多个芯片3-1~3-8、密封部4、芯片5、多个端子6-1~6-8、多个端子7-1~7-4、密封部22、外部电极23、衬底10及密封部21。
支撑体2是在XY方向上延伸的板状部件。支撑体2在沿着XY平面观察时具有矩形。支撑体2具有适于支撑多个芯片3-1~3-8的刚性。支撑体2可由适于具有规定刚性的材料(例如,玻璃、玻璃布、硅)等形成。
多个芯片3-1~3-8配置在支撑体2的-Z侧,分成相等的两部分呈阶梯状积层。多个芯片3-1~3-4在多个芯片3-5~3-8的-Y侧呈阶梯状积层。多个芯片3-5~3-8在多个芯片3-5~3-8的+Y侧呈阶梯状积层。各芯片3-1~3-8的功能与芯片5不同,例如是能够存储数据的存储器芯片。
密封部4将多个芯片3-1~3-8密封。密封部4可由模具树脂等具有热塑性的第1绝缘物形成。密封部4具有正面4a及背面4b。背面4b与支撑体2相接。正面4a是与支撑体2为相反侧的主面。密封部4在正面4a具有凹部4a1。凹部4a1是密封部4中从正面4a向+Z侧凹陷的空间。凹部4a1只要能收容芯片5,则可采用任意形状。凹部4a1配置在能收容芯片5的位置,也可以配置在例如沿着XY平面观察时正面4a的中央附近(参照图3)。
凹部4a1的深度比芯片3-4、3-8相对于正面4a的Z方向深度小。背面4b的Z位置比芯片3-4、3-8的表面(-Z侧的面)的Z位置更靠-Z侧。
凹部4a1具有底面4a11及侧面4a12。底面4a11沿着XY方向延伸。底面4a11与多个芯片3-1~3-8在Z方向上分离。底面4a11与多个芯片3-1~3-4中最靠-Z侧的芯片3-4在Z方向上分离,与多个芯片3-5~3-8中最靠-Z侧的芯片3-8在Z方向上分离。底面4a11可以与芯片3-4的正面3a大致平行,也可以与芯片3-8的正面3a大致平行。凹部4a1可以是例如大致长方体形状的孔,也可以在沿着XY平面观察时具有大致矩形。凹部4a1的开放端的面积大于底面4a11的面积。凹部4a1的开放端的X方向宽度大于底面4a11的X方向宽度。凹部4a1的开放端的Y方向宽度大于底面4a11的Y方向宽度。
凹部4a1的开放端的面积大于芯片5的面积。凹部4a1的开放端的X方向宽度大于芯片5的X方向宽度。凹部4a1的开放端的Y方向宽度大于芯片5的Y方向宽度。
底面4a11的面积大于芯片5的面积。底面4a11的X方向宽度大于芯片5的X方向宽度。底面4a11的Y方向宽度大于芯片5的Y方向宽度。
多个端子6-1~6-8对应于多个芯片3-1~3-8。各端子6-1~6-8从对应的芯片3中与支撑体2为相反侧的面(-Z侧的面)3a沿着-Z方向延伸,贯通密封部4而到达正面4a。各端子6-1~6-8也可以多个连接于对应的芯片3。各端子6-1~6-8也可以沿着-Z方向直线延伸。各端子6-1~6-8也可以是直立型端子,具有能够维持直线形状的刚性。
例如,各端子6-1~6-8的直径可以比用于打线接合型安装的金属线的直径粗。各端子6-1~6-8是垂直延伸的金属线,也被称为纵交线。通过将各端子6-1~6-8以直立型构成,可容易实现各端子6-1~6-8间的配置间距的窄间距化。
在将多个芯片3-1~3-8分成两半部分呈阶梯状积层的情况下,多个端子6-1~6-8也可以分成两半部分使长度呈阶梯状不同。多个端子6-1~6-4的+Z侧端部的Z位置在多个端子6-5~6-8的-Y侧呈阶梯状变低。多个端子6-5~6-8的+Z侧端部的Z位置在多个端子6-5~6-8的+Y侧呈阶梯状变低。多个端子6-1~6-8的-Z侧端部的Z位置也可以相互均等。各端子6-1~6-8的-Z侧端部经由电极8及焊球凸块(ball bump)9而连接于衬底10的电极图案11。各端子6-1~6-8可由以金属(例如金)为主成分的导电物形成。
芯片5配置在支撑体2的-Z侧,且配置在多个芯片3-1~3-8的-Z侧。芯片5的功能与芯片3不同,例如是能够控制多个芯片3-1~3-8的控制器芯片。芯片5电连接于多个芯片3-1~3-8。芯片5理想的是配置在半导体装置1中沿着XY平面观察时的中央附近,以此使得朝向各芯片3-1~3-8的配线长度一样长。因此,芯片5配置在凹部4a1内。
芯片5的背面(+Z侧的面)5b也可以与凹部4a1的底面4a11在-Z方向上稍微分离。这样一来,芯片5与多个芯片3-1~3-8中最靠-Z侧的芯片3-4、3-8在-Z方向上分离。
多个端子7-1~7-4配置在芯片5的正面(-Z侧的面)5a。各端子7-1~7-4也可以沿着-Z方向呈柱状延伸。各端子7-1~7-4的XY方向上的最大宽度比各端子6-1~6-8的XY方向上的最大宽度大。各端子7-1~7-4可由多个层的积层而形成。多个层可分别由焊料合金层、铜合金层等以合金为主成分的导电物形成。多个层可以包含组成互不相同的层,也可以是不同组成的层与相同组成的层混合存在。
多个端子7-1~7-4的+Z侧端部与芯片5的正面5a耦合。多个端子7-1~7-4的-Z侧端部的Z位置也可以相互均等。多个端子7-1~7-4的-Z侧端部距离支撑体2的Z方向高度可与多个端子6-1~6-8的-Z侧端部距离支撑体2的Z方向高度均等。各端子7-1~7-4的-Z侧端部经由电极8及焊球凸块9而连接于衬底10的电极图案11。各端子7-1~7-4是柱状凸块,也被称为柱形凸块。通过将各端子7-1~7-4以柱状构成,可容易实现各端子7-1~7-4间的配置间距的窄间距化。
密封部22填埋凹部4a1,且将芯片5密封。密封部22填埋密封部4与衬底10的间隙,并将电极8、焊球凸块9及电极图案11密封。密封部22覆盖密封部4的-Z侧的面,并且覆盖衬底10的正面10a。密封部22可由模具树脂等具有热塑性的第2绝缘物形成。第2绝缘物的组成与第1绝缘物不同。
密封部21从外侧覆盖支撑体2、密封部4、密封部22并进行密封。密封部21可到达衬底10的正面10a。密封部21可由模具树脂等具有热塑性的第3绝缘物形成。第3绝缘物的组成与第1绝缘物不同,与第2绝缘物也不同。
密封部4、密封部21、密封部22也可以是在绝缘性树脂中包含无机物填料所得者。这时,密封部4、密封部21的填料的含量可以比密封部22的填料的含量多。
密封部4、密封部21的热膨胀率可分别小于密封部22的热膨胀率。
密封部4、密封部21的杨氏模数可分别大于密封部22的杨氏模数。
衬底10具有多个电极图案11、多个通孔电极12、导电层13、多个通孔电极14、预浸体层15及核心层16。多个电极图案11分别露出在衬底10的正面10a,多个通孔电极14分别露出在衬底10的背面10b。各电极图案11、各通孔电极12、导电层13、各通孔电极14可分别由以导电物(例如铜)为主成分的材料形成。预浸体层15、核心层16可分别由以绝缘物(例如塑料等有机系物质)为主成分的材料形成。
此外,图1中,为了简化表示,示出了导电层13连接于多个电极图案11、多个通孔电极12、多个通孔电极14的形态,但实际上可形成规定的配线,选择性地连接规定的电极图案11、规定的通孔电极12、规定的通孔电极14。
多个外部电极23配置在衬底10的背面10b,且分别与通孔电极14接合。多个外部电极23的X方向的配置间距大于多个端子6-1~6-8的X方向的配置间距。多个外部电极23的X方向的配置间距大于多个端子7-1~7-4的X方向的配置间距。同样,多个外部电极23的Y方向的配置间距大于多个端子6-1~6-8的Y方向的配置间距。多个外部电极23的Y方向的配置间距大于多个端子7-1~7-4的Y方向的配置间距。由此,能够实现各端子6-1~6-8间的配置间距、各端子7-1~7-4间的配置间距的窄间距化,同时容易将半导体装置1连接于宽间距的外部端子(例如母板上的端子)。
接下来,使用图1~图5C对半导体装置1的制造方法进行说明。图1是表示半导体装置1的构成的剖视图,但也用作表示半导体装置1的制造方法的剖视图。图2A~图2D、图4A~图4C、图5A~图5C是表示半导体装置1的制造方法的剖视图。图3是表示半导体装置1的制造方法的俯视图。
图2A所示的步骤中,准备支撑体2。支撑体2是沿着XY方向延伸的板状部件。支撑体2可由适于具有规定刚性的材料(例如,玻璃、玻璃布、硅)等形成。多个芯片3-1~3-8呈阶梯状积层在支撑体2的-Z侧的面2a。
例如,在支撑体2的-Z侧的面2a中的-Y侧区域,可经由粘接剂或粘接膜等粘接芯片3-1。芯片3-2可以XY平面位置例如向+Y侧偏移的状态粘接在芯片3-1的-Z侧。芯片3-3可以XY平面位置例如向+Y侧偏移的状态经由粘接剂或粘接膜等粘接在芯片3-2的-Z侧。芯片3-4可以XY平面位置例如向+Y侧偏移的状态粘接在芯片3-3的-Z侧。
由此,在支撑体2的面2a的-Y侧区域,多个芯片3-1~3-4以Y位置向+Y侧依次偏移的方式呈阶梯状积层。各芯片3-1~3-4以正面3a为-Z侧的状态面朝上安装。多个芯片3-1~3-4的正面3a距离支撑体2的Z方向高度依次变高。同样,在支撑体2的面2a的+Y侧区域,多个芯片3-5~3-8以Y位置向-Y侧依次偏移的方式呈阶梯状积层。各芯片3-5~3-8以正面3a为-Z侧的状态面朝上安装。多个芯片3-5~3-8的正面3a距离支撑体2的Z方向高度依次变高。
图2B所示的步骤中,多个端子6-1~6-8与多个芯片3-1~3-8耦合。多个端子6-1~6-8对应于多个芯片3-1~3-8。多个端子6-1~6-8的长度对应于多个芯片3-1~3-8距离支撑体2的Z方向高度(例如,用来吸收Z方向高度的差异),可互不相同。各端子6-1~6-8在竖立在Z方向的姿势下,其+Z侧的端部可与所对应的芯片3的正面3a上的电极垫耦合。此外,也可以从各芯片3延伸出多个端子6(参照图3)。
例如,对应于多个芯片3-1~3-4的正面3a距离支撑体2的Z方向高度依次变高,多个端子6-1~6-4的长度会依次变短。由此,多个端子6-1~6-4在已与多个芯片3-1~3-4耦合的状态下,其-Z侧端部的Z位置相互靠近。同样,对应于多个芯片3-5~3-8的正面3a距离支撑体2的Z方向高度依次变高,多个端子6-5~6-8的长度会依次变短。由此,多个端子6-5~6-8在已与多个芯片3-5~3-8耦合的状态下,其-Z侧端部的Z位置相互靠近。
图2C所示的步骤中,在支撑体2的-Z侧形成密封部4i。也就是说,利用第1绝缘物覆盖多个芯片3-1~3-8的正面及侧面,并且利用第1绝缘物覆盖多个端子6-1~6-8的侧面及端面,以此形成密封部4i。密封部4i可由模具树脂等具有热塑性的第1绝缘物形成。密封部4i距离支撑体2的Z方向高度比最靠-Z侧的芯片3-4、3-8的Z方向高度高,且比各端子6-1~6-8的Z方向高度高。
图2D所示的步骤中,在密封部4i的-Z侧的正面4ai形成凹部4a1i。凹部4a1i的形成深度与规定深度和后续步骤的研磨厚度的合计相对应。规定深度形成为小于芯片3-4、3-8相对于正面4ai的Z方向深度。规定深度也可以是后续步骤中将芯片5安装在衬底10的状态下的芯片5距离衬底10的Z方向高度以上。凹部4a1i也可以形成为在分别沿着XZ截面观察及沿着YZ截面观察时呈锥形,即,以越靠近底面4a11开口宽度越小的方式使侧面4a12倾斜。例如,凹部4a1i可由模具成形而形成。准备模具,所述模具包含有在XY方向中央附近具有基座部的平坦部,使第1绝缘物加热熔融后流入模具中,冷却后进行脱模,由此可形成在表面的XY方向中央附近具有凹部4a1i的密封部4i。这时,通过使基座部为锥形,可容易进行脱模,能够提高形成密封部4i的处理的处理量。或者,凹部4a1i也可以通过激光加工来形成。在形成具有平坦表面的密封部4i之后,一边通过NC(Numerical Control,数字控制)控制等在其表面将照射位置控制为矩形,一边对所述表面照射激光,由此可形成在表面的中央附近具有凹部4a1i的密封部4i。这时,从激光加工的特性来看,凹部4a1i可形成为锥形。
如图3所示,凹部4a1i在沿着XY平面观察时形成在正面4ai的中央附近。图3中,例示了凹部4a1i形成为大致长方体形状的孔(沿着XY平面观察时为大致矩形)的构成。凹部4a1i以其X方向宽度大于芯片5的X方向宽度的方式形成。凹部4a1i以其Y方向宽度大于芯片5的Y方向宽度的方式形成。通过将凹部4a1i以这样的方式构成,能够在后续步骤中将芯片5收容在凹部4a1i内。
图4A所示的步骤中,对密封部4i的正面4ai进行研磨。例如,将研磨装置的研磨机抵接于密封部4i的正面4ai,研磨机以与接触面垂直的轴为中心旋转,使研磨机连续旋转,直到各端子6-1~6-8的-Z侧端部露出在密封部4的正面4a为止。密封部4的Z方向厚度相比密封部4i薄了相当于研磨厚度的量。凹部4a1的深度相比凹部4a1i减小了相当于研磨厚度的量。
图4B所示的步骤中,在密封部4的正面4a形成多个电极8。多个电极8对应于多个端子6-1~6-8。各电极8连接于所对应的端子6的-Z侧的端部。各电极8由金属(例如铜)等导电物形成。由此,可获得多个芯片3-1~3-8呈阶梯状积层且面朝上安装并被密封的上部构造体20。
图4C所示的步骤中,准备衬底10。露出在衬底10的正面10a的多个电极图案11分别与焊球凸块9耦合。沿着XY平面观察时的衬底10的中央附近的多个焊球凸块9分别与电极8耦合。
另一方面,准备芯片5。在芯片5的正面5a配置多个电极垫。准备与多个电极垫对应的多个端子7-1~7-4。多个端子7-1~7-4各自的一端与芯片5的正面5a上的对应的电极垫耦合。另外,多个端子7-1~7-4与沿着XY平面观察时的衬底10的中央附近的多个电极8相对应。多个端子7-1~7-4各自的另一端与电极8耦合。也就是说,芯片5以正面5a为-Z侧的状态面朝下安装于衬底10。由此,获得芯片5面朝下安装于衬底10的下部构造体30。
以正面4a与正面10a相对的方式使上部构造体20与下部构造体30对向配置。从Z方向透视时,以上部构造体20中的电极8与下部构造体30中的焊球凸块9重叠的方式,进行上部构造体20与下部构造体30的相对位置对准。这时,从Z方向透视时,芯片5包含在凹部4a1的内侧(参照图3)。
图5A所示的步骤中,上部构造体20及下部构造体30在Z方向上相对靠近。上部构造体20中的电极8与下部构造体30中的焊球凸块9相互耦合。芯片5被收容在密封部4的凹部4a1内。
图5B所示的步骤中,上部构造体20与下部构造体30的间隙被密封部22密封。密封部22以填满凹部4a1并且填满密封部4及衬底10的间隙的方式填充。密封部22可由模具树脂等具有热塑性的第2绝缘物形成。由此,芯片5被密封部22密封,并且电极8、焊球凸块9被密封部22密封。
图5C所示的步骤中,上部构造体20的外侧被密封部21密封。密封部21形成为从外侧覆盖支撑体2、密封部4、密封部22。密封部21也可以形成为到达衬底10的正面10a。密封部21可由模具树脂等具有热塑性的第3绝缘物形成。第3绝缘物的组成与第1绝缘物不同,与第2绝缘物也不同。
图1所示的步骤中,在衬底10的背面10b安装多个外部电极23。可对露出在衬底10的背面10b的通孔电极14接合外部电极23。然后,通过切削进行单片化,从而获得半导体装置1。
如上所述,在第1实施方式中,在半导体装置1中,在将积层的多个芯片3-1~3-8密封的密封部4的正面4a的沿着XY平面观察时的中央附近设置凹部4a1。在凹部4a1内收容芯片5。由此,容易将芯片5相对于多个芯片3-1~3-8以大致等距离配线,从而能够提供一种具有适于将多个芯片3-1~3-8及芯片5分别适当配置的构造的半导体装置1。
此处,当制造半导体装置1时,考虑将多个芯片3-1~3-8呈阶梯状积层在支撑体2上,在最上方(最靠-Z侧)的芯片3-4、3-8上粘接芯片5的情况。这种情况下,可能会因粘接时的应力等而导致芯片3-4、3-8弯曲,使得芯片5从恰当的平面方向倾斜。
对此,在第1实施方式中,在半导体装置1中,收容芯片5的凹部4a1的底面4a11与被密封部4密封的多个芯片3-1~3-8中的最上方(最靠-Z侧)的芯片3-4、3-8的正面3a在Z方向上分离。由此,能够提供一种具有适于将芯片5在不会从恰当的平面方向倾斜的情况下安装而制造的构造的半导体装置1。
此处,当制造半导体装置1时,考虑利用密封部4一并密封连接于芯片3-1~3-8的直立型端子6-1~6-8与安装于芯片5的柱状端子7-1~7-4。这种情况下,在端子6-1~6-8与端子7-1~7-4之间,前端的高度存在差异。为了吸收这种差异,将端子6-1~6-8及端子7-1~7-4形成得较高,然后通过研磨使高度一致。也就是说,因增高了具有比端子6-1~6-8复杂的构造(多个膜的积层构造)的端子7-1~7-4,有可能会导致半导体装置1的成本增加。
对此,在第1实施方式中,在半导体装置1中,直立型端子6-1~6-8与作为连接目标的芯片3-1~3-8均被密封部4密封,其-Z侧端部露出在密封部4的正面4a。柱状端子7-1~7-4安装在密封部4的凹部4a1内所收容的芯片5上。由此,能够抑制密封部4的密封对端子6-1~6-8及端子7-1~7-4间的不均的影响,从而能够将端子7-1~7-4抑制得较低。也就是说,能够提供一种适于降低制造成本的半导体装置1。
此外,如图6C所示,也可以在芯片5与凹部4a1的底面4a11之间介置缓冲部件40。图6A~图6C分别是表示第1实施方式的第1变化例的半导体装置的制造方法的剖视图。
例如,在半导体装置1的制造方法中,也可以在进行图2A~图2D所示的步骤之后,进行图6A所示的步骤。在图6A所示的步骤中,在凹部4a1的底面4a11配置缓冲部件40。缓冲部件40是在XY方向上延伸的板状部件。缓冲部件40也可以由树脂系粘着剂等具有柔软性、弹性的绝缘材料形成。缓冲部件40以覆盖底面4a11的主要部分的方式配置。
如图3中两点链线所示,缓冲部件40以沿着XY平面观察时包含在底面4a11的内侧并且内侧包含芯片5的方式配置。缓冲部件40的XY面积小于底面4a11的XY面积,大于芯片5的XY面积。缓冲部件40的X方向宽度小于底面4a11的X方向宽度,大于芯片5的X方向宽度。缓冲部件40的Y方向宽度小于底面4a11的Y方向宽度,大于芯片5的Y方向宽度。
在进行图4A~图4C所示的步骤之后,代替图5A所示的步骤,而进行图6B所示的步骤。在图6B所示的步骤中,上部构造体20及下部构造体30在Z方向上相对靠近。与第1实施方式相同的是,上部构造体20中的电极8与下部构造体30中的焊球凸块9相互耦合。芯片5的背面与缓冲部件40接触,并且芯片5被收容在密封部4的凹部4a1内。这时,芯片5稍微压抵于缓冲部件40,但由于缓冲部件40具有弹性,所以能抑制对芯片5的应力。
代替图5B所示的步骤而进行图6C所示的步骤。在图6C所示的步骤中,当利用密封部22将上部构造体20与下部构造体30的间隙密封时,覆盖缓冲部件40及芯片5的露出面并且填满凹部4a1。这时,凹部4a1的底面4a11的主要部分被缓冲部件40覆盖,因此,能够抑制密封部22中产生空隙,提高安装品质。
然后,进行图5C所示的步骤、图1所示的步骤,以与第1实施方式相同的方式来制造半导体装置1。
这样一来,在第1实施方式的第1变化例的半导体装置中,在芯片5与凹部4a1的底面4a11之间介置缓冲部件40。由此,能够提供具有适于提高安装品质的构造的半导体装置1。
另外,凹部4a1i只要能够收容芯片5,则可以是任意形状,例如也可以形成为图7所示的横I字状的沟槽(沿着XY平面观察时为大致横I字状)。图7是表示第1实施方式的第2变化例的半导体装置1的制造方法的俯视图。图7中,例示了凹部4a1i形成为横I字状的沟槽的构成。这种情况下,与第1实施方式不同的是,凹部4a1的开放端的Y方向宽度与底面4a11的Y方向宽度均等。此外,与第1实施方式相同的是,凹部4a1i的开放端的面积大于底面4a11的面积,凹部4a1i的开放端的X方向宽度大于底面4a11的X方向宽度。
端子6-1~6-8露出在凹部4a1i的底面。端子露出面的高度较低。因此,也可以另外形成电极来补足端子的高度。或者,也可以将电极8或焊球凸块9形成得较高。
凹部4a1i也可以形成为在沿着XZ截面观察时呈锥形,即,以越接近底面4a11开口宽度越小的方式使侧面4a12倾斜。例如,凹部4a1i也可以利用切割加工来形成。在形成具有平坦表面的密封部4i之后,一边通过NC控制等在其表面上控制接触位置一边使切割刀在X方向上接触所述表面并旋转,由此,可形成在表面的X方向中央附近具有槽状凹部4a1i的密封部4i。这时,从切割加工的特性来看,凹部4a1i可以形成为在沿着XZ截面观察时呈锥形。或者,凹部4a1i也可以通过模具成形而形成。准备模具,所述模具包含有在X方向中央附近具有横I字状基座部的平坦部,使第1绝缘物加热熔融后流入模具,冷却后进行脱模,由此,可形成在表面的X方向中央附近具有凹部4a1i的密封部4i。这时,通过使基座部为锥形,可容易进行脱模,从而可提高形成密封部4i的处理的处理量。或者,凹部4a1i也可以利用激光加工而形成。在形成具有平坦表面的密封部4i之后,一边通过NC控制等在其表面将照射位置控制为横条纹状,一边对所述表面照射激光,由此,可形成在表面的X方向中央附近具有凹部4a1i的密封部4i。这时,从激光加工的特性来看,凹部4a1i可形成为锥形。
另外,凹部4a1i例如也可以形成为图8所示的纵I字状的沟槽(沿着XY平面观察时为大致纵I字状)。图8是表示第1实施方式的第3变化例的半导体装置1的制造方法的俯视图。图8中,例示了凹部4a1i形成为纵I字状的沟槽的构成。这种情况下,与第1实施方式不同的是,凹部4a1的开放端的X方向宽度与底面4a11的X方向宽度均等。此外,与第1实施方式相同的是,凹部4a1i的开放端的面积大于底面4a11的面积,凹部4a1i的开放端的Y方向宽度大于底面4a11的Y方向宽度。
凹部4a1i也可以形成为在沿着YZ截面观察时呈锥形,即,以越接近底面4a11开口宽度越小的方式使侧面4a12倾斜。例如,凹部4a1i也可以利用切割加工而形成。在形成具有平坦表面的密封部4i之后,一边通过NC控制等在其表面控制接触位置,一边使切割刀在Y方向上接触所述表面并旋转,由此,可形成在表面的Y方向中央附近具有槽状凹部4a1i的密封部4i。这时,从切割加工的特性来看,凹部4a1i可以形成为在沿着YZ截面观察时呈锥形。或者,凹部4a1i也可以通过模具成形而形成。准备模具,所述模具包含有在Y方向中央附近具有纵I字状基座部的平坦部,使第1绝缘物加热熔融后流入模具,冷却后进行脱模,由此,可形成在表面的Y方向中央附近具有凹部4a1i的密封部4i。这时,通过使基座部为锥形,可容易进行脱模,从而可提高形成密封部4i的处理的处理量。或者,凹部4a1i也可以利用激光加工而形成。在形成具有平坦表面的密封部4i之后,一边通过NC控制等在其表面将照射位置控制为纵条纹状,一边照射激光,由此,可形成在表面的Y方向中央附近具有凹部4a1i的密封部4i。这时,从激光加工的特性来看,凹部4a1i可形成为锥形。
另外,凹部4a1i例如也可以形成为图9所示的十字状的沟槽(沿着XY平面观察时为大致十字状)。图9是表示第1实施方式的第4变化例的半导体装置1的制造方法的俯视图。图9中,例示了凹部4a1i形成为十字状沟槽的构成。这种情况下,与第1实施方式不同的是,凹部4a1的开放端的X方向宽度在Y方向中央附近与底面4a11的X方向宽度均等,在Y方向两端附近大于底面4a11的X方向宽度,凹部4a1的开放端的Y方向宽度在X方向中央附近与底面4a11的Y方向宽度均等,在X方向两端附近大于底面4a11的Y方向宽度。此外,与第1实施方式相同的是,凹部4a1i的开放端的面积大于底面4a11的面积。
端子6-1~6-8露出在凹部4a1i的底面。端子露出面的高度较低。因此,也可以另外形成电极以补足端子的高度。或者,也可以将电极8或焊球凸块9形成得较高。
凹部4a1i的X方向两端附近的部分也可以形成为在沿着YZ截面观察时呈锥形,即,以越接近底面4a11开口宽度越小的方式使侧面4a12倾斜。凹部4a1i的Y方向两端附近的部分也可以形成为在沿着XZ截面观察时呈锥形,即,以越接近底面4a11开口宽度越小的方式使侧面4a12倾斜。例如,凹部4a1i也可以利用切割加工来形成。在形成具有平坦表面的密封部4i之后,一边通过NC控制等在其表面控制接触位置,一边使切割刀在X方向上接触所述表面并旋转,并且使切割刀在Y方向上接触所述表面并旋转,由此,可形成表面具有交叉槽状的凹部4a1i的密封部4i。这时,从切割加工的特性来看,凹部4a1i的X方向两端附近的部分可形成为在沿着YZ截面观察时呈锥形,且Y方向两端附近的部分形成为在沿着XZ截面观察时呈锥形。或者,凹部4a1i也可以通过模具成形而形成。准备模具,所述模具包含具有十字状基座部的平坦部,使第1绝缘物加热熔融后流入模具,冷却后进行脱模,由此,可形成表面具有十字状凹部4a1i的密封部4i。这时,通过使基座部为锥形,可容易进行脱模,从而可提高形成密封部4i的处理的处理量。或者,凹部4a1i也可以利用激光加工而形成。在形成具有平坦表面的密封部4i之后,一边通过NC控制等在其表面将照射位置控制为十字状,一边对所述表面照射激光,由此,可形成表面具有十字状凹部4a1i的密封部4i。这时,从激光加工的特性来看,凹部4a1i的X方向两端附近的部分可形成为在沿着YZ截面观察时呈锥形,Y方向两端附近的部分形成为在沿着XZ截面观察时呈锥形。
(第2实施方式)
接下来,对第2实施方式的半导体装置进行说明。以下,以与第1实施方式不同的部分为中心进行说明。
在第1实施方式中,例示了包含芯片5的背面与凹部4a1的底面4a11分离的构造的半导体装置1,但在第2实施方式中,例示包含芯片5的背面与凹部4a1的底面4a11接触的构造的半导体装置101。
具体来说,如图10所示,半导体装置101中,芯片5的背面5b与凹部4a1的底面4a11接触。图10是表示第2实施方式的半导体装置101的构成的剖视图。与第1实施方式相比,芯片5与多个芯片3-1~3-8中最上方的芯片3-4、3-8的Z方向距离变得更小,因此,能够实现半导体装置101的低背化。
此外,在芯片5与芯片3-4、3-8之间介置着密封部4。由此,与第1实施方式相同的是,能够将芯片5在沿着XY平面观察时沿着XY方向安装在密封部4的中央附近。
半导体装置101具有多个端子107-1~107-4、密封部122来代替多个端子7-1~7-4、密封部22(参照图1),还具有密封部123。多个端子107-1~107-4的-Z侧端部的Z位置与多个端子6-1~6-8的-Z侧端部的Z位置大致相同。密封部123填埋凹部4a1并且密封芯片5。密封部123的-Z侧的面123a与密封部4的-Z侧的面4a形成连续面,且Z位置大致相同。密封部123可由模具树脂等具有热塑性的第4绝缘物形成。第4绝缘物的组成与第1绝缘物不同。第4绝缘物的组成可以与第2绝缘物不同,也可以与第3绝缘物不同。
密封部122及密封部123也可以是在绝缘性树脂中包含无机物填料所得者。这时,密封部4、密封部21、密封部122的填料的含量可以多于密封部123的填料的含量。密封部4、密封部21的填料的含量也可以多于密封部122的填料的含量。
密封部4、密封部21、密封部122的热膨胀率可以小于密封部123的热膨胀率。密封部4、密封部21的热膨胀率也可以小于密封部122的热膨胀率。
密封部4、密封部21、密封部122的杨氏模数可以大于密封部123的杨氏模数。密封部4、密封部21的杨氏模数也可以大于密封部122的杨氏模数。
此外,与第1实施方式相同的是,各端子6-1~6-8的-Z侧端部经由电极8及焊球凸块9而连接于衬底10的电极图案11,各端子7-1~7-4的-Z侧端部经由电极8及焊球凸块9而连接于衬底10的电极图案11。
另外,如图11A~图13C所示,半导体装置101的制造方法在以下方面与第1实施方式不同。图11A~图11B、图12A~图12C、图13A~图13C是表示半导体装置101的制造方法的剖视图。
例如,在半导体装置101的制造方法中,也可以在进行图2A~图2D所示的步骤之后,进行图11A所示的步骤。在图11A所示的步骤中,准备芯片5及多个端子107-1~107-4。多个端子107-1~107-4各自的一端与芯片5的表面上所对应的电极垫耦合。在凹部4a1的底面4a11配置与多个端子107-1~107-4耦合的芯片5。如图3中单点链线所示,芯片5以沿着XY平面观察时包含在底面4a11的内侧的方式配置。芯片5也可以是其背面5b经由粘接剂或粘接膜等而粘接于底面4a11。
这时,在凹部4a1内配置有芯片5的状态下,各端子6-1~6-8的-Z侧端部的Z位置与各端子107-1~107-8的-Z侧端部的Z位置可以在能够通过研磨而对齐的范围内互不相同。
在图11B所示的步骤中,在凹部4ai内填充第4绝缘物质。也就是说,利用第4绝缘物覆盖芯片5的表面及侧面,并且利用第4绝缘物覆盖多个端子107-1~107-8的侧面及端面,以此形成密封部123i。由此,形成填满凹部4ai的密封部123i。第4绝缘物质的组成与第1绝缘物不同。第4绝缘物的组成可以与第2绝缘物不同,也可以与第3绝缘物不同。
这时,密封部4的正面4ai的Z位置与密封部123的正面123ai的Z位置也可以在能够通过研磨而对齐的范围内互不相同。
在图12A所示的步骤中,对密封部4i的正面4ai及密封部123i的正面123ai进行研磨。例如,研磨装置的研磨机抵接于密封部4i的正面4ai及密封部123i的正面123ai,研磨机以与接触面垂直的轴为中心旋转,使研磨机连续旋转,直到各端子6-1~6-8的-Z侧端部露出在密封部4的正面4a并且各端子107-1~107-8的-Z侧端部露出在密封部123的正面123为止。凹部4a1的深度相比凹部4a1i(参照图2D)减小了相当于研磨厚度的量。密封部4的Z方向厚度相比密封部4i薄了相当于研磨厚度的量。凹部4a1的深度相比凹部4a1i减小了相当于研磨厚度的量。密封部123的Z方向厚度相比密封部123i薄了相当于研磨厚度的量。
这时,各端子6-1~6-8的-Z侧端部的Z位置与各端子107-1~107-8的-Z侧端部的Z位置大致相同。
在图12B所示的步骤中,在密封部4的正面4a形成多个电极8,在密封部123的正面123a形成多个电极8。形成在密封部4的正面4a的多个电极8与第1实施方式相同。形成在密封部123的正面123a的多个电极8对应于多个端子107-1~107-4。形成在正面123a的各电极8电连接于所对应的端子107的-Z侧的端部。由此,可获得多个芯片3-1~3-8呈阶梯状积层且面朝上安装并被密封、同时芯片5以能够面朝下安装的状态被密封的上部构造体120。
在图12C所示的步骤中,准备衬底10。露出在衬底10的正面10a的多个电极图案11分别与焊球凸块9耦合。可获得构成为芯片5能够面朝下安装的状态的下部构造体130。
以正面4a、123a与正面10a相对的方式将上部构造体120与下部构造体130对向配置。从Z方向透视时,以上部构造体120中的电极8与下部构造体130中的焊球凸块9重叠的方式,进行上部构造体120与下部构造体130的相对位置对准。
在图13A所示的步骤中,上部构造体120与下部构造体130在Z方向上相对接近。上部构造体120中的电极8与下部构造体130中的焊球凸块9相互耦合。
在图13B所示的步骤中,利用密封部122将上部构造体120与下部构造体130的间隙密封。密封部122以填埋密封部4、123及衬底10的间隙的方式填充。密封部122可由模具树脂等具有热塑性的第2绝缘物形成。由此,电极8、焊球凸块9被密封部122密封。
在图13C所示的步骤中,上部构造体120的外侧被密封部21密封。密封部21形成为从外侧覆盖支撑体2、密封部4、密封部122。密封部21也可以形成为到达衬底10的正面10a。密封部21可由模具树脂等具有热塑性的第3绝缘物形成。第3绝缘物的组成与第1绝缘物不同,与第2绝缘物也不同。
在图10所示的步骤中,在衬底10的背面10b安装多个外部电极23。外部电极23可与露出在衬底10的背面10b的通孔电极14接合。然后,通过切削进行单片化,获得半导体装置101。
如上所述,在第2实施方式中,在半导体装置101中,在将积层的多个芯片3-1~3-8密封的密封部4的正面4a的沿着XY平面观察时的中央附近设置凹部4a1。在凹部4a1内收容芯片5。由此,容易将芯片5相对于多个芯片3-1~3-8以大致等距离配线,因此,能够提供一种具有适于将多个芯片3-1~3-8及芯片5分别恰当地配置的构造的半导体装置101。
(第3实施方式)
接下来,对第3实施方式的半导体装置进行说明。以下,以与第1实施方式及第2实施方式不同的部分为中心进行说明。
在第2实施方式中,例示了包含将端子6-1~6-8、107-1~107-4经由衬底10连接于外部电极23的构造的半导体装置101,但在第3实施方式中,例示包含将端子6-1~6-8、107-1~107-4经由再配线层240连接于外部电极23的构造的半导体装置201。
具体来说,如图14所示,半导体装置201省略了电极8、焊球凸块9、密封部21(参照图10),且配置再配线层240以代替衬底10。图14是表示第3实施方式的半导体装置201的构成的剖视图。与第2实施方式相比,端子6-1~6-8、107-1~107-4与外部电极23的Z方向距离变得更小,并且Z高度降低了相当于密封部21的厚度的量,因此,可实现半导体装置201的更低背化。
此外,在芯片5与芯片3-4、3-8之间介置着密封部4。由此,与第1实施方式及第2实施方式相同的是,能够将芯片5在沿着XY平面观察时沿着XY方向安装在密封部4的中央附近。
在半导体装置201中,再配线层240包含用来将端子6-1~6-8、107-1~107-4与外部电极23连接的多层配线。再配线层240例如包含3层配线层,且包含配线层241、插塞层242、配线层243、插塞层244、配线层245、层间绝缘膜246。
多个端子6-1~6-8的-Z侧端部分别连接于配线层241中的电极图案。多个端子107-1~107-4的-Z侧端部分别连接于配线层241中的电极图案。
多个外部电极23分别连接于配线层245中的电极图案。
配线层241中的电极图案与配线层245中的电极图案可经由插塞层242中的插塞、配线层243中的线图案、插塞层244中的插塞等而连接。由此,端子6-1~6-8、107-1~107-4经由再配线层240而连接于外部电极23。
另外,如图14所示,半导体装置201的制造方法在以下方面与第2实施方式不同。图14是表示半导体装置201的构成的剖视图,但也可以用作表示半导体装置201的制造方法的剖视图。
例如,在半导体装置201的制造方法中,也可以在以与第2实施方式相同的方式进行到图12A所示的步骤之后,进行图14所示的步骤。在图14所示的步骤中,通过蒸镀法或溅镀法等,在密封体4的正面4a及密封部123的正面123a堆积导电层241i。在所述导电层241i上,形成选择性地覆盖多个端子6-1~6-8的-Z侧端部与多个端子107-1~107-4的-Z侧端部的抗蚀图案RP1。将抗蚀图案RP1作为掩模对导电层241i进行蚀刻加工。由此,形成包含选择性地覆盖多个端子6-1~6-8的-Z侧端部与多个端子107-1~107-4的-Z侧端部的电极图案的配线层241。
接着,堆积覆盖配线层241的绝缘膜246i。在所述绝缘膜246i上,形成在配线层241中的电极图案的位置具有开口的抗蚀图案RP2。将抗蚀图案RP2作为掩模对绝缘膜246i进行蚀刻加工。形成选择性地使配线层241中的电极图案露出的孔。在孔中埋入钨等导电物质。由此,形成与配线层241中的电极图案连接的插塞层242的插塞。
以相同的方式形成配线层243、插塞层244、配线层245。
然后,在再配线层240的-Z侧的面安装多个外部电极23。外部电极23与配线层245中的电极图案耦合。然后,通过切削进行单片化,获得半导体装置201。
如上所述,在第3实施方式中,在半导体装置201中,在将积层的多个芯片3-1~3-8密封的密封部4的正面4a的沿着XY平面观察时的中央附近设置凹部4a1。在凹部4a1内收容芯片5。由此,容易将芯片5相对于多个芯片3-1~3-8以大致等距离配线,因此,能够提供一种具有适于将多个芯片3-1~3-8及芯片5分别恰当地配置的构造的半导体装置201。
(其它实施方式)
(a)在第1实施方式及第2实施方式中,也可以设置密封部4来代替密封部22及密封部122。例如,在图5B中,不设置密封部22,而利用密封部4直接进行密封。在第2实施方式中,同样地,可以删除图13B中设置密封部122的步骤。由此,能够降低制造成本。这时,在密封部4与衬底10之间设置密封部21。
(b)在第1实施方式中,芯片5以面朝下状态通过倒装芯片接合将芯片5的端子连接于设置在衬底10的端子。这时,芯片5的电路面朝向衬底10侧而形成。也可以取而代之,将芯片5的端子通过打线接合而连接于设置在衬底10的端子。这时,芯片5的电路面形成为与衬底10为相反方向侧的面。通过利用打线接合进行连接,能够以低成本形成。
对本发明的几个实施方式进行了说明,但这些实施方式是作为示例提出的,并不意图限定发明的范围。这些新颖的实施方式能够以其它各种形态加以实施,且能够在不脱离发明的主旨的范围内进行各种省略、替换、变更。这些实施方式及其变化包含在发明的范围或主旨中,并且包含在权利要求书所记载的发明及其均等的范围内。
Claims (20)
1.一种半导体装置,具备:
支撑体;
多个第1芯片,积层在所述支撑体上;
第1密封部,将所述多个第1芯片密封,在与所述支撑体为相反侧的表面具有凹部,所述凹部包含与所述多个第1芯片分离的底面;
第2芯片,配置在所述凹部,功能与所述第1芯片不同;
多个第1端子,对应于所述多个第1芯片,分别从所述第1芯片的与所述支撑体为相反侧的面朝向积层方向延伸并贯通所述第1密封部;以及
第2端子,配置在所述第2芯片的与所述支撑体为相反侧的面。
2.根据权利要求1所述的半导体装置,其中
所述第1芯片是存储器芯片,
所述第2芯片是控制器芯片,
所述第1密封部于俯视下在所述表面的中央附近具有所述凹部。
3.根据权利要求1所述的半导体装置,其中
所述凹部于俯视下在内侧包含所述第2芯片。
4.根据权利要求3所述的半导体装置,其中
所述第2芯片在俯视下具有大致矩形,
所述凹部在俯视下具有大致矩形。
5.根据权利要求3所述的半导体装置,其中
所述第2芯片在俯视下具有大致矩形,
所述凹部在俯视下具有大致I字状。
6.根据权利要求3所述的半导体装置,其中
所述第2芯片在俯视下具有大致矩形,
所述凹部在俯视下具有大致十字状。
7.根据权利要求1所述的半导体装置,其中
所述凹部的底面与所述第2芯片的背面分离。
8.根据权利要求1所述的半导体装置,其中
所述凹部的底面与所述第2芯片的背面接触。
9.根据权利要求1所述的半导体装置,还具备第2密封部,
所述第2密封部至少填满所述凹部并将所述第2芯片密封。
10.根据权利要求9所述的半导体装置,还具备衬底,
所述衬底配置在所述积层方向上隔着所述第2密封部与所述第1密封部相反的一侧。
11.根据权利要求10所述的半导体装置,其中
所述第2密封部填埋所述凹部并且覆盖所述第1密封部,
所述衬底覆盖所述第2密封部。
12.根据权利要求10所述的半导体装置,还具备第3密封部,
所述第3密封部配置在所述第2密封部与所述衬底之间,且覆盖所述第1密封部。
13.根据权利要求9所述的半导体装置,还具备配线层,
所述配线层覆盖所述第1密封部的表面及所述第2密封部的表面,且与所述多个第1端子及所述第2端子电连接。
14.根据权利要求1所述的半导体装置,还具备缓冲部件,
所述缓冲部件介置在所述凹部的底面与所述第2芯片之间。
15.根据权利要求1所述的半导体装置,其中
所述第1端子的前端距离所述支撑体的高度与所述第1密封部的表面距离所述支撑体的高度均等。
16.根据权利要求9所述的半导体装置,其中
所述第2端子从所述第2芯片沿着所述积层方向延伸,
所述第2端子的前端距离所述支撑体的高度与所述第2密封部的表面距离所述支撑体的高度均等。
17.根据权利要求1所述的半导体装置,其中
所述第2端子从所述第2芯片沿着所述积层方向延伸,
所述第2端子的前端距离所述支撑体的高度与所述第1端子的前端距离所述支撑体的高度均等。
18.根据权利要求17所述的半导体装置,其中
所述第1端子的前端距离所述支撑体的高度与所述第1密封部的表面距离所述支撑体的高度均等,
所述第2端子的前端距离所述支撑体的高度与所述第2密封部的表面距离所述支撑体的高度均等。
19.根据权利要求17所述的半导体装置,还具备:
第2密封部,至少填满所述凹部,并将所述第2芯片密封;及
衬底,配置在积层方向上隔着所述第2密封部与所述第1密封部相反的一侧;
所述第1端子及所述第2端子分别连接于所述衬底。
20.根据权利要求17所述的半导体装置,还具备:
第2密封部,至少填埋所述凹部,并将所述第2芯片密封;及
配线层,覆盖所述第1密封部的表面及所述第2密封部的表面,且与所述多个第1端子及所述第2端子电连接;
所述第1端子及所述第2端子分别连接于所述配线层。
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