TWI826091B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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Abstract
一種電子封裝件,係於承載結構上設置電子元件及至少一封裝模組,且該封裝模組係包含有半導體晶片及遮蓋該半導體晶片之屏蔽結構,再以包覆層包覆該電子元件與該封裝模組,之後將屏蔽層設於該包覆層上且接觸該屏蔽結構,故該封裝模組因包含有半導體晶片及屏蔽結構而能同時具有晶片功能及屏蔽牆功能。
Description
本發明係有關一種半導體封裝結構,尤指一種具屏蔽機制之電子封裝件及其製法。
隨著半導體技術的演進,為了提升電性品質,多種半導體產品係具有屏蔽之功能,以防止電磁干擾(Electromagnetic Interference,簡稱EMI),尤其是系統封裝(System in Package,簡稱SiP)型產品。
如圖1A所示,習知半導體封裝件1係將複數半導體晶片11設於一封裝基板10上,再以封裝膠體13包覆各該半導體晶片11,並於該封裝膠體13之表面及該封裝基板10之側面上形成一金屬材屏蔽層14,以藉由該屏蔽層14保護該些半導體晶片11免受外界EMI影響,並可將至少一金屬材屏蔽牆12設於該些半導體晶片11周圍,以藉由該屏蔽牆12防止該些半導體晶片11之間相互電磁波(或訊號)干擾。
於前述半導體封裝件1中,該屏蔽牆12之製程可先製作金屬框架,再將其黏固於該封裝基板10上,如圖1B所示。或者,於該封裝膠體13中形成穿孔,再於該穿孔中電鍍金屬材,以作為該屏蔽牆12。
再者,由於終端產品均朝微小化趨勢設計,尤其是系統封裝(SiP)型產品,使該封裝基板10之表面10a之面積亦會隨之縮減。然而,該封裝基板10之表面10a上需配置該屏蔽牆12,故該屏蔽牆12不僅將佔用該封裝基板10之表面10a之局部面積而導致該封裝基板10無法進一步縮減,也佔用該封裝基板10之表面10a之可佈線區域,使該封裝基板10之佈線受限而無法進一步提升產品功能。
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:承載結構;電子元件,係接置於該承載結構上並電性連接該承載結構;封裝模組,係接置該承載結構上並電性連接該承載結構,且該封裝模組係包含有半導體晶片及遮蓋該半導體晶片至少一側之屏蔽結構;包覆層,係設於該承載結構上以包覆該電子元件與該封裝模組,且令該屏蔽結構之部分表面外露於該包覆層;以及屏蔽層,係設於該包覆層上並接觸該屏蔽結構外露之部分表面。
本發明亦提供一種電子封裝件之製法,係包括:於一承載結構上設置電子元件及封裝模組,其中,該電子元件與該封裝模組係電性連接該承載結構,且該封裝模組係包含有半導體晶片及遮蓋該半導體晶片至少一側之屏蔽結構;形成包覆層於該承載結構上,使該包覆層包覆該電子元件與該封裝模組,且令該屏蔽結構之部分表面外露於該包覆層;以及形成屏蔽層於該包覆層上,使該屏蔽層接觸該屏蔽結構外露之部分表面。
前述之電子封裝件及其製法中,該封裝模組復包含有包覆該半導體晶片之封裝層,以令該屏蔽結構形成於該封裝層上,且該封裝模組藉由複數導電元件設於該承載結構上。進一步,該封裝模組復包含一用以承載該半導體晶片之基板結構或線路結構,以令該基板結構或線路結構藉由該複數導電元件設於該承載結構上。
前述之電子封裝件及其製法中,承載結構係接置有複數該封裝模組。
前述之電子封裝件及其製法中,該承載結構上接置有複數功能晶片,以令該封裝模組設於該複數功能晶片之間,使該封裝模組作為該複數功能晶片之間的屏蔽牆。
前述之電子封裝件及其製法中,該包覆層係具有外露該屏蔽結構之至少一凹部。例如,該包覆層係具有外露該屏蔽結構之複數凹部。
前述之電子封裝件及其製法中,該包覆層之上表面係齊平該屏蔽結構之上表面。
前述之電子封裝件及其製法中,該屏蔽結構圍繞該半導體晶片之側面而未配置於該半導體晶片之上方。
前述之電子封裝件及其製法中,該屏蔽結構係包含至少一金屬層。
由上可知,本發明之電子封裝件及其製法中,主要藉由該封裝模組具有半導體晶片及屏蔽結構之設計,以供作為屏蔽牆的用途,故相較於習知技術,本發明之電子封裝件藉由該封裝模組取代習知屏蔽牆,不僅不會額外佔用該承載結構之封裝平面區域,有利於縮減該承載結構之尺寸而使該電子封裝件符合微小化之需求,且透過減少佔用該承載結構之佈線區域之面積,以提升終端產品之功能。
1:半導體封裝件
10:封裝基板
10a:表面
11,22:半導體晶片
12:屏蔽牆
13:封裝膠體
14:屏蔽層
2,4:電子封裝件
2a,3a,3b,4a:封裝模組
20:承載結構
20a:第一側
20b:第二側
20c:側面
21a,21b:電子元件
210,220:導電凸塊
211:導線
22a:作用面
22b:非作用面
23,33:包覆層
230,330,430:凹部
24:屏蔽層
25:封裝層
26,36:屏蔽結構
27:基板結構
28:導電元件
360:導電柱
361:第一金屬層
362:第二金屬層
37:線路結構
370:絕緣層
371:線路層
40:主動元件
41:被動元件
h1,h2:高度
圖1A係為習知半導體封裝件之剖面示意圖。
圖1B係為圖1A之局部立體示意圖。
圖2A至圖2D係為本發明之電子封裝件之製法之剖視示意圖。
圖2A-1係為圖2A之另一實施例之局部上視平面示意圖。
圖2C-1及圖2C-2係為圖2C之其它態樣之剖面示意圖。
圖2D-1、圖2D-2及圖2D-3係為圖2D之其它態樣之剖面示意圖。
圖3A、圖3B及圖3C係為圖2D之其它實施例之剖視示意圖。
圖4係為圖2D之另一實施例之剖視示意圖。
圖4A及圖4B係為圖2A-1之其它實施例之上視平面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並
非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
圖2A至圖2D圖係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示,於一承載結構20上設置至少一封裝模組2a及至少一電子元件21a,且該封裝模組2a及電子元件21a均電性連接該承載結構20。
所述之承載結構20係例如為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構,其係於絕緣材(圖略)上形成至少一線路層(圖略),如扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL)。應可理解地,該承載結構20亦可為其它承載晶片之板材,如晶圓(wafer)或其它具有金屬佈線(routing)之板體等,並不限於上述。
於本實施例中,該承載結構20係具有相對之第一側20a與第二側20b,且形成該線路層之材質係為銅,而該絕緣材係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材、或如綠漆、油墨等之防銲材。
所述之電子元件21a係設於該承載結構20之第一側20a上,且該電子元件21a係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如為半導體晶片,且該被動元件係例如為電阻、電容及電感。
於本實施例中,該電子元件21a係為主動元件,如功能晶片,其可藉由覆晶方式(如圖所示之導電凸塊210)、打線方式、直接接觸該線路層或其它適當方式電性連接該承載結構20之線路層,並無特別限制。
再者,該承載結構20之第一側20a上亦可承載其它主動元件40,如圖2A-1所示之功能晶片。
所述之封裝模組2a係包含有至少一半導體晶片22、包覆該半導體晶片23之封裝層25、及形成於該封裝層25上之屏蔽結構26。
於本實施例中,該封裝模組2a係為晶片尺寸封裝(Chip Scale Package,簡稱CSP)態樣。例如,該半導體晶片22係具有相對之作用面22a與非作用面22b,且該作用面22a上具有複數電極墊(未圖式),以結合含有銲錫材料之導電元件28,供該封裝模組2a藉由該些導電元件28結合至該承載結構20之第一側20a之線路層上,使該封裝模組2a電性連接該承載結構20。
再者,該封裝層25係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound),但不限於上述。
又,該封裝模組2a之種類繁多,並無特別限制。如圖3A所示之覆晶(Flip chip,簡稱FC)CSP態樣或扇出(Fan-out,簡稱FO)型晶圓級晶片尺寸封裝(Wafer Level Chip Scale Packaging,簡稱WLCSP)態樣,該封裝模組3a可包含一用以承載該半導體晶片22之基板結構27,如具有核心層與線路結構之封裝基板、無核心層(coreless)形式線路結構
之封裝基板、具導電矽穿孔(Through-silicon via,簡稱TSV)之矽中介板(Through Silicon interposer,簡稱TSI)或其它板型,其包含至少一絕緣層及至少一結合該絕緣層之線路層,使該半導體晶片22藉由複數導電凸塊220以覆晶方式電性連接該基板結構27之線路層,且該基板結構27藉由該些導電元件28設於該承載結構20上。
或者,如圖3B所示之WLCSP態樣,該封裝模組3b可包含一用以承載該半導體晶片22之線路結構37,如無核心層(coreless)形式,其包含至少一絕緣層370及至少一結合該絕緣層370之線路層371,使該半導體晶片22直接接觸該線路結構37之線路層371以電性連接該線路結構37之線路層371,且該線路結構37藉由該些導電元件28設於該承載結構20上。
甚至於,如圖3C所示之扇入型晶圓級晶片尺寸封裝(FI(Fan-In)-WLCSP)態樣,直接將屏蔽結構26形成於該半導體晶片22上,而未製作封裝層25。
應可理解地,可依需求配置複數封裝模組2a,4a,如圖4所示,且該複數封裝模組2a,4a之至少兩者之功能規格、尺寸大小(如圖4所示之高度h1,h2)或元件配置可相同或相異,並無特別限制。例如,該封裝模組4a可堆疊多個半導體晶片22,如圖4所示。
另外,該屏蔽結構26係為單一金屬層或多層金屬層(如圖3A所示之屏蔽結構36具有第一金屬層361與第二金屬層362),其可藉由濺鍍、蒸鍍、電鍍、化鍍或貼膜等方式製作以遮蓋該半導體晶片22至少一側,但不限於上述方式。例如,該屏蔽結構26可接地(圖未示)或未接地(如圖2A所示);或者,該屏蔽結構26,36可藉由電性連接該基板結構27(如圖3A所示)或線路結構37(如圖3B所示之導電柱360,其形成於該封裝
層25中以電性導通該屏蔽結構26與該線路結構37之線路層371)中的接地線路接地。應可理解地,該屏蔽結構26,36接地該基板結構27或線路結構37之方式繁多,並無特別限制,甚至於該屏蔽結構26,36亦可未接地該基板結構27(圖未示)或線路結構37(圖未示)。
如圖2B所示,於該電子元件21a堆疊另一電子元件21b,且該另一電子元件21b亦電性連接該承載結構20,以形成系統封裝(System in Package,簡稱SiP)型。
於本實施例中,該另一電子元件21b係藉由打線方式(如圖所示之導線211)或其它適當方式電性連接該承載結構20之線路層;於其它實施例中,該另一電子元件21b亦可採用覆晶方式電性連接其下方之電子元件21a。
如圖2C所示,形成一包覆層23於該承載結構20上,以令該包覆層23包覆該封裝模組2a與該些電子元件21a,21b,且使該封裝模組2a之屏蔽結構26之部分表面外露於該包覆層23。
於本實施例中,藉由該包覆層23上形成有至少一凹部230,以令該封裝模組2a之屏蔽結構26外露於該凹部230,使該屏蔽結構26之部分表面外露於該包覆層23。應可理解地,該包覆層23上可依需求形成複數凹部330,如圖2C-1所示。
再者,於其它實施例中,可藉由整平製程,如研磨方式,使該包覆層33之表面齊平該封裝模組2a(屏蔽結構26)之上表面,如圖2C-2所示,使該屏蔽結構26之上表面外露於該包覆層33。
如圖2D所示,接續圖2C所示之製程,形成一屏蔽層24於該包覆層23上並延伸至該凹部230中,使該屏蔽層24接觸該屏蔽結構26,以獲得本發明之電子封裝件2。
於本實施例中,該屏蔽層24可依需求延伸至該承載結構20之側面20c,但該屏蔽層24未形成於該承載結構20之第二側20b。例如,可藉由濺鍍、蒸鍍、電鍍、化鍍或貼膜等方式製作一如金屬層之屏蔽層24,但不限於上述方式。
再者,該屏蔽層24及/或屏蔽結構26,36係可接地該承載結構20。例如,該屏蔽結構26,36藉由導電元件28接地該承載結構20。
又,若接續圖2C-1或圖2C-2所示之製程,將得到圖2D-1或圖2D-2所示之電子封裝件,其中,如圖2D-1所示,該電子封裝件藉由複數凹部330之設計,以優化屏蔽層24之電性強度,且降低屏蔽層24與屏蔽結構26,36之間的電阻,故該屏蔽層24藉由該些凹部330以與屏蔽結構26之間形成更好的電性連接。如圖2D-2所示,藉由該屏蔽層24與該屏蔽結構26為大面積接觸,也可達到相同優化效果。應可理解地,該屏蔽結構26亦可僅圍繞該半導體晶片22之側面22c而未配置於該半導體晶片22之上方,如圖2D-3所示。
另外,如圖4所示之電子封裝件4,可於該包覆層23上形成深淺不同的凹部230,430,以外露各該封裝模組2a,4a之屏蔽結構26,使該屏蔽層24能延伸至該些凹部230,430中以接觸各該封裝模組2a,4a之屏蔽結構26。應可理解地,該些封裝模組2a,4a之排設可依需求配置,如圖4A及圖4B所示,並於其周圍配置至少一如功能晶片之主動元件40及/或至少一如電容、電感或電阻之被動元件41,使該些封裝模組2a,4a可同時作為該些功能晶片(如圖2A-1或圖4A所示之主動元件40與電子元件21a,21b)之間的屏蔽牆。
因此,本發明之製法主要藉由該封裝模組2a,3a,3b,4a中的半導體晶片22為功能晶片,不僅具有晶片所需之功能,且能透過屏蔽結構
26,36產生EMI防護的功能,並透過該封裝模組2a,3a,3b,4a於該電子封裝件2,4的位置設計,以供作為屏蔽牆的用途,故相較於習知技術,本發明之封裝模組2a,3a,3b,4a具有多功能,以取代習知屏蔽牆,使該封裝模組2a,3a,3b,4a不僅不會額外佔用該承載結構20之第一側20a之封裝平面區域,以利於縮減該承載結構20之尺寸(如第一側20a之面積),而使該電子封裝件2,4符合微小化之需求,同時透過減少佔用該承載結構20之佈線區域之面積,以利於提升終端產品之功能。
例如,基於相同功能下,習知封裝基板10需配置半導體晶片11與屏蔽牆12等兩個元件,而本發明之承載結構20上僅需配置該封裝模組2a之單一元件,故本發明之承載結構20之第一側20a之其它可用區域將多於習知封裝基板10之表面10a之其它可用區域。
再者,相較於習知屏蔽牆之製程,本發明之製法中無需額外製作金屬框架,也無需額外於該包覆層23中進行穿孔、鍍銅等習知屏蔽牆作業,因而能有效降低製作成本。
又,該封裝模組2a,3a,3b,4a中之半導體晶片22係為功能晶片,不僅具有晶片功能,且還可藉由屏蔽結構26達到自身EMI防護的功能。
本發明亦提供一種電子封裝件2,4,其包括:一承載結構20、至少一電子元件21、至少一封裝模組2a,3a,3b,4a、一包覆層23,33以及至少一屏蔽層24。
所述之電子元件21係設於該承載結構20上並電性連接該承載結構20。
所述之封裝模組2a,3a,3b,4a係設於該承載結構20上並電性連接該承載結構20,且該封裝模組2a,3a,3b,4a係包含有半導體晶片22及遮蓋該半導體晶片22至少一側之屏蔽結構26,36。
所述之包覆層23,33係設於該承載結構20上以包覆該電子元件21與該封裝模組2a,3a,3b,4a。
所述之屏蔽層24係設於該包覆層23,33上並接觸該屏蔽結構26,36。
於一實施例中,該封裝模組2a,3a,3b,4a復包含有包覆該半導體晶片22之封裝層25,以令該屏蔽結構26,36形成於該封裝層25上,且該封裝模組2a,3a,3b,4a藉由複數電性連接該半導體晶片22之導電元件28設於該承載結構20上。進一步,該封裝模組3a,3b復包含一用以承載該半導體晶片22之基板結構27或線路結構37,以令該基板結構27或線路結構37藉由該複數導電元件28設於該承載結構20上。
於一實施例中,該包覆層23係具有外露該屏蔽結構26之至少一凹部230,330。例如,該封裝模組2a係對應多個該凹部330,如圖2D-1所示。
於一實施例中,該包覆層33之上表面係齊平該屏蔽結構26之上表面,如圖2D-2所示。
於一實施例中,該屏蔽結構26亦可僅圍繞該半導體晶片22之側面22c而未配置於該半導體晶片22之上方,如圖2D-3所示。
於一實施例中,該承載結構20上接置有複數該封裝模組2a,2b,如圖4A及圖4B所示。例如,該複數封裝模組2a,4a之至少兩者之高度h1,h2係不相同,如圖4所示。進一步,該包覆層23係具有外露各該
屏蔽結構26之複數凹部230,430,且該複數凹部230,430之至少兩者之深度不相同,如圖4所示。
於一實施例中,該承載結構20上接置有複數功能晶片(如主動元件40與電子元件21a,21b),以令該封裝模組2a,4a設於該複數功能晶片(如主動元件40與電子元件21a,21b)之間,使該封裝模組2a,4a作為該複數功能晶片(如主動元件40與電子元件21a,21b)之間的屏蔽牆。
於一實施例中,該屏蔽結構26,36係包含至少一金屬層(如圖3A所示之第一金屬層361與第二金屬層362)。
綜上所述,本發明之電子封裝件及其製法,係藉由該封裝模組具有半導體晶片及屏蔽結構之設計,以供作為屏蔽牆的用途,故本發明之電子封裝件藉由該封裝模組取代習知屏蔽牆,不僅不會額外佔用該承載結構之封裝平面區域,有利於縮減該承載結構之尺寸而使該電子封裝件符合微小化之需求,同時透過減少佔用該承載結構之佈線區域之面積,以提升終端產品之功能。
再者,該封裝模組中之半導體晶片係為功能晶片,不僅具有晶片功能,且還可藉由屏蔽結構達到自身EMI防護的功能。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2:電子封裝件
2a:封裝模組
20:承載結構
20a:第一側
20b:第二側
20c:側面
21a,21b:電子元件
22:半導體晶片
23:包覆層
230:凹部
24:屏蔽層
25:封裝層
26:屏蔽結構
28:導電元件
Claims (20)
- 一種電子封裝件,係包括:承載結構;電子元件,係接置於該承載結構上並電性連接該承載結構;封裝模組,係接置該承載結構上並電性連接該承載結構,且該封裝模組包含有半導體晶片及遮蓋該半導體晶片至少一側之屏蔽結構,其中,該屏蔽結構未直接接觸該承載結構;包覆層,係設於該承載結構上以包覆該電子元件與該封裝模組,且令該屏蔽結構之部分表面外露於該包覆層;以及屏蔽層,係設於該包覆層上並接觸該屏蔽結構外露之部分表面。
- 如請求項1所述之電子封裝件,其中,該封裝模組復包含有包覆該半導體晶片之封裝層,以令該屏蔽結構形成於該封裝層上,且該封裝模組藉由複數導電元件設於該承載結構上。
- 如請求項2所述之電子封裝件,其中,該封裝模組復包含一用以承載該半導體晶片之基板結構或線路結構,以令該基板結構或線路結構藉由該複數導電元件設於該承載結構上。
- 如請求項1所述之電子封裝件,其中,該承載結構上接置有複數該封裝模組。
- 如請求項1所述之電子封裝件,其中,該承載結構上接置有複數功能晶片,以令該封裝模組設於該複數功能晶片之間,使該封裝模組作為該複數功能晶片之間的屏蔽牆。
- 如請求項1所述之電子封裝件,其中,該包覆層係具有外露該屏蔽結構之至少一凹部。
- 如請求項1所述之電子封裝件,其中,該包覆層係具有外露該屏蔽結構之複數凹部。
- 如請求項1所述之電子封裝件,其中,該包覆層之上表面係齊平該屏蔽結構之上表面。
- 如請求項1所述之電子封裝件,其中,該屏蔽結構圍繞該半導體晶片之側面而未配置於該半導體晶片之上方。
- 如請求項1所述之電子封裝件,其中,該屏蔽結構係包含至少一金屬層。
- 一種電子封裝件之製法,係包括:於一承載結構上設置電子元件及封裝模組,其中,該電子元件與該封裝模組係電性連接該承載結構,且該封裝模組係包含有半導體晶片及遮蓋該半導體晶片至少一側之屏蔽結構,其中,該屏蔽結構未直接接觸該承載結構;形成包覆層於該承載結構上,使該包覆層包覆該電子元件與該封裝模組,且令該屏蔽結構之部分表面外露於該包覆層;以及形成屏蔽層於該包覆層上,使該屏蔽層接觸該屏蔽結構外露之部分表面。
- 如請求項11所述之電子封裝件之製法,其中,該封裝模組復包含有包覆該半導體晶片之封裝層,以令該屏蔽結構形成於該封裝層上,且該封裝模組藉由複數導電元件設於該承載結構上。
- 如請求項12所述之電子封裝件之製法,其中,該封裝模組復包含一用以承載該半導體晶片之基板結構或線路結構,以令該基板結構或線路結構藉由該複數導電元件設於該承載結構上。
- 如請求項11所述之電子封裝件之製法,其中,該承載結構上接置有複數該封裝模組。
- 如請求項11所述之電子封裝件之製法,其中,該承載結構上接置有複數功能晶片,以令該封裝模組設於該複數功能晶片之間,使該封裝模組作為該複數功能晶片之間的屏蔽牆。
- 如請求項11所述之電子封裝件之製法,其中,該包覆層係具有外露該屏蔽結構之至少一凹部。
- 如請求項11所述之電子封裝件之製法,其中,該包覆層係具有外露該屏蔽結構之複數凹部。
- 如請求項11所述之電子封裝件之製法,其中,該包覆層之上表面係齊平該屏蔽結構之上表面。
- 如請求項11所述之電子封裝件之製法,其中,該屏蔽結構圍繞該半導體晶片之側面而未配置於該半導體晶片之上方。
- 如請求項11所述之電子封裝件之製法,其中,該屏蔽結構係包含至少一金屬層。
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US20050189622A1 (en) * | 2004-03-01 | 2005-09-01 | Tessera, Inc. | Packaged acoustic and electromagnetic transducer chips |
US20170330839A1 (en) * | 2016-05-13 | 2017-11-16 | Nepes Co., Ltd. | Semiconductor package and method of manufacturing the same |
TW202135245A (zh) * | 2020-03-09 | 2021-09-16 | 南茂科技股份有限公司 | 晶片封裝結構及其製造方法 |
TW202139375A (zh) * | 2020-04-01 | 2021-10-16 | 矽品精密工業股份有限公司 | 電子封裝件 |
TW202141740A (zh) * | 2020-04-16 | 2021-11-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050189622A1 (en) * | 2004-03-01 | 2005-09-01 | Tessera, Inc. | Packaged acoustic and electromagnetic transducer chips |
US20170330839A1 (en) * | 2016-05-13 | 2017-11-16 | Nepes Co., Ltd. | Semiconductor package and method of manufacturing the same |
TW202135245A (zh) * | 2020-03-09 | 2021-09-16 | 南茂科技股份有限公司 | 晶片封裝結構及其製造方法 |
TW202139375A (zh) * | 2020-04-01 | 2021-10-16 | 矽品精密工業股份有限公司 | 電子封裝件 |
TW202141740A (zh) * | 2020-04-16 | 2021-11-01 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
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