TWI821820B - 互連基板、半導體封裝及製造互連基板之方法 - Google Patents

互連基板、半導體封裝及製造互連基板之方法 Download PDF

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Publication number
TWI821820B
TWI821820B TW110146760A TW110146760A TWI821820B TW I821820 B TWI821820 B TW I821820B TW 110146760 A TW110146760 A TW 110146760A TW 110146760 A TW110146760 A TW 110146760A TW I821820 B TWI821820 B TW I821820B
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Taiwan
Prior art keywords
layer
interconnect
metal
insulating layer
film
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TW110146760A
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English (en)
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TW202301622A (zh
Inventor
瀬戶基司
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日商鎧俠股份有限公司
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Priority claimed from US17/459,349 external-priority patent/US12027452B2/en
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202301622A publication Critical patent/TW202301622A/zh
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    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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Abstract

實施例提供一種能夠防止一互連材料之遷移之互連基板及半導體封裝。 根據一項實施例，一種互連基板包含一絕緣層。一第一互連層係在該絕緣層之一第一側上。一第二互連層係在該絕緣層之與該第一側相對之一第二側上。包括碳之一第一膜覆蓋該等第一及第二互連層之至少部分。

Description

互連基板、半導體封裝及製造互連基板之方法
本文描述之實施例大體上係關於一種互連基板、一種半導體封裝、以及一種製造一互連基板之方法。
一電氣裝置或各種半導體裝置封裝中之一互連板採用一互連基板。當電氣裝置或半導體裝置封裝在不同環境中使用時，互連基板中使用之一金屬可從基板遷移。
實施例提供一種能夠防止一互連材料遷移之互連基板及半導體封裝。
一般言之，根據一項實施例，一種互連基板包含一絕緣層。一第一互連層係在該絕緣層之一第一側上。一第二互連層係在該絕緣層之與該第一側相對之一第二側上。包括碳之一第一膜覆蓋該等第一及第二互連層之至少部分。
將參考圖式描述根據本發明之特定實例實施例。應注意，實例實施例不旨在限制本發明之範疇。一般言之，圖式係示意性的或概念性的，且所描繪之元件及態樣之比例及尺寸不一定與實際尺寸及比例相同。在本說明書中，先前針對一項實施例描述之元件及/或態樣可在後續實施例之描述中藉由相同之參考符號表示，並且可從(若干)後續描述中省略對此等重複之元件及/或態樣之詳細描述。 (第一實施例)
圖1A係展示根據一第一實施例之一半導體封裝1之一實例之一示意性橫截面視圖。根據第一實施例之半導體封裝1包含一互連基板10、半導體晶片C1、金屬線40、樹脂層20及60、以及金屬凸塊80。
互連基板10包括一絕緣層11、互連層12、13及14以及一阻焊劑16。互連層12設置在絕緣層11之一第一表面11a上。互連層13設置在與第一表面11a相對之一第二表面11b上。絕緣層11設置在互連層12與13之間。穿孔15可設置在絕緣層11中。在此情況下，互連層12及13經由設置在一穿孔15內之互連層14 (亦稱為一穿孔連接器、一通孔連接器、一層間互連或類似者)彼此電連接。例如，諸如玻璃環氧樹脂之一絕緣材料用於絕緣層11。例如，諸如銅之一低電阻金屬材料用於互連層12至14。
複數個半導體晶片C1堆疊在互連基板10之更靠近絕緣層11之第一表面11a之一第一表面上。複數個半導體晶片C1各使用諸如一DAF (晶粒附著膜)之一粘合劑粘性接合至互連基板10中之阻焊劑16上或另一半導體晶片C1上。一金屬線40從一半導體晶片C1之一墊接合至互連層12，並將墊電連接至互連層12。可為複數個半導體晶片C1提供複數根金屬線40。同樣，半導體晶片C1可經由對應於一金屬線40或類似者之接合線電連接至另一半導體晶片C1。
半導體晶片C1及金屬線40用樹脂層60覆蓋。一絕緣樹脂材料用於樹脂層60。
金屬凸塊80設置在互連基板10之更靠近絕緣層11之第二表面11b之一第二表面上。金屬凸塊80電連接至互連層13。金屬凸塊80將其他基板及/或設備電連接至互連層13。例如，諸如一焊料之一低電阻金屬材料用於金屬凸塊80。
圖1B係展示互連基板10之部分之一實例之一放大橫截面視圖。互連基板10具有設置在互連層12至14內之一碳膜18。碳膜18覆蓋互連層12至14之至少部分。碳膜18充當一阻障膜，並且能夠防止材料之擴散。例如，碳膜18阻止形成互連層12至14之諸如銅之一金屬擴散。碳膜18較佳地儘可能在不影響處理之情況下覆蓋互連層12至14。例如，碳膜18係含有或包含碳之一膜，並且可藉由一電鍍法或其他沉積方法形成。例如，碳膜18在一些例項中可為藉由一電化學電鍍程序或以其他方式形成之一實質上純碳膜。
碳在電離傾向上高於互連層12至14中使用之金屬(諸如銅)。此外，與諸如氮化鈦(TiN)、氮化鉭(TaN)、金或鉑之金屬材料相比，碳係一低成本材料，因此與互連層一起使用碳通常不導致一互連基板之製造的成本增加。此外，碳可藉由一電鍍技術(例如，一電化學電鍍程序，諸如一熔鹽電化學程序)形成為一膜，並且亦具有優異之耐水性及導電性。因此，用碳膜18覆蓋互連層12至14使得可在不損害互連層12至14之導電性之情況下防止來自互連層12至14之擴散。此外，可藉由使用碳膜18來防止水通過。由此，可防止互連層12至14之腐蝕。
圖2A至圖8B描繪與根據第一實施例之製造互連基板10之一方法之一實例相關之態樣。注意，圖2A至圖8A展示橫截面，且圖2B至8B展示平面圖。
首先，如圖2A及圖2B所展示，在絕緣層11之第一表面11a及第二表面11b上形成材料膜12_1及13_1。絕緣層11充當一核心。例如，諸如銅之一金屬材料用於材料膜12_1及13_1。材料膜12_1及13_1可使用一濺鍍法、一電鍍法或類似者形成。材料膜12_1及13_1之厚度各例如為10 μm。材料膜12_1及13_1分別構成互連層12至13之部分。
接著，如圖3A及圖3B所展示，根據需要在絕緣層11及材料膜12_1及13_1中形成穿孔15。各穿孔15以穿透絕緣層11之第一表面11a與第二表面11b之間之此一方式形成。一穿孔15可使用一光微影技術及一蝕刻技術形成，或可使用一雷射光束機械加工方法形成。
接著，如圖4A及圖4B所展示，使用一電鍍法在絕緣層11上形成一碳材料。因此，在第一表面11a上之材料膜12_1、第二表面11b上之材料膜13_1及穿孔15之一內表面上形成一碳膜18。碳膜18之一厚度例如為1微米(μm)。碳膜18覆蓋材料膜12_1上及13_1之表面。如上文提及，碳膜18具有比諸如銅之一金屬更高之一電離傾向，並且具有優異之耐水性及導電性。因此，碳膜18能夠防止材料膜12_1及13_1之遷移及腐蝕，但實質上不損害材料膜12_1及13_1之導電性。
接著，如圖5A及圖5B所展示，使用一濺鍍法、一電鍍法或類似者在碳膜18上形成材料膜12_2及13_2。例如，諸如銅之一金屬材料用於材料膜12_2及13_2，類似於材料膜12_1及13_1。材料膜12_2及13_2之厚度各例如為5 μm。與材料膜12_1及13_1類似之材料膜12_2及13_2分別充當互連層12及13之材料。碳膜18係在材料膜12_1與12_2之間以及材料膜13_1與13_2之間。然而，由於碳膜18係導電的，故碳膜18不顯著地損害材料膜12_1與12_1之間或材料膜13_1與13_2之間之導電率。即，材料膜12_1及12_2仍然能夠用作一整合式互連層12。另外，材料膜13_1及13_2類似地能夠用作一整合式互連層13。材料膜12_1及12_2亦將被統稱為「互連層12」，並且材料膜13_1及13_2亦將被統稱為「互連層13」。
接著，如圖6A及圖6B所展示，使用一微影及蝕刻技術將互連層12及13圖案化為所要互連圖案。在此處理期間，在形成(若干)互連圖案時移除碳膜18之部分以及互連層12及13。
接著，如圖7A及圖7B所展示，在絕緣層11之第一表面11a及第二表面11b上形成阻焊劑16。阻焊劑16亦填充各穿孔15。可使用微影及蝕刻技術對阻焊劑16進行圖案化。阻焊劑16以曝露互連層12及13之接觸區域並覆蓋其他區域之此一方式圖案化。
接著，如圖8A及圖8B所展示，使用一濺鍍法、一電鍍法或類似者在由阻焊劑16曝露之接觸區域上形成一接觸膜19。例如，諸如金或鎳之一低電阻金屬材料用於接觸膜19。
由此完成互連基板10。
如圖1A所展示，在於半導體封裝體1中使用互連基板10之一情況下，使用樹脂層20將一個半導體晶片C1直接粘性接合至互連基板10之互連層12及阻焊劑16。使用一樹脂層20將另一半導體晶片C1粘性接合至第一半導體晶片C1上。半導體晶片C1係(例如)記憶體晶片。複數個半導體晶片C1 (例如)以一交錯之方式配置，使得半導體晶片C1之墊不與下方之半導體晶片C1之墊重疊。
接著，半導體晶片C1之墊藉由金屬絲40電連接至互連板10上之一接觸膜19。
接著，互連基板10上之半導體晶片C1及金屬線40用樹脂層60覆蓋。樹脂層60由此密封且保護半導體晶片C1及金屬線40。由此完成圖1所展示之半導體封裝1。
根據第一實施例之互連基板10之互連層12及13之至少部分用碳膜18覆蓋。
注意，第一實施例中之碳膜18特別覆蓋構成互連層12及13之一子部分之材料膜12_1及13_1。但是，替代材料膜12_1及13_1或除了材料膜12_1及13_1外，一碳膜18可覆蓋材料膜12_2及13_2。由此，可進一步防止互連層12及13之遷移及/或腐蝕，而不損害互連層12及13之導電率。 (第二實施例)
圖9係展示根據一第二實施例之一互連板100之一實例之一平面圖。互連板100係(例如)用於對一DUT (被測裝置)執行諸如一HAST測試(高度加速蒸汽及溫度測試)之一可靠性測試之一可靠性測試裝置之一主機板。將參考圖10描述一可靠性測試裝置之總體組態。在一可靠性測試中，一使用者將至少一個DUT安裝在互連板100上，並為安裝在互連板100上之插座或類似者中之該(等)DUT設定周圍氣氛之測試條件(諸如一溫度及一濕度位準)。接著，可靠性測試裝置量測DUT之特性。由此可評估DUT在加速條件下之可靠性。各DUT可為(例如)諸如圖1A所描繪之一半導體封裝1。
用於此一可靠性測試之互連板100曝露於與其中放置DUT之氣氛相似之一氣氛中。因此，互連板100內之互連層之材料之遷移、劣化及類似者本身可不利地影響可靠性測試。在第二實施例中，將與根據第一實施例之互連基板10之組態相似之組態應用至互連板100。
互連板100包括一互連基板110、插座120、連接器130、互連區段140、一板連接器150及板端子160。一般而言，互連基板110具有與互連基板10 (參照圖1B描述)基本上相同之一結構組態，但是在比例上存在差異。如同圖1B所展示，碳膜18覆蓋互連基板110內之互連層12至14之至少部分。碳膜18防止組態互連層12至14之金屬(諸如銅)之擴散。碳膜18包括碳並且可藉由一電鍍法形成。
各插座120充當一安裝區段，並設置在阻焊劑16上。各插座120具有與一DUT之一外部形狀匹配或稍大之一框架狀或碗狀形狀。插座120用於將DUT固定至互連基板110上之一預定位置。例如，一絕緣材料(諸如一樹脂)用於插座120。將DUT裝配至一插座120中使得可將DUT實體地安裝在互連基板110上。此外，將DUT裝配在插座120中亦使得可相對於互連板100固定DUT之一位置並量測DUT之特性。
各連接器130設置在一插座120之底部部分處並電連接至互連層12及13 (圖1B所展示)。連接器130具備對應於DUT之各端子之連接器位置。在將DUT附接在插座120中後，DUT之端子(例如，圖1所展示之一凸塊80)電連接至一連接器130之一對應連接器部分。
互連區段140係連接在連接器130與板連接器150之間以阻止一過量電流在連接器130與板連接器150之間通過之電阻元件(電阻器)。
板連接器150係用於當互連板100附接至可靠性測試裝置200中時，將可靠性測試裝置200 (圖10所展示)或另一裝置(例如，一電腦或其他外部裝置)之端子電連接至安裝在互連板100上之一DUT之一連接器。一外部裝置或可靠性測試裝置200本身量測DUT之電特性。板連接器150可電連接至互連層12至14之任一者。板連接器150可用於從外部向DUT供應一控制信號及/或向DUT供應電力，或用於從一DUT向外部輸出一信號。
各板端子160係用於當互連板100附接至可靠性測試裝置200中時與可靠性測試裝置200或一外部裝置進行電連接之一電極。板端子160類似於板連接器150。板連接器150及板端子160可充當用於量測可靠性測試裝置200之一腔室210內之DUT之電特性之量測端子。
圖10係展示一可靠性測試裝置200之一實例之一示意性外部視圖。可靠性測試裝置200具有一腔室210及一蓋區段220。腔室210設置在一主體區段內側，並且能夠在其中容納互連板100。腔室210可能夠容納複數個互連板100。蓋區段220經組態以能夠敞開/閉合腔室210之開口。閉合蓋區段220使腔室210之內部能夠被氣密地密封。可靠性測試裝置200包含一加熱器、一冷卻系統、一加濕器及類似者，並且能夠改變互連板100之周圍氣氛之諸如溫度及濕度之條件。由此，可靠性測試裝置200能夠在一高濕度氣氛中在高溫下執行互連板100之一可靠性測試(例如，一HAST測試)。
接著，將描述製造互連板100之一方法。
製造互連基板110之一方法可被視為與根據第一實施例之製造互連基板10之方法基本上相同。
將各插座120裝配至阻焊劑上，例如圖1B所展示之阻焊劑16，該阻焊劑形成在互連基板110上。接著，在插座120中設置電連接至互連層12及13之連接器130。接著，在互連基板110上形成板連接器150及各板端子160。如此，完成互連板100。
與根據第一實施例之互連板10中之互連層類似，根據第二實施例之互連板100中之互連層12及13 (參考圖1B)之至少部分被碳膜18覆蓋。因此，碳膜18能夠阻止互連層12及13之遷移及腐蝕，但實質上不損害互連層12及13之導電性。此外，碳膜18之使用不導致互連板100之一顯著成本增加，此係因為碳膜18通常係一低成本材料。
注意，在類似於第一實施例之第二實施例中，替代材料膜12_1及13_1或除了材料膜12_1及13_1外，碳膜18可覆蓋材料膜12_2及13_2。由此，可進一步防止互連層12及13之遷移及腐蝕，而不損害互連層12及13之導電率。
例如，使用根據第二實施例之互連板100，對一BGA (球柵陣列)類型之半導體封裝1執行一測試。腔室210之內部溫度被設定為大約110°C，且內部濕度被設定為大約85%。
若互連板100不具有碳膜18，並且HAST長約1000小時，則通常必須在HAST之後更換互連板100。
當互連板100如在根據本實施例之互連板100之情況中具有碳膜18時，互連板100經歷較少劣化，並且即使在1000小時長之HAST之後亦不必更換互連板100。因此，將碳膜18施敷至互連板100使得可延長互連板100之壽命。
雖然已描述特定實施例，但此等實施例已僅藉由實例來呈現，且不旨在限制本發明之範疇。實際上，本文描述之新穎實施例可以各種其他形式體現；此外，可在不脫離本發明之精神之情況下做出呈本文描述之實施例之形式之各種省略、替換及改變。隨附發明申請專利範圍及其等之等效物旨在涵蓋如將落在本發明之範疇及精神內之此等形式或修改。 相關申請案之交叉參考
本申請案基於2021年3月12日申請之日本專利申請案第2021-040554號及2021年8月27日申請之美國專利申請案第17/459349號並要求其等之優先權，該等案之全部內容以引用之方式併入本文中。
1:半導體封裝 10:互連基板 11:絕緣層 11a:第一表面 11b:第二表面 12:互連層 12_1:材料膜 12_2:材料膜 13:互連層 13_1:材料膜 13_2:材料膜 14:互連層 15:穿孔 16:阻焊劑 18:碳膜 19:接觸膜 20:樹脂層 40:金屬線 60:樹脂層 80:金屬凸塊 100:互連板 110:互連基板 120:插座 130:連接器 140:互連區段 150:板連接器 160:板端子 200:可靠性測試裝置 210:腔室 220:蓋區段 C1:半導體晶片
圖1A係根據一第一實施例之一半導體封裝之一橫截面視圖。
圖1B係一互連基板之部分之一放大橫截面視圖。
圖2A至圖8B描繪根據第一實施例之製造一互連基板之一方法之態樣。
圖9係根據一第二實施例之一互連板之一平面圖。
圖10係一可靠性測試裝置之一示意性外部視圖。
10:互連基板
11:絕緣層
11a:第一表面
11b:第二表面
12:互連層
13:互連層
14:互連層
15:穿孔
16:阻焊劑
18:碳膜

Claims (16)

  1. 一種互連基板，其包括：一絕緣層；一第一互連層，其在該絕緣層之一第一側上；一第二互連層，其在該絕緣層之一第二側上，該第二側與該第一側相對；一第一膜，其包括碳且覆蓋該等第一及第二互連層之至少部分；一安裝區段，其在該第一互連層上，用於一半導體封裝；一連接器，其在該安裝區段中，該連接器經組態以電接觸該半導體封裝，該連接器電連接至該等第一及第二互連層之至少一者；及一量測端子，其用於經由該等第一及第二互連層之至少一者將一外部裝置電連接至該連接器。
  2. 如請求項1之互連基板，其中該等第一及第二互連層各包括銅。
  3. 如請求項1之互連基板，其進一步包括：一半導體晶片，其附接至該絕緣層之該第一側；一接合線，其將該半導體晶片電連接至該第一互連層；一焊球，其在該絕緣層之該第二側上，該焊球電連接至該第二互連層；及一絕緣樹脂材料，其在覆蓋該半導體晶片及該接合線之該絕緣層之 該第一側上。
  4. 一種互連基板，其包括：一絕緣層；一第一互連層，其在該絕緣層之一第一側上；一第二互連層，其在該絕緣層之一第二側上，該第二側與該第一側相對；一第一膜，其包括碳且覆蓋該等第一及第二互連層之至少部分；一穿孔，其從該第一側穿過該絕緣層至該第二側；及一互連器，其在該穿孔中並電連接該等第一及第二互連層；其中該第一膜延伸穿過該穿孔，且在該絕緣層與該互連器之間。
  5. 如請求項4之互連基板，其中該第一膜係從該第一側至該第二側之一連續膜。
  6. 如請求項4之互連基板，其中該第一膜係一碳膜。
  7. 一種半導體裝置，其包括：一絕緣層，其具有一第一表面及一第二表面；一穿孔，其在該絕緣層中，該穿孔從該第一表面延伸至該第二表面；一第一金屬層，其在該絕緣層之該第一表面上，該第一金屬層直接接觸該第一表面； 一第二金屬層，其在該絕緣層之該第二表面上，該第二金屬層直接接觸該第二表面；一碳膜，其在該第一金屬層及該第二金屬層上；及一金屬互連器部分，其在該穿孔中，其中該第一金屬層係在該第一表面與該碳膜之間，該第二金屬層係在該第二表面與該碳膜之間，及該碳膜延伸穿過該穿孔並且從該第一表面至該第二表面係連續的。
  8. 如請求項7之半導體裝置，其中該金屬互連器部分包含：一第一部分，其在該第一表面上，該碳膜係在該第一部分與該第一金屬層之間，一第二部分，其在該穿孔中，該碳膜係在該第二部分與該絕緣層之間，及一第三部分，其在該第二表面上，該碳膜係在該第三部分與該第二金屬層之間。
  9. 如請求項7之半導體裝置，其進一步包括：一半導體晶片，其在該第一表面上，該半導體晶片電連接至該第一金屬層；及一焊球，其在該第二表面上，該焊球電連接至該第二金屬層。
  10. 如請求項7之半導體裝置，其進一步包括：一晶片插座，其在該第一表面上，該晶片插座將該插座中之一半導 體晶片電連接至該第一金屬層；及一板端子，其在該絕緣層之一端部上，該板端子經由該等第一及第二金屬層之至少一者電連接至該晶片插座。
  11. 一種製造一互連基板之方法，該方法包括：在一絕緣層之一第一表面上形成一第一金屬膜；在該絕緣層之一第二表面上形成一第二金屬膜，該第二表面與該第一表面相對；在該絕緣層中形成一穿孔，該穿孔從該第一表面延伸至該第二表面；在該第一金屬膜、該第二金屬膜及該穿孔之一內表面上形成一連續碳膜；在該連續碳膜上形成一第三金屬膜；藉由對該第一金屬膜、該第二金屬膜及該第三金屬膜進行圖案化而形成一第一互連層及一第二互連層；及形成覆蓋該第一互連層及該第二互連層之部分並填充該穿孔之一第一樹脂層。
  12. 如請求項11之方法，其進一步包括：將用於一封裝半導體晶片之一插座連接器放置在該第一樹脂層上，該插座連接器電連接至至少該第一互連層。
  13. 如請求項12之方法，其進一步包括： 在該絕緣層之一端部上形成一板端子，該板端子經由該第一互連層及該第二互連層之至少一者連接至該插座連接器。
  14. 如請求項11之方法，其中該碳膜係藉由一電鍍法形成。
  15. 如請求項11之方法，其中該第三金屬膜係藉由一電鍍法形成。
  16. 如請求項11之方法，其中該第一金屬層、該第二金屬層及該第三金屬層為銅。
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Publication number Priority date Publication date Assignee Title
US20120299193A1 (en) * 2010-02-15 2012-11-29 Renesas Electronics Corporation Semiconductor device, semiconductor package, interposer, semiconductor device manufacturing method and interposer manufacturing method
TW201944869A (zh) * 2018-04-17 2019-11-16 新加坡商星科金朋有限公司 半導體裝置和形成對於屏蔽層具有增強接觸之導電通孔的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120299193A1 (en) * 2010-02-15 2012-11-29 Renesas Electronics Corporation Semiconductor device, semiconductor package, interposer, semiconductor device manufacturing method and interposer manufacturing method
TW201944869A (zh) * 2018-04-17 2019-11-16 新加坡商星科金朋有限公司 半導體裝置和形成對於屏蔽層具有增強接觸之導電通孔的方法

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