TWI809797B - 可潤濕側面的封裝結構與其製作方法及垂直封裝模組 - Google Patents
可潤濕側面的封裝結構與其製作方法及垂直封裝模組 Download PDFInfo
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- TWI809797B TWI809797B TW111112537A TW111112537A TWI809797B TW I809797 B TWI809797 B TW I809797B TW 111112537 A TW111112537 A TW 111112537A TW 111112537 A TW111112537 A TW 111112537A TW I809797 B TWI809797 B TW I809797B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 165
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000011265 semifinished product Substances 0.000 claims description 106
- 230000017525 heat dissipation Effects 0.000 claims description 62
- 239000002184 metal Substances 0.000 claims description 38
- 229910000679 solder Inorganic materials 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 27
- 238000005538 encapsulation Methods 0.000 claims description 21
- 238000005520 cutting process Methods 0.000 claims description 11
- 238000009713 electroplating Methods 0.000 claims description 11
- 239000005022 packaging material Substances 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 239000000463 material Substances 0.000 description 19
- 230000008054 signal transmission Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 230000009286 beneficial effect Effects 0.000 description 12
- 238000013461 design Methods 0.000 description 9
- 230000005540 biological transmission Effects 0.000 description 8
- 230000006870 function Effects 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 8
- 239000000047 product Substances 0.000 description 8
- 238000012536 packaging technology Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 230000033228 biological regulation Effects 0.000 description 4
- 230000008595 infiltration Effects 0.000 description 4
- 238000001764 infiltration Methods 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000003672 processing method Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000003490 calendering Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009993 protective function Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H—ELECTRICITY
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4817—Conductive parts for containers, e.g. caps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
- H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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Abstract
本發明公開了一種可潤濕側面的封裝結構與其製作方法及垂直封裝模組,封裝結構包括第一介質層、晶片和線路層,第一介質層設置有封裝腔,第一介質層的側壁且位於封裝腔的外側設置有側壁焊盤,晶片封裝於封裝腔內,且晶片的引腳朝向第一介質層的第一面,線路層設置在第一介質層的第一面,線路層直接或間接連接於側壁焊盤和晶片的引腳。
Description
本發明涉及半導體封裝技術領域,特別涉及一種可潤濕側面的封裝結構與其製作方法及垂直封裝模組。
在半導體封裝技術中,無論是基於金屬凸塊(Bump,又稱為凸點)的凸點倒裝封裝技術,還是基於引腳的貼裝和插裝、引線鍵合等封裝技術,都需要通過在晶片上佈置金屬凸點或引線來作為與引線框架或IC基板相連的電性連接點。電信號在傳導過程中會因為傳輸距離加長、引線間存在寄生電感而導致出現高損耗和高延遲,而且會使封裝尺寸無法小型化。
球柵陣列(BGA)或者平面網格陣列(LGA)封裝技術是半導體封裝技術中常見的封裝技術,該技術主要在於它用金屬觸點式封裝取代了以往的針狀插腳,然而,一般很難從產品外觀來直接判斷其焊錫點,尤其是底部的焊錫點的性能是否良好,進而影響封裝產品在應用時的可靠性和穩定性。
隨著I/O數目的增加,引線鍵合的封裝方式已無法滿足封裝需求,面積一定的封裝結構同樣限制了基板上錫球的數目的增加,目前解決這種問題是通過在晶片上佈置再分佈線路層,用以增大間距來製造新的電接觸件,進而形成BGA或LGA的封裝體,但是這樣會導致產品良率的降低以及封裝成本的增加。而且,由於封裝體的焊盤位於封裝體的底部,器件只能通過表面貼裝的方式安裝在印刷垂直封裝模組上,器件散熱需要通過電路向下傳導或從器件背面主動散熱,無法應用於側面垂直裝配的場景,從而不能滿足特定半導體特殊器件的多方向的收發功能需求。
本發明旨在至少解決現有技術中存在的技術問題之一。為此,本發明提出一種可潤濕側面的封裝結構與其製作方法及垂直封裝模組,具有可焊錫浸潤的側壁焊盤,能夠通過晶片引腳引出線路層,取消鍵合引線或金屬凸點,縮小封裝體積和縮短電信號的傳導距離。
第一方面,根據本發明實施例的可潤濕側面的封裝結構,包括第一介質層,設置有封裝腔,所述第一介質層的側壁且位於所述封裝腔的外側設置有第一側壁焊盤;晶片,封裝於所述封裝腔內,且所述晶片的有源面的引腳朝向所述第一介質層的第一面;線路層,設置在所述第一介質層的第一面,所述線路層直接或間接連接於所述第一側壁焊盤和所述晶片的有源面上的引腳。
根據本發明實施例的封裝結構,至少具有如下有益效果:
與現有的封裝結構相比,本發明實施例設置有可潤濕焊錫的第一側壁焊盤,並通過晶片引腳引出線路層,取消鍵合引線或金屬凸點,縮小封裝體積和縮短電信號的傳導距離,有利於實現封裝結構的小型化,以及優化電信號傳導的損耗和延時。當第一側壁焊盤進行焊錫浸潤時,可以通過自動光學檢測設備檢查第一側壁焊盤的焊錫浸潤情況,從而判斷焊錫的品質狀況,進而得出晶片焊錫性能的有效性判斷,有利於提高相關電子產品裝配後的可靠性,可以滿足車規級的要求。
根據本發明的一些實施例,所述線路層直接與所述第一側壁焊盤連接或者通過第二導電通孔柱與所述第一側壁焊盤連接,所述線路層還直接與所述晶片的有源面上的引腳連接或者通過第一導電通孔柱與所述晶片的有源面上的引腳連接。
根據本發明的一些實施例,所述線路層的數量為多層,相鄰兩層所述線路層之間通過第三導電通孔柱連接。
根據本發明的一些實施例,所述第一介質層的第二面設置有散熱層,所述散熱層與所述晶片的散熱面直接連接或通過第一導熱通孔柱與所述晶片的散熱面連接。
根據本發明的一些實施例,所述線路層設置有底部焊盤,所述第一側壁焊盤和所述底部焊盤中的至少之一植有錫球。
根據本發明的一些實施例,所述晶片的有源面上設置有功能區,所述功能區露出所述第一介質層。
根據本發明的一些實施例,所述晶片的有源面上設置有透明色的第二表面保護層。
根據本發明的一些實施例,所述晶片的有源面上設置有非透明色的第二表面保護層,所述第二表面保護層上設置有與所述功能區對應的開窗位。
第二方面,根據本發明實施例的封裝結構的製作方法,包括:
提供一介質框架,所述介質框架上設置有至少一個封裝腔,所述介質框架上且位於所述封裝腔的外側設置有第一金屬柱,所述第一金屬柱的兩個端面分別暴露於所述介質框架的相對兩面;
將待封裝的晶片封裝在所述封裝腔內,以獲得第一半成品,其中,所述晶片的有源面上的引腳朝向所述第一半成品的第一面;
在所述第一半成品的第一面製作線路層,以獲得第二半成品,其中,所述線路層直接或間接連接於所述第一金屬柱和所述晶片的有源面上的引腳;
對所述第二半成品進行切割,以獲得具有第一側壁焊盤的封裝單元,其中,至少一條切割路徑經過所述第一金屬柱。
根據本發明實施例的封裝結構的製作方法,至少具有如下有益效果:
通過本發明實施例的封裝結構的製作方法,可以獲得一種封裝結構,與現有的封裝結構相比,本發明實施例製作出可潤濕焊錫的第一側壁焊盤,並通過晶片引腳引出線路層,取消鍵合引線或金屬凸點,縮小封裝體積和縮短電信號的傳導距離,有利於實現封裝結構的小型化,以及優化電信號傳導的損耗和延時。當第一側壁焊盤進行焊錫浸潤時,可以通過自動光學檢測設備檢查第一側壁焊盤的焊錫浸潤情況,從而判斷焊錫的品質狀況,進而得出晶片焊錫性能的有效性判斷,有利於提高相關電子產品裝配後的可靠性,可以滿足車規級的要求。
根據本發明的一些實施例,在所述第一半成品的第一面製作線路層,包括步驟:
當所述晶片的有源面上的引腳朝向且暴露於所述第一半成品的第一面時,在所述第一半成品的第一面製作所述線路層,以獲得所述第二半成品,其中,所述線路層與所述晶片的有源面上的引腳直接連接。
根據本發明的一些實施例,在所述第一半成品的第一面製作線路層,包括步驟:
當所述晶片的有源面上的引腳朝向所述第一半成品的第一面且埋藏於所述第一半成品內時,在所述第一半成品的第一面開設第一導通孔,所述第一導通孔連通於所述晶片的有源面上的引腳;
通過電鍍的方式在所述第一導通孔內加工出第一導電通孔柱,其中,所述第一導電通孔柱的第一端與所述晶片的有源面上的引腳連接,所述第一導電通孔柱的第二端暴露於所述第一半成品的第一面;
在所述第一半成品的第一面製作所述線路層,以獲得所述第二半成品,其中,所述線路層與所述第一導電通孔柱連接,並通過所述第一導電通孔柱與所述晶片的有源面上的引腳連接。
根據本發明的一些實施例,所述線路層的數量為多層,相鄰兩層所述線路層之間通過第三導電通孔柱連接,最外層的所述線路層通過第四導電通孔柱與所述第一金屬柱連接。
根據本發明的一些實施例,在所述第一半成品的第一面製作線路層,包括步驟:
當所述晶片的有源面上的引腳朝向所述第一半成品的第一面且所述晶片的散熱面埋藏於所述第一半成品內時,在所述第一半成品的第二面開設第二導通孔,所述第二導通孔連通於所述晶片的散熱面;
通過電鍍的方式在所述第二導通孔內加工出第一導熱通孔柱,其中,所述第一導熱通孔柱的第一端與所述晶片的散熱面連接,所述第一導熱通孔柱的第二端暴露於所述第一半成品的第二面;
在所述第一半成品的第一面製作所述線路層,在所述第一半成品的第二面製作散熱層,以獲得所述第二半成品,其中,所述散熱層與所述第一導熱通孔柱連接。
根據本發明的一些實施例,在所述第一半成品的第一面製作線路層,包括步驟:
當所述晶片的有源面上的引腳朝向所述第一半成品的第一面且所述晶片的散熱面暴露於所述第一半成品的第二面時,在所述第一半成品的第一面製作所述線路層,在所述第一半成品的第二面製作散熱層,以獲得所述第二半成品,其中,所述散熱層與所述晶片的散熱面直接連接。
根據本發明的一些實施例,所述晶片的有源面設置有功能區,將待封裝的晶片封裝在所述封裝腔內,包括步驟:
在所述封裝腔的底部提供一臨時承載面;
將所述晶片貼裝在所述封裝腔內,且所述晶片的有源面貼裝在所述臨時承載面上;
採用封裝材料對所述晶片進行封裝;
去除所述臨時承載面,以露出所述晶片的有源面上的功能區。
根據本發明的一些實施例,對所述第二半成品進行切割,之後還包括步驟:
在所述晶片的有源面上加工透明色的第二表面保護層。
根據本發明的一些實施例,對所述第二半成品進行切割,之後還包括步驟:
在所述晶片的有源面上加工非透明色的第二表面保護層;
在所述第二表面保護層上且對應於所述功能區的位置開窗。
第三方面,根據本發明實施例的封裝結構,通過第二方面所述的封裝結構的製作方法獲得。
第四方面,根據本發明實施例的垂直封裝模組,包括第一方面所述的封裝結構,或者,包括第三方面所述的封裝結構。
第五方面,根據本發明實施例的垂直封裝模組,包括:印刷線路板;封裝單元,設置有第二側壁焊盤,並通過所述第二側壁焊盤焊接在所述印刷線路板上,所述封裝單元的第一面垂直於所述印刷線路板;具有功能區域的封裝器件,封裝在所述封裝單元內且與所述第二側壁焊盤電性連接,所述封裝器件的功能區域朝向所述封裝單元的第一面。
根據本發明實施例的垂直封裝模組,至少具有如下有益效果:
本發明通過在封裝單元上設置第二側壁焊盤,將平面的表面貼裝方式改為垂直貼裝方式,縮小貼裝面積,有利於垂直封裝模組的小型化和高密度化,而且垂直貼裝的方式,可以使封裝器件對光、電磁波、紅外線等信號的發射、傳導、接收或探測方向從單一方向變成多個可選方向,有利於實現信號收發等相關功能,還有利於降低垂直封裝模組的設計難度,以及降低垂直裝配的工藝難度,並提高板級裝配的可靠性。
根據本發明的一些實施例,所述印刷線路板的表面或側邊設置有凹位,所述凹位內設置有第一焊盤,所述第二側壁焊盤與所述第一焊盤焊接連接。
根據本發明的一些實施例,所述印刷線路板的上表面或下表面設置有凸起部。
根據本發明的一些實施例,所述凸起部上設置有第二焊盤,所述封裝單元還設置有底部焊盤,所述底部焊盤與所述第二焊盤焊接連接。
本發明的附加方面和優點將在下面的描述中部分給出,部分將從下面的描述中變得明顯,或通過本發明的實踐瞭解到。
下面詳細描述本發明的實施例,所述實施例的示例在附圖中示出,其中自始至終相同或類似的標號表示相同或類似的元件或具有相同或類似功能的元件。下面通過參考附圖描述的實施例是示例性的,僅用於解釋本發明,而不能理解為對本發明的限制。
在本發明的描述中,若干的含義是一個或者多個,多個的含義是兩個以上,大於、小於、超過等理解為不包括本數,以上、以下、以內等理解為包括本數。如果有描述到第一、第二只是用於區分技術特徵為目的,而不能理解為指示或暗示相對重要性或者隱含指明所指示的技術特徵的數量或者隱含指明所指示的技術特徵的先後關係。
本發明的描述中,除非另有明確的限定,設置、安裝、連接等詞語應做廣義理解,所屬技術領域技術人員可以結合技術方案的具體內容合理確定上述詞語在本發明中的具體含義。
實施例1
請參照圖1和圖2,本實施例公開了一種可潤濕側面的封裝結構,包括第一介質層110、晶片200(又稱為微電路、微晶片或積體電路)和線路層300,第一介質層110的材料為玻璃纖維布、高分子聚合物或陶瓷材料中的至少一種,第一介質層110設置有封裝腔101,具體的,封裝腔101位於第一介質層110的中部,第一介質層110的側壁且位於封裝腔101的外側設置有第一側壁焊盤120,第一側壁焊盤120的數量根據晶片200的有源面上的引腳201數量以及實際的佈線需求而定,晶片200封裝於封裝腔101內,且晶片200的有源面上的引腳201朝向第一介質層110的第一面,其中,用於封裝晶片200的封裝材料103可以是味之素增層材料、具有聚合物基質的材料、感光性絕緣材料、封裝模塑膠或聚醯亞胺等,封裝材料103將晶片200包裹在封裝腔101內且晶片200部分露出封裝材料103,以便於實現電連接或散熱連接。請參照圖1、圖3和圖4,線路層300設置在第一介質層110的第一面,線路層300直接或間接連接於第一側壁焊盤120和晶片200的有源面上的引腳201,用以實現第一側壁焊盤120與晶片200的有源面上的引腳201之間的電性連接。值得理解的是,引腳201可以朝向第一介質層110的兩個相對表面中的任意一個,為了便於敘述,本發明實施例以引腳201的朝向為基準,確定第一介質層110的第一面,即第一介質層110以引腳201朝向的一面為第一面。
與現有的封裝結構相比,本發明實施例通過晶片200引腳引出線路層300,取消鍵合引線或金屬凸點,縮小封裝體積和縮短電信號的傳導距離,有利於實現封裝結構的小型化,以及優化電信號傳導的損耗和延時。而且,本實施例通過設置第一側壁焊盤120,可以在單位面積的封裝結構上佈置更多的焊盤,從而滿足不斷增加的I/O數量的需求。第一側壁焊盤120的設計可以實現封裝結構的表面貼裝、側面貼裝或垂直貼裝,可以滿足更多場景的貼裝需求,有利於提高封裝結構的適用性。在後續的使用中,當第一側壁焊盤120進行焊錫浸潤時,可以通過自動光學檢測設備檢查第一側壁焊盤120的焊錫浸潤情況,從而判斷焊錫的品質狀況,進而得出晶片焊錫性能的有效性判斷,有利於提高相關電子產品裝配後的可靠性,可以滿足車規級的要求。
根據不同設計,線路層300與第一側壁焊盤120和晶片200的有源面上的引腳201之間的連接方式均可以是直接連接或間接連接,其中,請參照圖1或圖3,圖中示出了線路層300分別與第一側壁焊盤120和晶片200的有源面上的引腳201直接連接;請參照圖4,圖中示出了線路層300與第一側壁焊盤120直接連接,以及線路層300通過第一導電通孔柱301與晶片200的有源面上的引腳201連接;請參照圖5,圖中示出了線路層300通過第二導電通孔柱302與第一側壁焊盤120連接,以及線路層300通過第一導電通孔柱301與晶片200的有源面上的引腳201連接。因此,本實施例可以實現線路層300直接與第一側壁焊盤120連接或者通過第二導電通孔柱302與第一側壁焊盤120連接,線路層300還直接與晶片200的有源面上的引腳201連接或者通過第一導電通孔柱301與晶片200的有源面上的引腳201連接。
請參照圖5、圖6和圖7,線路層300的數量為一層或多層,可以滿足更多的佈線需求。當線路層300的數量為多層時,相鄰兩層線路層300之間通過第三導電通孔柱303連接,最外層的線路層300通過第四導電通孔柱304與第一側壁焊盤120連接。
請參照圖5或圖7,第一介質層110的第二面設置有散熱層400,有利於提高晶片200的散熱效率,降低晶片200的工作溫度,從而提高晶片200工作的可靠性。其中,散熱層400與晶片200的散熱面直接連接或通過第一導熱通孔柱401與晶片200的散熱面連接。具體的,請參照圖5,圖中示出了散熱層400與晶片200的散熱面直接連接;請參照圖7,圖中示出了散熱層400通過第一導熱通孔柱401與晶片200的散熱面連接。
請繼續參照圖5或圖7,在應用時,第一側壁焊盤120上植有錫球600,或者在電路板上印刷錫膏,以便於與電路板連接。當然,對於部分封裝結構,線路層300設置有底部焊盤,根據實際的焊接需求,第一側壁焊盤120和底部焊盤中的至少之一植有錫球600,以便於實現表面貼裝、側面貼裝或垂直貼裝。
需要說明的是,為了對封裝結構進行保護,封裝結構上施加有第一表面保護層510,具體的,第一表面保護層510覆蓋於線路層300,當設置有散熱層400時,第一表面保護層510還覆蓋於散熱層400。第一表面保護層510可以是阻焊層或塑封層,用以實現機械保護和隔離水汽的功能。
請參照圖8a,在實際應用中,根據晶片200的不同選型,晶片200的有源面的朝向有所不同。例如,當晶片200為LED、光接收器件或感測器晶片等元件時,晶片200的有源面上設置有功能區202,功能區202露出第一介質層110,即晶片200的有源面朝向封裝腔101的外側,以便於完成信號發射、信號接收、信號傳導或信號探測等功能。
請參照圖8b,對於部分類型的晶片200,例如具有防水要求的晶片200,為了加強對晶片200的保護,晶片200的有源面上設置有透明色的第二表面保護層520。根據第二表面保護層520的材料不同,第二表面保護層520可以起到不同的保護作用,例如起到機械保護和隔離水汽的作用。
當然,請參照圖8c,根據第二表面保護層520材料的不同,晶片200的有源面上可以設置非透明色的第二表面保護層520,第二表面保護層520上設置有與功能區202對應的開窗位,用以避讓功能區202,從而露出功能區202,以便於完成信號發射、信號接收、信號傳導或信號探測等功能。
實施例2
本發明實施例提供一種封裝結構的製作方法,包括步驟S100、步驟S200、步驟S300和步驟S400,下面對各個步驟進行詳細說明。
步驟S100、請參照圖9和圖10,提供一介質框架100,介質框架100用於形成封裝結構的第一介質層110。介質框架100上設置有至少一個封裝腔101,介質框架100上且位於封裝腔101的外側設置有第一金屬柱102,第一金屬柱102的兩個端面分別暴露於介質框架100的相對兩面。本實施例中,封裝腔101為連通於介質框架100相對兩面的空腔,介質框架100的材料為玻璃纖維布、高分子聚合物或陶瓷材料中的至少一種。為了便於敘述,本實施例的介質框架100上陣列設置有4*3=12個封裝腔101,在同一行中,介質框架100上且位於相鄰的封裝腔101之間設置有第一金屬柱102,而且介質框架100的兩側壁且位於封裝腔101的一側同樣設置有第一金屬柱102。
步驟S200、請參照圖11,將待封裝的晶片200封裝在封裝腔101內,以獲得第一半成品,其中,晶片200的有源面上的引腳201朝向第一半成品的第一面。晶片200的封裝方式可以通過層壓、注塑成型或壓延工藝等方式完成,其中,用於封裝晶片200的封裝材料103可以是味之素增層材料、具有聚合物基質的材料、感光性絕緣材料、封裝模塑膠或聚醯亞胺等,封裝材料103將晶片200包裹在封裝腔101內且晶片200部分露出封裝材料103,以便於實現電連接或散熱連接。
步驟S300、請參照圖12,在第一半成品的第一面製作線路層300,以獲得第二半成品,其中,線路層300直接或間接連接於第一金屬柱102和晶片200的有源面上的引腳201,從而實現第一金屬柱102和晶片200的有源面上的引腳201之間的電性連接。與現有的封裝結構相比,本發明實施例通過晶片200引腳引出線路層300,取消鍵合引線或金屬凸點,縮小封裝體積和縮短電信號的傳導距離,有利於實現封裝結構的小型化,以及優化電信號傳導的損耗和延時。
步驟S400、請繼續參照圖12,對第二半成品進行切割,以獲得具有第一側壁焊盤120的封裝單元,其中,至少一條切割路徑經過第一金屬柱102,切割的方式可以是鐳射切割或機械切割。對於同一行上相鄰的兩個封裝腔101,將位於同一列的第一金屬柱102的中心連線(如圖中的虛線所示)確定為切割路徑,沿著切割路徑進行切割,可以使第一金屬柱102的剖面暴露於介質框架100的表面,以形成第一側壁焊盤120,然後對經過一次切割的半成品進行二次等分切割,以獲得封裝單元。第一側壁焊盤120的設計使封裝結構可以在單位面積上佈置更多的焊盤,從而滿足不斷增加的I/O數量的需求。第一側壁焊盤120的設計可以實現封裝結構的表面貼裝、側面貼裝或垂直貼裝,可以滿足更多場景的貼裝需求,有利於提高封裝結構的適用性。
對於步驟S300中在第一半成品的第一面製作線路層300的這一步驟,本實施例公開了兩種實施方式。其一,在第一半成品的第一面製作線路層300,包括步驟:
步驟S310、請參照圖11和圖12,當晶片200的有源面上的引腳201朝向且暴露於第一半成品的第一面時,在第一半成品的第一面製作線路層300,以獲得第二半成品,其中,線路層300與晶片200的有源面上的引腳201直接連接。值得理解的是,在晶片200的貼裝的過程中可以通過在封裝腔101的底部提供臨時承載面的方式來使晶片200的有源面上的引腳201朝向且暴露於第一半成品的第一面。另外,線路層300的製作方法可以通過圖形轉移和圖形電鍍的方式實現,對於本領域技術人員來說是公知的技術,本實施例不再進行累述。
其二,在第一半成品的第一面製作線路層300,包括步驟:
步驟S321、請參照圖13和圖14,當晶片200的有源面上的引腳201朝向第一半成品的第一面且埋藏於第一半成品內時,在第一半成品的第一面開設第一導通孔104,第一導通孔104連通於晶片200的有源面上的引腳201。在本實施例中,第一導通孔104通過鐳射鑽孔的方式加工得到。
步驟S322、請參照圖15,通過電鍍的方式在第一導通孔104內加工出第一導電通孔柱301,其中,第一導電通孔柱301的第一端與晶片200的有源面上的引腳201連接,第一導電通孔柱301的第二端暴露於第一半成品的第一面。
步驟S323、請繼續參照圖15,在第一半成品的第一面製作線路層300,以獲得第二半成品,其中,線路層300與第一導電通孔柱301連接,並通過第一導電通孔柱301與晶片200的有源面上的引腳201連接。通過如此設置,可以將晶片200的有源面上的引腳201封裝在封裝材料103中,還可以實現晶片200與第一金屬柱102的電性連接,有利於降低水氣對晶片200的影響,提高晶片200工作的穩定性。
需要說明的是,當封裝材料103的厚度較厚時,請參照圖14,在步驟S321中,第一導通孔104的數量為多個,多個第一導通孔104對應連通於第一金屬柱102和晶片200的有源面上的引腳201;相應的,請參照圖15,在步驟S322中,通過電鍍的方式在對應的第一導通孔104內分別加工出第二導電通孔柱302和第一導電通孔柱301,其中,第二導電通孔柱302的第一端與第一金屬柱102連接,第一導電通孔柱301的第一端與晶片200的有源面上的引腳201連接,第二導電通孔柱302的第二端和第一導電通孔柱301的第二端均暴露於第一半成品的第一面;在步驟S323中,在第一半成品的第一面製作線路層300後,線路層300分別與第二導電通孔柱302和第一導電通孔柱301連接,從而實現線路層300通過第二導電通孔柱302與第一金屬柱102連接,線路層300通過第一導電通孔柱301與晶片200的有源面上的引腳201連接,進而實現線路層300分別與第一金屬柱102和晶片200的有源面上的引腳201間接連接。
請參照圖16,在本實施例中,線路層300的數量為多層,相鄰兩層線路層300之間通過第三導電通孔柱303連接,最外層的線路層300通過第四導電通孔柱304與第一金屬柱102連接。其中,多層線路層300的加工方法可以通過圖形轉移、圖形電鍍、疊層和壓合等工序實現,同樣的,第三導電通孔柱303和第四導電通孔柱304的加工方法也可以通過圖形轉移、圖形電鍍、疊層和壓合等工序實現,對於本領域技術人員來說是公知的技術,本實施例不再累述。通過如此設置,本實施例可以製作出具有多層扇出的封裝結構,有利於提高佈線密度。
為了提高晶片200的散熱效率,可以在第一半成品上加工散熱層400,其中,散熱層400可以在步驟S300中同步製作,其中,本實施例提供兩種實施方式。
其一,在上述步驟S300中,在第一半成品的第一面製作線路層300,包括步驟:
請參照圖17,當晶片200的有源面上的引腳201朝向第一半成品的第一面且晶片200的散熱面埋藏於第一半成品內時,在第一半成品的第二面開設第二導通孔105,第二導通孔105連通於晶片200的散熱面。本實施例中,晶片200的散熱面位於晶片200的背面,晶片200的散熱面與晶片200的有源面上的引腳201分別位於晶片200的相對兩面。
請參照圖18,通過電鍍的方式在第二導通孔105內加工出第一導熱通孔柱401,其中,第一導熱通孔柱401的第一端與晶片200的散熱面連接,第一導熱通孔柱401的第二端暴露於第一半成品的第二面。
請繼續參照圖18,在第一半成品的第一面製作線路層300,在第一半成品的第二面製作散熱層400,以獲得第二半成品,其中,散熱層400與第一導熱通孔柱401連接。散熱層400的製作方法可通過圖形轉移和圖像電鍍的方式實現,本實施例不在累述。
其二,在上述步驟S300中,在第一半成品的第一面製作線路層300,包括步驟:
請參照圖14和圖15,當晶片200的有源面上的引腳201朝向第一半成品的第一面且晶片200的散熱面暴露於第一半成品的第二面時,在第一半成品的第一面製作線路層300,在第一半成品的第二面製作散熱層400,以獲得第二半成品,其中,散熱層400與晶片200的散熱面直接連接。線路層300的製作方法可參照上述的實施方式,不在此累述。
上述步驟S300、在第一半成品的第一面製作線路層300,之後還包括步驟:
請參照圖19或圖20,在第一半成品上施加第一表面保護層510,以獲得第二半成品,第一表面保護層510可以是阻焊層或塑封層,用以實現機械保護和隔離水氣的功能。當加工有散熱層400時,通過圖形轉移工藝、等離子蝕刻或鐳射工藝對第一表面保護層510進行局部去除,以暴露出對應的散熱金屬。其中,第一表面保護層510的塑封材料可以為封裝材料103。
請繼續參照圖19或圖20,在獲得封裝單元後,可以對第一側壁焊盤120進行植球處理,用以在第一側壁焊盤120加工出連接結構。需要說明的是,對於部分封裝結構,線路層300設置有底部焊盤,第一表面保護層510設置有用於露出底部焊盤的開窗位,此時,可以對第一側壁焊盤120和底部焊盤進行植球處理,用以在第一側壁焊盤120和底部焊盤上加工出連接結構。
在實際應用中,根據晶片200的不同選型,晶片200的有源面的朝向有所不同。例如,當晶片200為LED、光接收器件或感測器晶片等元件時,晶片200的有源面設置有功能區202。
為了使功能區202露出第一介質層110,在上述步驟S200中,將待封裝的晶片200封裝在封裝腔101內,包括步驟:
步驟S210、在封裝腔101的底部提供一臨時承載面(未圖示),其中,臨時承載面可以是設置在介質框架100底部的臨時承載板,或者,臨時承載面可以是黏貼在介質框架100底部的膠紙或膠帶。
步驟S220、將晶片200貼裝在封裝腔101內,且晶片200的有源面貼裝在臨時承載面上,可以使晶片200的有源面與介質框架100的底部齊平,即與第一介質層110的表面齊平。
步驟S230、採用封裝材料103對晶片200進行封裝。由於晶片200的有源面貼裝在臨時承載面上,在封裝時,封裝材料103可以對晶片200的有源面進行避讓,避免封裝材料103對晶片200進行全覆蓋。
步驟S240、去除臨時承載面,以露出晶片200的有源面上的功能區202。由於晶片200的有源面貼裝在臨時承載面上,當去除臨時承載面後,可以暴露出晶片200的有源面,封裝後的結構可參照圖8a。當然,當晶片200的有源面上設置有引腳201時,也可以實現引腳201露出第一介質層110。為了對晶片200進行保護,在上述步驟S400中,對第二半成品進行切割,之後還包括步驟:
步驟S520、在晶片200的有源面上加工透明色的第二表面保護層520,其結構可參照圖8b。
在上述步驟S400中,根據第二表面保護層520的材料不同,第二表面保護層520的加工方式有所不同。例如,對第二半成品進行切割,之後還包括步驟:
步驟S521、在晶片200的有源面上加工非透明色的第二表面保護層520;
步驟S522、在第二表面保護層520上且對應於功能區202的位置開窗,其結構可參照圖8c,可以對功能區202進行避讓,從而露出功能區202,以便於完成信號發射、信號接收、信號傳導或信號探測等功能。
實施例3
本發明實施例公開一種封裝結構,通過實施例2的封裝結構的製作方法獲得。與現有的封裝結構相比,本發明實施例通過晶片200的引腳201引出線路層300,取消鍵合引線或金屬凸點,縮小封裝體積和縮短電信號的傳導距離,有利於實現封裝結構的小型化,以及優化電信號傳導的損耗和延時。而且,本實施例通過設置第一側壁焊盤120,可以在單位面積的封裝結構上佈置更多的焊盤,從而滿足不斷增加的I/O數量的需求。第一側壁焊盤120的設計可以實現封裝結構的表面貼裝、側面貼裝或垂直貼裝,可以滿足更多場景的貼裝需求,有利於提高封裝結構的適用性。在後續的使用中,當第一側壁焊盤120進行焊錫浸潤時,可以通過自動光學檢測設備檢查第一側壁焊盤120的焊錫浸潤情況,從而判斷焊錫的品質狀況,進而得出晶片焊錫性能的有效性判斷,有利於提高相關電子產品裝配後的可靠性,可以滿足車規級的要求。
實施例4
本發明實施例公開一種垂直封裝模組,包括實施例1的封裝結構,或者,包括實施例3的封裝結構。本發明實施例通過晶片200的有源面上的引腳201引出線路層300,取消鍵合引線或金屬凸點,縮小封裝體積和縮短電信號的傳導距離,有利於實現封裝結構的小型化,以及優化電信號傳導的損耗和延時。而且,本實施例通過設置第一側壁焊盤120,可以在單位面積的封裝結構上佈置更多的焊盤,從而滿足不斷增加的I/O數量的需求。第一側壁焊盤120的設計可以實現封裝結構的表面貼裝、側面貼裝或垂直貼裝,可以滿足更多場景的貼裝需求,有利於提高封裝結構的適用性。
實施例5
請參照圖21,發明實施例公開一種垂直封裝模組,包括印刷線路板700、封裝單元800和封裝器件810,封裝單元800設置有第二側壁焊盤820,並通過第二側壁焊盤820焊接在印刷線路板700上,封裝單元800的第一面垂直於印刷線路板700,封裝器件810具有功能區域811,其中,功能區域811對應於實施例1的功能區202,即功能區域811可以是信號發射端、信號接收端、信號傳導端或信號探測端,當然,功能區域811還可以是集成了信號發射端和信號接收端的信號收發端。功能區域811暴露在空氣中,也可以通過覆蓋保護材料進行保護。封裝器件810封裝在封裝單元800內且與第二側壁焊盤820電性連接,封裝器件810的功能區域811朝向封裝單元800的第一面,如此可以實現封裝器件810的信號傳導方向平行或實質平行於印刷線路板700所在的虛擬平面。值得理解的是,功能區域811可以朝向封裝單元800的兩個相對表面中的任意一個,為了便於敘述,本發明實施例以功能區域811的朝向為基準,確定封裝單元800的第一面,即封裝單元800以功能區域811朝向的一面為第一面。需要說明的是,本實施例涉及的「信號傳導方向」是指封裝器件810發出或接收的信號(如光信號)沿某一虛擬的直線路徑傳導,該直線路徑的指向即為信號傳導方向。本實施例涉及的「實質平行」是指封裝器件810的信號傳導方向與印刷線路板700所在的虛擬平面之間的夾角在一定的誤差範圍內,例如≤3°或≤5°。本實施例的封裝單元800垂直裝配在印刷線路板700上,可以為封裝器件810提供一種正面、背面和側面同時主動散熱的垂直裝配結構,有利於提高封裝器件810的散熱效率。
為了避免重複累述,本實施例的封裝單元800的具體結構可參照實施例1,例如,通過封裝器件810的引腳201引出線路層,取消鍵合引線或金屬凸點,縮小封裝體積和縮短電信號的傳導距離,有利於實現封裝結構的小型化,以及優化電信號傳導的損耗和延時;又例如,封裝單元800上設置有散熱層400,散熱層400與封裝器件810直接或間接連接,用以提高封裝器件810的散熱效率。本實施例的垂直裝配結構,可以將設置在封裝器件810正面或背面的散熱層400暴露在空氣中,後續可通過風冷或水冷等方式進行主動散熱,有利於提高散熱效率,其中,在本實施例中,封裝器件810可以是LED、光接收器件或感測器晶片等。應當理解的是,印刷線路板700內部或表面設置有走線710和/或焊盤,印刷線路板700上還可以貼裝其它元器件,例如,有源器件720(如晶片或開關管等)和無源器件730(如電阻或電容等),元器件之間通過走線710連接。當封裝器件810為光收發器件,而有源器件720為光收發器件的驅動控制晶片(ASIC)時,可以實現光收發器件及其ASIC的集成。
對於常規的封裝有封裝器件810的封裝單元800,封裝器件810的功能區域811一般朝向於封裝單元800的正面,而封裝單元800的焊盤一般佈置在底部,因此,當封裝單元800通過表面貼裝技術貼裝在印刷線路板上後,封裝器件810的信號傳導方向只能垂直於印刷線路板所在的虛構平面,導致封裝器件810的信號傳導方向單一;而且由於結構設計以及生產工藝等原因,封裝單元800一般為長方體結構,通常面積較大的一面與印刷線路板連接,導致貼裝面積大。
本實施例通過在封裝單元800上設置第二側壁焊盤820,將平面的表面貼裝方式改為垂直貼裝方式,縮小貼裝面積,有利於垂直封裝模組的小型化和高密度化,而且垂直貼裝的方式,可以使封裝器件810對光、電磁波、紅外線等信號的發射、傳導、接收或探測方向從單一方向變成多個可選方向,例如請參照圖22a、圖22b、圖22c和圖22d,圖中分別示出了6個、4個、3個和2個封裝單元800的排列情況,圖中虛線表示信號傳導方向,信號傳導方向與印刷線路板700所在的虛構平面平行,通過調整封裝單元800的數量以及貼裝的朝向,可以實現多個朝向的貼裝陣列(如LED陣列或天線陣列),有利於實現信號收發等相關功能,還有利於降低垂直封裝模組的設計難度以及降低垂直裝配的工藝難度,並提高板級裝配的可靠性。
請參照圖21或圖23,印刷線路板700的表面或側邊設置有凹位701,凹位701內設置有第一焊盤702,第二側壁焊盤820與第一焊盤702焊接連接。例如,請參照圖21,圖示的凹位701為凹槽結構,第一焊盤702設置在凹槽內,封裝單元800貼裝後,通過液體填充劑填埋凹槽內的空隙,並通過熱固化或光固化的方式將填充劑固化,用於提高封裝單元800貼裝的穩固性;又例如,請參照圖23,圖示的凹位701為設置在印刷線路板700邊緣的缺角凹位,第一焊盤702設置在缺角凹位內,其中,第一焊盤702為平面焊盤或直角焊盤。當第一焊盤702為直角焊盤時,封裝單元800還設置有底部焊盤,封裝單元800的第二側壁焊盤820和底部焊盤分別與直角焊盤焊接連接,用以提高封裝單元800的貼裝穩固性。
請參照圖24,印刷線路板700的表面設置有凸起部703,其中,凸起部703可以是立柱、凸台或豎牆等結構,凸起部703的側壁設置有第二焊盤704,封裝單元800還設置有底部焊盤,底部焊盤與第二焊盤704焊接連接。如此,通過第二側壁焊盤820與第一焊盤702焊接連接,以及通過底部焊盤與第二焊盤704焊接連接,可以提高封裝單元800的貼裝穩固性,還可以充分利用立體空間來增大佈線面積,有利於增大元器件的集成密度。值得理解的是,凸起部703有多個側壁,根據設計佈局需求,可以在凸起部703的一個或多個側壁上設置第二焊盤704,用以貼裝一個或多個封裝單元800。
上面結合附圖對本發明實施例作了詳細說明,但是本發明不限於上述實施例,在所屬技術領域普通技術人員所具備的知識範圍內,還可以在不脫離本發明宗旨的前提下作出各種變化。
100:介質框架
101:封裝腔
102:第一金屬柱
103:封裝材料
104:第一導通孔
105:第二導通孔
110:第一介質層
120:第一側壁焊盤
200:晶片
201:引腳
202:功能區
300:線路層
301:第一導電通孔柱
302:第二導電通孔柱
303:第三導電通孔柱
304:第四導電通孔柱
400:散熱層
401:第一導熱通孔柱
510:第一表面保護層
520:第二表面保護層
600:錫球
700:印刷線路板
701:凹位
702:第一焊盤
703:凸起部
704:第二焊盤
710:走線
720:有源器件
730:無源器件
800:封裝單元
810:封裝器件
811:功能區域
820:第二側壁焊盤
S100:步驟
S200:步驟
S210:步驟
S220:步驟
S230:步驟
S240:步驟
S300:步驟
S310:步驟
S321:步驟
S322:步驟
S323:步驟
S400:步驟
S520:步驟
S521:步驟
S522:步驟
本發明的上述和/或附加的方面和優點從結合下面附圖對實施例的描述中將變得明顯和容易理解,其中:
圖1為本發明實施例的封裝結構的結構示意圖之一。
圖2為圖1示出的封裝結構的仰視示意圖。
圖3為本發明實施例的封裝結構的結構示意圖之二。
圖4為本發明實施例的封裝結構的結構示意圖之三。
圖5為本發明實施例的封裝結構的結構示意圖之四。
圖6為本發明實施例的封裝結構的結構示意圖之五。
圖7為本發明實施例的封裝結構的結構示意圖之六。
圖8a為本發明實施例的封裝結構的結構示意圖之七。
圖8b為本發明實施例的封裝結構的結構示意圖之八。
圖8c為本發明實施例的封裝結構的結構示意圖之九。
圖9至圖20為本發明實施例的封裝結構的製作方法的中間過程示意圖。
圖21為本發明實施例的垂直封裝模組的結構示意圖之一。
圖22a、圖22b、圖22c、圖22d分別為本發明實施例的不同數量的封裝單元在印刷線路板上分佈的俯視圖。
圖23為本發明實施例的垂直封裝模組的結構示意圖之二。
圖24為本發明實施例的垂直封裝模組的結構示意圖之三。
101:封裝腔
103:封裝材料
110:第一介質層
120:第一側壁焊盤
200:晶片
201:引腳
300:線路層
510:第一表面保護層
600:錫球
Claims (21)
- 一種可潤濕側面的封裝結構,其中,包括:第一介質層,設置有封裝腔,所述第一介質層的側壁且位於所述封裝腔的外側設置有第一側壁焊盤;晶片,封裝於所述封裝腔內,且所述晶片的有源面的引腳朝向所述第一介質層的第一面;線路層,設置在所述第一介質層的第一面,所述線路層直接連接於所述第一側壁焊盤和所述晶片的有源面上的引腳。
- 如請求項1所述的可潤濕側面的封裝結構,其中,所述第一介質層的第二面設置有散熱層,所述散熱層與所述晶片的散熱面直接連接或通過第一導熱通孔柱與所述晶片的散熱面連接。
- 如請求項1或2所述的可潤濕側面的封裝結構,其中,所述線路層設置有底部焊盤,所述第一側壁焊盤和所述底部焊盤中的至少之一植有錫球。
- 如請求項1所述的可潤濕側面的封裝結構,其中,所述晶片的有源面上設置有功能區,所述功能區露出所述第一介質層。
- 如請求項4所述的可潤濕側面的封裝結構,其中,所述晶片的有源面上設置有透明色的第二表面保護層。
- 如請求項4所述的可潤濕側面的封裝結構,其中,所述晶片的有源面上設置有非透明色的第二表面保護層,所述第二表面保護層上設置有與所述功能區對應的開窗位。
- 一種封裝結構的製作方法,其中,包括:提供一介質框架,所述介質框架上設置有至少一個封裝腔,所述介質框架 上且位於所述封裝腔的外側設置有第一金屬柱,所述第一金屬柱的兩個端面分別暴露於所述介質框架的相對兩面;將待封裝的晶片封裝在所述封裝腔內,以獲得第一半成品,其中,所述晶片的有源面上的引腳朝向所述第一半成品的第一面;在所述第一半成品的第一面製作線路層,以獲得第二半成品,其中,所述線路層直接或間接連接於所述第一金屬柱和所述晶片的有源面上的引腳;對所述第二半成品進行切割,以獲得具有第一側壁焊盤的封裝單元,其中,至少一條切割路徑經過所述第一金屬柱。
- 如請求項7所述的封裝結構的製作方法,其中,在所述第一半成品的第一面製作線路層,包括步驟:當所述晶片的有源面上的引腳朝向且暴露於所述第一半成品的第一面時,在所述第一半成品的第一面製作所述線路層,以獲得所述第二半成品,其中,所述線路層與所述晶片的有源面上的引腳直接連接。
- 如請求項7所述的封裝結構的製作方法,其中,在所述第一半成品的第一面製作線路層,包括步驟:當所述晶片的有源面上的引腳朝向所述第一半成品的第一面且埋藏於所述第一半成品內時,在所述第一半成品的第一面開設第一導通孔,所述第一導通孔連通於所述晶片的有源面上的引腳;通過電鍍的方式在所述第一導通孔內加工出第一導電通孔柱,其中,所述第一導電通孔柱的第一端與所述晶片的有源面上的引腳連接,所述第一導電通孔柱的第二端暴露於所述第一半成品的第一面;在所述第一半成品的第一面製作所述線路層,以獲得所述第二半成品,其 中,所述線路層與所述第一導電通孔柱連接,並通過所述第一導電通孔柱與所述晶片的有源面上的引腳連接。
- 如請求項8或9所述的封裝結構的製作方法,其中,所述線路層的數量為多層,相鄰兩層所述線路層之間通過第三導電通孔柱連接,最外層的所述線路層通過第四導電通孔柱與所述第一金屬柱連接。
- 如請求項7所述的封裝結構的製作方法,其中,在所述第一半成品的第一面製作線路層,包括步驟:當所述晶片的有源面上的引腳朝向所述第一半成品的第一面且所述晶片的散熱面埋藏於所述第一半成品內時,在所述第一半成品的第二面開設第二導通孔,所述第二導通孔連通於所述晶片的散熱面;通過電鍍的方式在所述第二導通孔內加工出第一導熱通孔柱,其中,所述第一導熱通孔柱的第一端與所述晶片的散熱面連接,所述第一導熱通孔柱的第二端暴露於所述第一半成品的第二面;在所述第一半成品的第一面製作所述線路層,在所述第一半成品的第二面製作散熱層,以獲得所述第二半成品,其中,所述散熱層與所述第一導熱通孔柱連接。
- 如請求項7所述的封裝結構的製作方法,其中,在所述第一半成品的第一面製作線路層,包括步驟:當所述晶片的有源面上的引腳朝向所述第一半成品的第一面且所述晶片的散熱面暴露於所述第一半成品的第二面時,在所述第一半成品的第一面製作所述線路層,在所述第一半成品的第二面製作散熱層,以獲得所述第二半成品,其中,所述散熱層與所述晶片的散熱面直接連接。
- 如請求項7所述的封裝結構的製作方法,其中,所述晶片的有源面設置有功能區,將待封裝的晶片封裝在所述封裝腔內,包括步驟:在所述封裝腔的底部提供一臨時承載面;將所述晶片貼裝在所述封裝腔內,且所述晶片的有源面貼裝在所述臨時承載面上;採用封裝材料對所述晶片進行封裝;去除所述臨時承載面,以露出所述晶片的有源面上的功能區。
- 如請求項13所述的封裝結構的製作方法,其中,對所述第二半成品進行切割,之後還包括步驟:在所述晶片的有源面上加工透明色的第二表面保護層。
- 如請求項13所述的封裝結構的製作方法,其中,對所述第二半成品進行切割,之後還包括步驟:在所述晶片的有源面上加工非透明色的第二表面保護層;在所述第二表面保護層上且對應於所述功能區的位置開窗。
- 一種可潤濕側面的封裝結構,其中,通過請求項7至15中任一項所述的封裝結構的製作方法獲得。
- 一種垂直封裝模組,其中,包括請求項1至6中任一項所述的可潤濕側面的封裝結構,或者,包括請求項16所述的可潤濕側面的封裝結構。
- 一種垂直封裝模組,其中,包括:印刷線路板;封裝單元,在所述封裝單元的側壁設置有第二側壁焊盤,並通過所述第二側壁焊盤焊接在所述印刷線路板上,所述封裝單元的第一面垂直於所述印刷線 路板,且所述封裝單元的第一面設置有線路層;具有功能區域的封裝器件,封裝在所述封裝單元內,且所述封裝器件的有源面的引腳朝向所述封裝單元的第一面,並且,所述線路層直接連接於所述第二側壁焊盤和所述封裝器件的有源面的引腳,所述封裝器件的功能區域朝向所述封裝單元的第一面。
- 如請求項18所述的垂直封裝模組,其中,所述印刷線路板的表面或側邊設置有凹位,所述凹位內設置有第一焊盤,所述第二側壁焊盤與所述第一焊盤焊接連接。
- 如請求項18或19所述的垂直封裝模組,其中,所述印刷線路板的上表面或下表面設置有凸起部。
- 如請求項20所述的垂直封裝模組,其中,所述凸起部上設置有第二焊盤,所述封裝單元還設置有底部焊盤,所述底部焊盤與所述第二焊盤焊接連接。
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JP2022186602A (ja) | 2022-12-15 |
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