WO2024103312A1

WO2024103312A1 - Nitride-based semiconductor circuit and method for manufacturing the same

Info

Publication number: WO2024103312A1
Application number: PCT/CN2022/132359
Authority: WO
Inventors: Yifeng Zhu; Kai Cao; Bangxing CHEN
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-11-16
Filing date: 2022-11-16
Publication date: 2024-05-23
Also published as: CN118266085A

Abstract

A nitride-based semiconductor circuit includes a carrier, a nitride-based semiconductor die, and connecting clips. The nitride-based semiconductor circuit has first connecting surfaces, and the first connecting surfaces located around the carrier, and the connecting clips connect the nitride-based semiconductor die and the first connecting surface. The carrier has an accommodation hole. The nitride-based semiconductor die is disposed in the accommodation hole. Every connecting clip has a ground surface, and the ground surfaces are located at the top of the nitride-based semiconductor circuit, and the ground surfaces are located above the carrier and the nitride-based semiconductor die. The nitride-based semiconductor die has a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a 2DEG region.

Description

NITRIDE-BASED SEMICONDUCTOR CIRCUIT AND METHOD FOR MANUFACTURING THE SAME

Inventors: Yifeng ZHU; Kai CAO; Bangxing CHEN

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor circuit. More specifically, the present disclosure relates to a nitride-based semiconductor circuit having connecting clips to improve the electrical connection.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor circuit is provided. The nitride-based semiconductor circuit includes a carrier, a nitride-based semiconductor die, and a plurality of connecting clips. The nitride-based semiconductor circuit has a plurality of first connecting surfaces, and the first connecting surfaces located around the carrier, and the connecting clips connect the nitride-based semiconductor die and the first connecting surface. The carrier has an accommodation hole. The nitride-based semiconductor die is disposed in the accommodation hole. Every connecting clip has a ground surface, and the ground surfaces are located at the top of the nitride-based semiconductor circuit, and the ground surfaces are located above the carrier and the nitride-based semiconductor die. The nitride-based semiconductor die has a first nitride-based semiconductor layer and a second nitride-based semiconductor layer, and the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. A bandgap of the second nitride-based semiconductor layer is greater than a bandgap of the first nitride-based semiconductor layer, and a 2DEG region is formed near an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor circuit is provided. The method has steps as follows: providing a carrier having a plurality of accommodation holes and a plurality of connection holes; disposing a plurality of nitride-based semiconductor dies in the accommodation holes respectively; disposing a plurality of connecting clips in the connection holes and connect the connecting clips and the nitride-based semiconductor dies; encapsulating the connecting clips on the carrier with a second dielectric layer; grinding the second dielectric layer and expose a ground surface on every connecting clip; and dicing the carrier and separate the nitride-based semiconductor dies and expose a first connecting surface on every connecting clip. The ground surfaces are located at the top of the nitride-based semiconductor circuit, and the ground surfaces are located above the carrier and the nitride-based semiconductor die. Each of the nitride-based semiconductor dies has a first nitride-based semiconductor layer and a second nitride-based semiconductor layer, and the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. A bandgap of the second nitride-based semiconductor layer is greater than a bandgap of the first nitride-based semiconductor layer, and a 2DEG region is formed near an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor circuit is provided. The nitride-based semiconductor circuit includes a carrier, a nitride-based semiconductor die, and a plurality of connecting clips. The nitride-based semiconductor die is embedded in the carrier. The connecting clip has a ground surface and a first connecting surface. The connecting clips are electrically connected to the nitride-based semiconductor die. The first connecting surfaces are located at sides of the nitride-based semiconductor circuit, and the ground surfaces are located at a top of the nitride-based semiconductor circuit. The nitride-based semiconductor die has a first nitride-based semiconductor layer and a second nitride-based semiconductor layer, and the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. A bandgap of the second nitride-based semiconductor layer is greater than a bandgap of the first nitride-based semiconductor layer, and a 2DEG region is formed near an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer.

By the above configuration, the connecting clips connected to the nitride-based semiconductor die can dissipate heat through the ground surfaces, while the first connecting surfaces can form connection with the nitride-based semiconductor die through the connecting clips.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIGS. 2-10 are side sectional view of steps of a manufacturing method of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 11 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 12 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 13 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure; and

FIG. 14 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor circuits/devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a side sectional view of a nitride-based semiconductor circuit 1A according to some embodiments of the present disclosure. Referring to FIG. 1, the nitride-based semiconductor circuit 1A has a carrier 10, a nitride-based semiconductor die 11, and a plurality of connecting clips 12. The carrier 10 has an accommodation hole 100, and the nitride-based semiconductor die 11 is disposed in the accommodation hole 100. The connecting clips 12 are connected to the nitride-based semiconductor die 11. In other words, the nitride-based semiconductor die 11 is embedded in the carrier 10.

In this embodiment, the nitride-based semiconductor circuit 1A has a plurality of connecting surfaces 120, and the connecting surfaces 120 are located around the carrier 10. In other words, the connecting surfaces 120 are located at the sides of the nitride-based semiconductor circuit 1A. The connecting clips 12 connect the nitride-based semiconductor die 11 and the connecting surfaces 120. In other words, the connecting clips 12 have the connecting surfaces 120. Other devices can be electrically connected to the nitride-based semiconductor die 11 through the connecting surfaces 120 of the connecting clips 12.

In this embodiment, every connecting clip 12 has a ground surface 121, and the ground surfaces 121 are located at the top of the nitride-based semiconductor circuit 1A. The ground surfaces 121 of the connecting clips 12 are located above the carrier 10 and the nitride-based semiconductor die 11. Therefore, the ground surfaces 121 can dissipate heat from the nitride-based semiconductor die 11.

In this embodiment, the nitride-based semiconductor die 11 has a nitride-based semiconductor layer 110 and a nitride-based semiconductor layer 111. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110. A bandgap of the nitride-based semiconductor layer 111 is greater than a bandgap of the nitride-based semiconductor layer 110, and a 2DEG region is formed near an interface between the nitride-based semiconductor layer 110 and the nitride-based semiconductor layer 111. Therefore, a plurality of HEMTs are formed in the nitride-based semiconductor die 11.

Therefore, in this embodiment, the connecting clips 12 can form connection of the nitride-based semiconductor die 11, and the connecting clips 12 can redistribute connecting interfaces, and the connecting clips 12 can dissipate the heat generated from the nitride-based semiconductor die 11.

In this embodiment, the carrier 10 may comprise, for example, silicon. In some embodiments, the carrier 10 may comprise Al ₂O ₃, AlN, or any other materials with high thermal conductivity.

In one aspect, the nitride-based semiconductor die 11 in this embodiment has a plurality of HEMTs, and the nitride-based semiconductor layer 110 can form the tunnel layers of these HEMTs, and the nitride-based semiconductor layer 111 can form the barrier layers of these HEMTs. For example, the nitride-based semiconductor layer 110 may include gallium nitride (GaN) , and the nitride-based semiconductor layer 111 may include aluminum gallium nitride (AlGaN) .

To be specific, the exemplary materials of the nitride-based semiconductor layers 110, 111 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InAlN, In _xAl _yGa _(1-x-y) N where x+y ≦ 1, Al _yGa _(1-y) N where y ≦ 1.

The exemplary materials of the nitride-based semiconductor layers 110, 111 are selected such that the nitride-based semiconductor layer 111 has the bandgap (i.e., forbidden band width) greater than the bandgap of the nitride-based semiconductor layer 110, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. As such, the nitride-based semiconductor layers 110, 111 can serve as the channel layer and the barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating the two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

In this embodiment, the connecting clips 12 may comprise, for example, copper. In some embodiments, the connecting clips 12 may comprise other conductive materials.

Referring to FIG. 1, in this embodiment, a height of the nitride-based semiconductor die 11 and a depth of the accommodation hole 100 are the same. A dimension of the nitride-based semiconductor die 11 is corresponded to a dimension of the accommodation hole 100. Therefore, the carrier 10 can accommodate the nitride-based semiconductor die 11 properly. In other words, the accommodation hole 100 of the carrier 10 can be altered with the nitride-based semiconductor die 11, and nitride-based semiconductor die 11 with any dimension can be accommodated properly in the carrier 10. Also, the connecting clips 12 can lead the connection of the nitride-based semiconductor die 11 and provide accessible interfaces for connection.

To be specific, the nitride-based semiconductor die 11 includes a top surface 113 and a bottom surface 114. The top surface 113 and the bottom surface 114 are opposite, and the bottom surface 114 is connected to a bottom 1001 of the accommodation hole 100 of the carrier 10, and the top surface 113 is facing outward.

The nitride-based semiconductor die 11 has a plurality of connecting pads 112. The connecting pads 112 are embedded in the top surface 113. The top surface 113 expose the connecting pads 112, and the connecting clips 12 are electrically connected to the connecting pads 112. Therefore, the nitride-based semiconductor die 11 in the accommodation hole 100 of the carrier 10 can be electrically connected to other devices through the connecting clips 12 easily. Also, the heat generated by the nitride-based semiconductor die 11 can be dissipated by the connecting clips 12 efficiently.

In this embodiment, the carrier 10 has a top surface 101. The top surface 101 surrounds the top surface 113, and the top surface 101 and the top surface 113 are coplanar. Therefore, the connecting pads 112 embedded in the top surface 113 can be easily connected through the connecting clips 12.

In this embodiment, the nitride-based semiconductor circuit 1A comprises dielectric layer 13. The dielectric layer 13 covers the top surface 113 and part of the top surface 101 that is surrounding the top surface 113. The connecting pads 112 of the nitride-based semiconductor die 11 are free from the dielectric layer 13, and the dielectric layer 13 form a dielectric plane on the carrier 10 and the nitride-based semiconductor die 11. Therefore, the dielectric layer 13 provide a proper platform to form connection between the connecting pads 112 and the connecting clips 12.

Moreover, part of the dielectric layer 13 surrounds the nitride-based semiconductor die 11. A gap is formed between a side of the nitride-based semiconductor die 11 and the accommodation hole 100, and the dielectric layer 13 fills the gap between the nitride-based semiconductor die 11 and the accommodation hole 100. Therefore, the carrier 10 can hold the nitride-based semiconductor die 11 firmly, and the connection between the carrier 10 and the nitride-based semiconductor die 11 is solid.

In this embodiment, the nitride-based semiconductor circuit 1A comprises a plurality of conductive layers 14. The conductive layers 14 are disposed on the dielectric layer 13. Every conductive layer 14 is connected to one of the connecting pads 112, and the connecting clips 12 are electrically connected to the conductive layers 14. In other words, every conductive layer 14 connects one of the connecting pads 112 to one of the connecting clips 12.

The conductive layer 14 form a conductive surface on the carrier 10 and the nitride-based semiconductor die 11, and the connecting area of the conductive layer 14 is larger than the connecting area of the connecting pad 112. Therefore, the conductive layers 14 form sufficient interfaces for connection of the connecting clips 12, and the conductive layers 14 can reduce the resistance of the electrical connection between the connecting clips 12 and the connecting pads 112.

In this embodiment, the nitride-based semiconductor circuit 1A comprises a plurality of solder layers 15. Every solder layer 15 connects one of the conductive layers 14 and one of the connecting clips 12.

To be specific, every connecting clip 12 has a protrusion facing towards the conductive layer 14, and the solder layer 15 may fully cover the protrusion and form connection between the connecting clip 12 and the conductive layer 14. Therefore, the connection between the connecting clip 12 and the conductive layer 14 is solid, and the solder layer 15 and the conductive layer 14 may provide electrical connection with low resistance, so as to improve the transmission between the connecting clip 12 and the nitride-based semiconductor die 11. Also, the solder layer 15 covers large area on the connecting clip 12, and, therefore; heat generated from the nitride-based semiconductor die 11 can be transmitted efficiently towards the connecting clip 12, so as to dissipate the heat.

The conductive layer 14 and the solder layer 15 may comprise metal. For example, the conductive layer 14 may comprise copper, and the solder layer 15 may comprise alloy of tin (Sn) and silver (Ag) . In some embodiments, the solder layer 15 may comprise alloy of tin, silver, and copper (Cu) , or alloy of lead (Pb) , tin, and silver. Therefore, the conductive layer 14 and the solder layer 15 can form a proper connection.

In this embodiment, the nitride-based semiconductor circuit 1A comprises a dielectric layer 16. The dielectric layer 16 encapsulate the connecting clips 12 to the carrier 10, and the ground surfaces 121 and the connecting surfaces 120 are free from the dielectric layer 16. The dielectric layer 16 do not cover the ground surfaces 121 and the connecting surfaces 120 of the connecting clips 12, and, therefore; the connecting clips 12 can form electrical connection through the connecting surfaces 120 and dissipate heat through the ground surfaces 121.

The dielectric layer 16 protect most of the connecting clips 12 on the carrier 10, and the dielectric layer 16 provide structural support between the connecting clips 12 and the carrier 10. Also, the dielectric layer 16 fixes the connecting clips 12 on the carrier 10. Therefore, the connecting clips 12 on the carrier 10 won’t be deformed or moved.

In this embodiment, every connecting clip 12 has a connecting part 122, a heat dissipation part 123, a slanted part 124, and a connecting part 125. The heat dissipation part 123 connects the connecting part 122 and the slanted part 124, and the slanted part 124 connects the heat dissipation part 123 and the connecting part 125.

The heat dissipation parts 123 have the ground surfaces 121, and the heat dissipation parts 123 are located at the top of the nitride-based semiconductor circuit 1A. The connecting part 122 is located on the nitride-based semiconductor die 11, and the connecting part 122 is connected to the nitride-based semiconductor die 11. Therefore, heat generated from the nitride-based semiconductor die 11 can be transmitted to the heat dissipation part 123 through the connecting part 122, and the heat can be dissipated through the ground surface 121.

The connecting parts 125 have connecting surfaces 120, and the connecting parts 125 are located at the bottom of the nitride-based semiconductor circuit 1A. Therefore, the connecting surfaces 120 are located near the bottom of the nitride-based semiconductor circuit 1A, and connection can be formed easily through the bottom of the nitride-based semiconductor circuit 1A through the connecting surfaces 120 with high heat dissipation performance.

To be specific, every connecting part 125 has a bottom surface 126, and the carrier 10 has a bottom surface 102. The bottom surface 102 is facing backward towards the nitride-based semiconductor die 11, and the bottom surface 102 and the top surface 101 is opposite. The bottom surfaces 126 of the connecting parts 125 and the bottom surface 102 of the carrier 10 are coplanar, and the bottom surfaces 126 of the connecting clips 12 are free from any material. Therefore, connection of the nitride-based semiconductor die 11 can be formed easily through the bottom surfaces 126 and the connecting surfaces 120.

FIGS. 2-10 are side sectional views of steps of a manufacturing method of the nitride-based semiconductor circuit 1A according to some embodiments of the present disclosure. In the following descriptions, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes. Referring to FIG. 2, 3 and 4, the manufacturing method of this embodiment includes: providing the carrier 10 having a plurality of accommodation holes 100 and a plurality of connection holes 103. Every two of the connection holes 103 are disposed between two adjacent accommodation holes 100. In other words, two of the connection holes 103 and one of the accommodation holes 100 form a group of holes, and a plurality of groups are formed on the carrier 10.

Referring to FIG. 2, in this embodiment, the step of providing the carrier 10 comprises: providing the carrier 10. The carrier 10 has the top surface 101 and the bottom surface 102, and the top surface 101 and bottom surface 102 are opposite. In this step, the carrier 10 has no hole or opening formed thereon.

Referring to FIG. 3, in this embodiment, the step of providing the carrier 10 comprises: etching the accommodation holes 100 on the carrier 10. The accommodation holes 100 are concaved from the top surface 101. The accommodation hole 100 has a bottom 1001 form in the carrier 10, and the accommodation holes 100 are separated. The distance remain between the accommodation holes 100 are longer than two times the width of every accommodation hole 100.

Referring to FIG. 4, in this embodiment, the step of providing the carrier 10 comprises: etching the connection holes 103 on the carrier 10. The accommodation holes 100 are located among the connection holes 103. The connection holes 103 pass through the carrier 10, and a width of every connection hole 103 is smaller than the width of the accommodation hole 100. Therefore, the carrier 10 can provide accommodation spaces for nitride-based semiconductor dies 11 and connecting clip 12 respectively.

Referring to FIG. 5, after the carrier 10 is provided, the manufacturing method disposes a plurality of nitride-based semiconductor dies 11 in the accommodation holes 100 respectively. Every nitride-based semiconductor die 11 in the accommodation hole 100 is surrounded by the connection holes 103.

To be specific, a depth of every accommodation hole 100 and a height of the nitride-based semiconductor die 11 therein are the same. The top surface 101 of the carrier 10 and the top surface 113 of the nitride-based semiconductor die 11 are coplanar. Therefore, the carrier 10 can compensate the height of the nitride-based semiconductor dies 11.

Also, the connecting pads 112 of the nitride-based semiconductor die 11 is embedded in the top surface 113. The top surfaces of the connecting pads 112 and the top surface 101 of the carrier 10 are also coplanar. Therefore, the nitride-based semiconductor die 11 in the carrier 10 provide a proper interface for electrical connection.

Referring to FIGS. 6, 7, and 8, after the nitride-based semiconductor dies 11 are disposed, the manufacturing method disposes a plurality of connecting clips 12 in the connection holes 103 and connects the connecting clips 12 and the nitride-based semiconductor dies 11. One side of every connecting clip 12 is inserted into one of the connection holes 103, and the other side of the connecting clip 12 span across part of the carrier 10 and connected to the nitride-based semiconductor die 11. In other words, every connecting clip 12 is extended from one of the connection holes 103 and cover one of the nitride-based semiconductor dies 11. Therefore, the nitride-based semiconductor die 11 can be electrically connected towards the other side of the carrier 10 and form proper interfaces for electrical connection.

Referring to FIG. 6, before the step of disposing the connecting clips 12, the manufacturing method of this embodiment comprises: disposing a dielectric layer 13 on every nitride-based semiconductor die 11. The dielectric layer 13 covers the top surface 113 of the nitride-based semiconductor die 11, and the connecting pads 112 are free from the dielectric layer 13. The dielectric layer 13 also covers the top surface 101 of the carrier 10 that surrounds the top surface 113 of the nitride-based semiconductor die 11, and the dielectric layer 13 doesn’t cover the top surface 101 near the connection hole 103. Therefore, the dielectric layer 13 provides dielectric platforms near the connecting pads 112.

In this embodiment, the dielectric layer 13 surrounds the nitride-based semiconductor die 11. Therefore, the dielectric layer 13 insulate the top surfaces 113 of the nitride-based semiconductor dies 11 from the carrier 10, so as to provide a proper interface for the connection of the connecting pads 112.

To be specific, every dielectric layer 13 fills the gap between the nitride-based semiconductor die 11 and the accommodation hole 100. Therefore, the carrier 10 may hold the nitride-based semiconductor dies 11 firmly through the dielectric layer 13. The connection between the carrier 10 and the nitride-based semiconductor dies 11 are solid.

Referring to FIG. 7, after the dielectric layers 13 are disposed, the manufacturing method disposes a plurality of conductive layers 14. The conductive layers 14 cover the dielectric layers 13 and the connecting pads 112. To be specific, every conductive layer 14 is disposed on one of the connecting pads 112 and part of the dielectric layer 13 near the connecting pad 112. The connecting pad 112 provide a wide plane for electrical connection on the nitride-based semiconductor die 11 and the carrier 10.

Referring to FIG. 8, after the conductive layers 14 are disposed, the manufacturing method dispose the connecting clips 12. Every connecting clip 12 is connected to the conductive layer 14 through a solder layer 15, and the solder layer 15 and the conductive layer 14 provide an electrical connection with low resistance between the connecting clip 12 and the nitride-based semiconductor die 11.

To be specific, in every connecting clip 12, the connecting part 125 and part of the slanted part 124 is inserted into the connection hole 103. The connecting part 122, the heat dissipation part 123, and the rest of the slanted part 124 is located above the carrier 10, and the connecting part 122 is connected to the nitride-based semiconductor die 11.

Referring to FIG. 9, after the connecting clips 12 are disposed, the manufacturing method encapsulates the connecting clips 12 on the carrier 10 with the dielectric layer 16. The dielectric layer 16 covers the connecting clips 12 and the carrier 10, and the dielectric layer 16 fills the gap between the connecting clips 12 and the carrier 10. Therefore, the connecting clips 12 are fixed on the carrier 10.

Also, the dielectric layer 16 fills the connection holes 103, and, therefore, the connecting clip 12 in the connection hole 103 is firmly hold by the carrier 10 and the dielectric layer 16.

In one aspect, the connecting surface 120 and the bottom surface 126 of the connecting clip 12 are free from the dielectric layer 16. Therefore, the connecting surface 120 and the bottom surface 126 can provide good electrical connecting interfaces.

Referring to FIG. 10, after the connecting clips 12 are encapsulated, the manufacturing method grinds the dielectric layer 16 and expose the ground surface 121 on every connecting clip 12. Part of the dielectric layer 16 above the ground surface 121 is removed, and the ground surface 121 is free from any other material.

After grinding the dielectric layer 16, the manufacturing method dices the carrier 10 and separates the nitride-based semiconductor dies 11 and expose the connecting surface 120 on every connecting clip 12, and the nitride-based semiconductor circuit 1A as shown in FIG. 1 is provided. The manufacturing method of this embodiment remove the materials on the ground surfaces 121 and connecting surfaces 120, and the manufacturing method disposes the ground surfaces 121 at the top of the nitride-based semiconductor circuit 1A, and the manufacturing method disposes the connecting surfaces 120 at the bottom of the nitride-based semiconductor circuit 1A. Therefore, the nitride-based semiconductor circuit 1A can dissipate the heat from the nitride-based semiconductor die 11 through the ground surfaces 121, and the nitride-based semiconductor circuit 1A can form proper electrical connection through the connecting surfaces 120.

The ground surfaces 121 are located above the carrier 10 and the nitride-based semiconductor die 11, and, therefore; the connecting clips 12 may dissipate the heat from the nitride-based semiconductor die 11.

Also, the depth of the accommodation hole 100 is corresponded to the height of the nitride-based semiconductor die 11. Therefore, the carrier 10 can compensate the nitride-based semiconductor die 11 having different height, so as to form connection of the nitride-based semiconductor die 11 easily. In other words, the depth of the accommodation hole 100 can be varied with the height of the nitride-based semiconductor die 11.

FIG. 11 is a side sectional view of a nitride-based semiconductor circuit 1B according to some embodiments of the present disclosure. Referring to FIG. 11, the nitride-based semiconductor circuit 1B is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1. The nitride-based semiconductor circuit 1B has a carrier 10, a nitride-based semiconductor die 11, and a plurality of connecting clips 12B. The carrier 10 has an accommodation hole 100, and the nitride-based semiconductor die 11 is disposed in the accommodation hole 100. The nitride-based semiconductor die 11 has a nitride-based semiconductor layer 110 and a nitride-based semiconductor layer 111. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and a 2DEG region is formed near the interface between the nitride-based semiconductor layers 110, 111. The connecting clips 12B are connected to the nitride-based semiconductor die 11, and every connecting clip 12B has a connecting surface 120 and a ground surface 121B. The ground surfaces 121B are located at the top of the nitride-based semiconductor circuit 1B, and the connecting surfaces 120 are located at the bottom of the nitride-based semiconductor circuit 1B.

In this embodiment, the nitride-based semiconductor circuit 1B has a plurality of conductive layers 14 and a plurality of solder layers 15. Every connecting clip 12B is connected to the nitride-based semiconductor die 11 through one of the conductive layers 14 and one of the solder layers 15. The conductive layers 14 are disposed on the nitride-based semiconductor die 11, and the solder layers 15 are disposed on the conductive layers 14 respectively.

To be specific, in this embodiment, every conductive layer 14 has a connecting surface 140 located at its top. The connecting surface 140 is covered by one of the solder layers 15, and the ground surface 121B is larger than the connecting surface 140, which is different from the nitride-based semiconductor circuit 1A as shown in FIG. 1. Therefore, the nitride-based semiconductor circuit 1B may have flexibility to have different designs, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1B with design that is different from the designs of the nitride-based semiconductor circuits above.

The ground surface 121B is larger than the connecting surface 140. Therefore, the heat dissipation efficiency of the connecting clips 12B are improved. The ground surfaces 121B have large area, so as to dissipate the heat from the nitride-based semiconductor die 11 efficiently.

Also, the ground surface 121B of every connecting clip 12B is larger than a top surface 113 of the nitride-based semiconductor die 11. Therefore, the connecting clips 12B improves the heat dissipation of the nitride-based semiconductor die 11.

FIG. 12 is a side sectional view of a nitride-based semiconductor circuit 1C according to some embodiments of the present disclosure. Referring to FIG. 12, the nitride-based semiconductor circuit 1C is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1. The nitride-based semiconductor circuit 1C has a carrier 10, a nitride-based semiconductor die 11, and a plurality of connecting clips 12C. The carrier 10 has an accommodation hole 100, and the nitride-based semiconductor die 11 is disposed in the accommodation hole 100. The nitride-based semiconductor die 11 has a nitride-based semiconductor layer 110 and a nitride-based semiconductor layer 111. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and a 2DEG region is formed near the interface between the nitride-based semiconductor layers 110, 111. The connecting clips 12C are connected to the nitride-based semiconductor die 11, and every connecting clip 12C has a connecting surface 120 and a ground surface 121C. The ground surfaces 121C are located at the top of the nitride-based semiconductor circuit 1C, and the connecting surfaces 120 are located at the bottom of the nitride-based semiconductor circuit 1C.

In this embodiment, the nitride-based semiconductor circuit 1C has a plurality of conductive layers 14 and a plurality of solder layers 15. Every connecting clip 12C is connected to the nitride-based semiconductor die 11 through one of the conductive layers 14 and one of the solder layers 15. The conductive layers 14 are disposed on the nitride-based semiconductor die 11, and the solder layers 15 are disposed on the conductive layers 14 respectively.

To be specific, in this embodiment, every conductive layer 14 has a connecting surface 140 located at its top. The connecting surface 140 is covered by one of the solder layers 15, and the ground surface 121C covers the connecting surface 140, which is different from the nitride-based semiconductor circuit 1A as shown in FIG. 1. Therefore, the nitride-based semiconductor circuit 1C may have flexibility to have different designs, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1C with design that is different from the designs of the nitride-based semiconductor circuits above.

The ground surfaces 121C cover the connecting surfaces 140 respectively, and the ground surfaces 121C cover the periphery of the nitride-based semiconductor die 11. Therefore, every ground surface 121C occupies a large area, and the connecting clip 12C can dissipate heat generated from the nitride-based semiconductor die 11 efficiently through the ground surface 121C.

Also, the ground surface 121C of every connecting clip 12C is larger than a top surface 113 of the nitride-based semiconductor die 11. Therefore, the connecting clips 12C improves the heat dissipation of the nitride-based semiconductor die 11.

FIG. 13 is a side sectional view of a nitride-based semiconductor circuit 1D according to some embodiments of the present disclosure. Referring to FIG. 13, the nitride-based semiconductor circuit 1D is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1. The nitride-based semiconductor circuit 1D has a carrier 10, a nitride-based semiconductor die 11, and a plurality of connecting clips 12D. The carrier 10 has an accommodation hole 100, and the nitride-based semiconductor die 11 is disposed in the accommodation hole 100. The nitride-based semiconductor die 11 has a nitride-based semiconductor layer 110 and a nitride-based semiconductor layer 111. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and a 2DEG region is formed near the interface between the nitride-based semiconductor layers 110, 111. The connecting clips 12D are connected to the nitride-based semiconductor die 11, and every connecting clip 12D has a connecting surface 120 and a ground surface 121D. The ground surfaces 121D are located at the top of the nitride-based semiconductor circuit 1D, and the connecting surfaces 120 are located at the bottom of the nitride-based semiconductor circuit 1B.

In this embodiment, every connecting clip 12D has a plurality of protrusions 127. The protrusions 127 are facing towards the carrier 10, which is different from the nitride-based semiconductor circuit 1A as shown in FIG. 1. Therefore, the nitride-based semiconductor circuit 1D may have flexibility to have different designs, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1D with design that is different from the designs of the nitride-based semiconductor circuits above.

The protrusions 127 are fully covered by the dielectric layer 16, and the protrusions 127 increase the connecting surface between the dielectric layer 16 and the connecting clip 12D. Therefore, the connection between the connecting clips 12D and the dielectric layer 16 is strengthened, so as to improve the connection between the carrier 10 and the connecting clips 12D.

FIG. 14 is a side sectional view of a nitride-based semiconductor circuit 1E according to some embodiments of the present disclosure. Referring to FIG. 14, the nitride-based semiconductor circuit 1E is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1. The nitride-based semiconductor circuit 1E has a carrier 10, a nitride-based semiconductor die 11, and a plurality of connecting clips 12E. The carrier 10 has an accommodation hole 100, and the nitride-based semiconductor die 11 is disposed in the accommodation hole 100. The nitride-based semiconductor die 11 has a nitride-based semiconductor layer 110 and a nitride-based semiconductor layer 111. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and a 2DEG region is formed near the interface between the nitride-based semiconductor layers 110, 111. The connecting clips 12E are connected to the nitride-based semiconductor die 11, and every connecting clip 12E has a connecting surface 120 and a ground surface 121E. The ground surfaces 121E are located at the top of the nitride-based semiconductor circuit 1E, and the connecting surfaces 120 are located at the bottom of the nitride-based semiconductor circuit 1E.

In this embodiment, each of the connecting clips 12E has a plurality of concave structures 128, and the concave structures 128 are disposed on the ground surface 121E, which is different from the nitride-based semiconductor circuit 1A as shown in FIG. 1. Therefore, the nitride-based semiconductor circuit 1E may have flexibility to have different designs, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1E with design that is different from the designs of the nitride-based semiconductor circuits above.

In the manufacturing method of the nitride-based semiconductor circuit 1E, the concave structures 128 may be formed through the step of grinding the dielectric layer 16. The concave structures 128 increase the contacting area of the ground surface 121E, and, therefore; the connecting clips 12E can dissipate heat generated from the nitride-based semiconductor die 11 more efficiently.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor circuit comprising:

a carrier having an accommodation hole;

a nitride-based semiconductor die disposed in the accommodation hole;

a plurality of first connecting surfaces located around the carrier; and

a plurality of connecting clips connecting the nitride-based semiconductor die and the first connecting surfaces;

wherein every connecting clip has a ground surface, and the ground surfaces are located at the top of the nitride-based semiconductor circuit, and the ground surfaces are located above the carrier and the nitride-based semiconductor die;

wherein the nitride-based semiconductor die has a first nitride-based semiconductor layer and a second nitride-based semiconductor layer, and the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and a bandgap of the second nitride-based semiconductor layer is greater than a bandgap of the first nitride-based semiconductor layer, and a 2DEG region is formed near an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer.
The nitride-based semiconductor circuit of claim 1, wherein the nitride-based semiconductor die comprises:

a plurality of connecting pads;

a first top surface; and

a first bottom surface,

wherein the first top surface and the first bottom surface are opposite, and the connecting pads are embedded in the first top surface, and the first bottom surface is connected to a bottom of the accommodation hole of the carrier, and the connecting clips are electrically connected to the connecting pads.
The nitride-based semiconductor circuit of claim 2, wherein the carrier has a second top surface, and the second top surface surrounds the first top surface, and the second top surface and the first top surface are coplanar.
The nitride-based semiconductor circuit of claim 3 further comprising a first dielectric layer, wherein the first dielectric layer covers the first top surface and part of the second top surface that is surrounding the first top surface.
The nitride-based semiconductor circuit of claim 4, wherein part of the first dielectric layer surrounds the nitride-based semiconductor die.
The nitride-based semiconductor circuit of claim 4 further comprising a plurality of conductive layers, wherein the conductive layers are disposed on the first dielectric layer, and every conductive layer is connected to one of the connecting pads, and the connecting clips are electrically connected to the conductive layers.
The nitride-based semiconductor circuit of claim 6 further comprising a plurality of solder layers, wherein every solder layer connects one of the conductive layers and one of the connecting clips.
The nitride-based semiconductor circuit of claim 7, wherein every conductive layer has a second connecting surface, and the second connecting surface is covered by one of the solder layers, and the ground surfaces are larger than the second connecting surfaces.
The nitride-based semiconductor circuit of claim 8, wherein the ground surfaces cover the second connecting surfaces.
The nitride-based semiconductor circuit of claim 1 further comprising a second dielectric layer, and the second dielectric layer encapsulate the connecting clips to the carrier, and the ground surfaces and the first connecting surfaces are free from the second dielectric layer.
The nitride-based semiconductor circuit of claim 1, wherein every connecting clip comprises:

a first connecting part;

a heat dissipation part having the ground surface;

a slanted part; and

a second connecting part having the first connecting surface;

wherein the heat dissipation part connects the first connecting part and the slanted part, and the slanted part connects the heat dissipation part and the second connecting part;

wherein the heat dissipation parts are located at the top of the nitride-based semiconductor circuit, and the second connecting parts are located at the bottom of the nitride-based semiconductor circuit.
The nitride-based semiconductor circuit of claim 11, wherein every second connecting part has a second bottom surface, and the carrier has a third bottom surface, and the second bottom surfaces and the third bottom surface are coplanar.
The nitride-based semiconductor circuit of claim 1, wherein a height of the nitride-based semiconductor die and a depth of the accommodation hole are the same.
The nitride-based semiconductor circuit of claim 1, wherein each of the connecting clips has a plurality of first protrusions facing towards the carrier.
The nitride-based semiconductor circuit of claim 1, wherein each of the connecting clips has a plurality of concave structures disposed on the ground surface.
A method for manufacturing a nitride-based semiconductor circuit, comprising:

providing a carrier having a plurality of accommodation holes and a plurality of connection holes;

disposing a plurality of nitride-based semiconductor dies in the accommodation holes respectively;

disposing a plurality of connecting clips in the connection holes and connect the connecting clips and the nitride-based semiconductor dies;

encapsulating the connecting clips on the carrier with a second dielectric layer;

grinding the second dielectric layer and expose a ground surface on every connecting clip; and

dicing the carrier and separate the nitride-based semiconductor dies and expose a first connecting surface on every connecting clip;

wherein the ground surfaces are located at the top of the nitride-based semiconductor circuit, and the ground surfaces are located above the carrier and the nitride-based semiconductor die;

wherein each of the nitride-based semiconductor dies has a first nitride-based semiconductor layer and a second nitride-based semiconductor layer, and the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and a bandgap of the second nitride-based semiconductor layer is greater than a bandgap of the first nitride-based semiconductor layer, and a 2DEG region is formed near an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer.
The method of the claim 16, wherein the step of providing the carrier comprises:

etching the accommodation holes on the carrier; and

etching the connection holes on the carrier;

wherein the accommodation holes are located among the connection holes, and a depth of every accommodation hole and a height of every nitride-based semiconductor die are the same.
The method of the claim 16, wherein every connecting clip is extended from one of the connection holes and cover one of the nitride-based semiconductor dies.
The method of the claim 16, before the step of disposing the connecting clips, further comprising:

disposing a first dielectric layers on every nitride-based semiconductor die;

wherein the first dielectric layer surrounds the nitride-based semiconductor die.
The method of the claim 19, wherein every first dielectric layer fills the gap between the nitride-based semiconductor die and the accommodation hole.
A nitride-based semiconductor circuit comprising:

a carrier;

a nitride-based semiconductor die embedded in the carrier; and

a plurality of connecting clips having ground surface and first connecting surface;

wherein the connecting clips are electrically connected to the nitride-based semiconductor die, and the first connecting surfaces are located at sides of the nitride-based semiconductor circuit, and the ground surfaces are located at a top of the nitride-based semiconductor circuit;

wherein the nitride-based semiconductor die has a first nitride-based semiconductor layer and a second nitride-based semiconductor layer, and the second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and a bandgap of the second nitride-based semiconductor layer is greater than a bandgap of the first nitride-based semiconductor layer, and a 2DEG region is formed near an interface between the first nitride-based semiconductor layer and the second nitride-based semiconductor layer.
The nitride-based semiconductor circuit of claim 21, wherein the first connecting surfaces are located near a bottom of the nitride-based semiconductor circuit, and a second bottom surface of every connecting clip is free from any material.
The nitride-based semiconductor circuit of claim 21, wherein the carrier has an accommodation hole, and the nitride-based semiconductor die is disposed in the accommodation hole, and a first dielectric layer fills the gap between the nitride-based semiconductor die and the accommodation hole.
The nitride-based semiconductor circuit of claim 21, wherein the ground surface of every connecting clip is larger than a first top surface of the nitride-based semiconductor die.
The nitride-based semiconductor circuit of claim 21, wherein a first top surface of the nitride-based semiconductor die and a second top surface of the carrier are coplanar.