WO2024098356A1

WO2024098356A1 - Nitride-based semiconductor circuit and method for manufacturing thereof

Info

Publication number: WO2024098356A1
Application number: PCT/CN2022/131258
Authority: WO
Inventors: Ergang Xu; Kai Cao; Jianping Zhang
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2024-05-16

Abstract

A nitride-based semiconductor circuit comprises conductive layer, nitride-based semiconductor die, carrier layer, and antenna structures. The nitride-based semiconductor die is disposed over the conductive layer. The carrier layer is disposed on the nitride-based semiconductor die. The antenna structures are disposed over the carrier layer. The nitride-based semiconductor die comprises a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a first cavity structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and the second nitride-based semiconductor layer has a bandgap less than a bandgap of the first nitride-based semiconductor layer. The first cavity structure is disposed over the second nitride-based semiconductor layer. The antenna structures are electrically connected to the conductive layer. The carrier layer has a second cavity structure, and the second cavity structure and the first cavity structure are connected.

Description

NITRIDE-BASED SEMICONDUCTOR CIRCUIT AND METHOD FOR MANUFACTURING THE SAME

Inventors: Ergang Xu, Kai Cao, Jiangping Zhang

Field of the Invention:

The present invention generally relates to a semiconductor circuit. More specifically, the present invention relates to a high electron mobility transistor (HEMT) nitride-based semiconductor circuit having an antenna.

Background of the Invention:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent for semiconductor devices, such as high power switching and high frequency applications. The HEMT utilizes a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) . At present, there is a need to improve the yield rate for HEMT devices, thereby making them suitable for mass production.

Summary of the Invention:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor circuit is provided. The nitride-based semiconductor circuit comprises a conductive layer, a nitride-based semiconductor die, a carrier layer, and a plurality of antenna structures. The nitride-based semiconductor die is disposed over the conductive layer. The carrier layer is disposed on the nitride-based semiconductor die. The antenna structures are disposed over the carrier layer. The nitride-based semiconductor die comprises a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a first cavity structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and the second nitride-based semiconductor layer has a bandgap less than a bandgap of the first nitride-based semiconductor layer. The first cavity structure is disposed over the second nitride-based semiconductor layer. The antenna structures are electrically connected to the conductive layer. The carrier layer has a second cavity structure, and the second cavity structure and the first cavity structure are connected.

In accordance with one aspect of the present disclosure, a method for manufacturing a nitride-based semiconductor circuit is provided. The method includes steps as follows: disposing a nitride-based semiconductor die on a first substrate; etching the nitride-based semiconductor die and form a first cavity structure; disposing a carrier layer on the nitride-based semiconductor die; disposing a plurality of antenna structures over the carrier layer; disposing a second substrate on the antenna structures; flipping the nitride-based semiconductor die and removing the first substrate; disposing a conductive layer over the nitride-based semiconductor die; and removing the second substrate. The nitride-based semiconductor die comprises a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and the first cavity structure. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and the second nitride-based semiconductor layer has a bandgap less than a bandgap of the first nitride-based semiconductor layer. The first cavity structure is disposed over the second nitride-based semiconductor layer. The antenna structures are electrically connected to the conductive layer. The carrier layer has a second cavity structure, and the second cavity structure and the first cavity structure are connected.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor circuit is provided. The nitride-based semiconductor circuit comprises a conductive layer, a nitride-based semiconductor die, a carrier layer, and a plurality of antenna structures. The nitride-based semiconductor die is disposed over the conductive layer. The carrier layer is disposed on the nitride-based semiconductor die. The antenna structures are disposed over the carrier layer. The nitride-based semiconductor die comprises a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and a first well. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer, and the second nitride-based semiconductor layer has a bandgap less than a bandgap of the first nitride-based semiconductor layer. The first well is disposed over the second nitride-based semiconductor layer. The antenna structures are electrically connected to the conductive layer. The carrier layer comprises a second well, and the second well covers the first well of the nitride-based semiconductor die, and an opening of the second well and an opening of the first well are connected.

By applying the above configuration, nitride-based semiconductor circuit comprising antenna structures having wide bandwidth and high efficiency can be achieved. As such, a HEMT circuit with antenna structures can be manufactured with wide bandwidth and high efficiency.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIGS. 2-15 are side sectional view of steps of a manufacturing method of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 16 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 17 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 18 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 19 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 20 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure;

FIG. 21 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure; and

FIG. 22 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

In the following description, semiconductor circuits, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. Referring to FIG. 1, the nitride-based semiconductor circuit 1A of this embodiment comprises a conductive layer 10, a nitride-based semiconductor die 11, a carrier layer 12, and a plurality of antenna structures 13.

The nitride-based semiconductor die 11 is disposed over the conductive layer 10. The carrier layer 12 is disposed on the nitride-based semiconductor die 11. The antenna structures 13 are disposed over the carrier layer 12. The antenna structures 13 are electrically connected to the conductive layer 10. In this embodiment, the nitride-based semiconductor die 11 and the carrier layer 12 are disposed between the conductive layer 10 and the antenna structures 13, and the nitride-based semiconductor die 11 and the carrier layer 12 provide a passageway with low resistance.

To be specific, in this embodiment, the nitride-based semiconductor die 11 comprises a nitride-based semiconductor layer 110, a nitride-based semiconductor layer 111, and a cavity structure 112. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and the nitride-based semiconductor layer 111 has a bandgap less than a bandgap of the nitride-based semiconductor layer 110. To be specific, the nitride-based semiconductor layer 110 and the nitride-based semiconductor layer 111 form a heterojunction, and a 2DEG region is formed. The nitride-based semiconductor die 11 comprise a plurality of HEMTs, and the nitride-based semiconductor layer 110 and the nitride-based semiconductor layer 111 form a channel layer and a barrier layer of every HEMTs.

In this embodiment, the cavity structure 112 is disposed over the nitride-based semiconductor layer 111. In other words, the cavity structure 112 is located at the top of the nitride-based semiconductor die 11, while the bottom of the nitride-based semiconductor die 11 is connected to the conductive layer 10.

In this embodiment, the carrier layer 12 has a cavity structure 120, and the cavity structure 120 and the cavity structure 112 are connected. In other word, the cavity structure 112 is a well, and the cavity structure 120 is a well, and an opening of the well of the nitride-based semiconductor die 11 and an opening of the well of the carrier layer 12 are connected. The cavity structure 120 and the cavity structure 112 together form an accommodating space above the nitride-based semiconductor layer 110 and the nitride-based semiconductor layer 111. The accommodating space possesses low resistance, and the nitride-based semiconductor die 11 and the carrier layer 12 provide a passageway with low resistance between the antenna structures 13 and the conductive layer 10 through the cavity structure 112 and the cavity structure 120. Therefore, the bandwidth of the antenna structures 13 may be improved and widen. Also, the efficiency of the antenna structures 13 may be improved as well.

In other words, there are fewer dielectric materials and substrate material such as silicon between the antenna structures 13 and the conductive layer 10, and the antenna structures 13 may have wider bandwidth because the resistance is reduced. Moreover, the cavity structure 112 is formed in the nitride-based semiconductor die 11, and the cavity structure 120 is formed in the carrier layer 12, and no extra structure is formed around the nitride-based semiconductor die 11 and the carrier layer 12. Therefore, the size of the nitride-bases semiconductor circuit 1A is compact. Also, the dielectric constant of the filling material in the

cavity structures

112, 120 is smaller than silicon. Therefore, the bandwidth and the efficiency of the antenna structures 13 are increased.

In one aspect, the carrier layer 12 separates the space surrounded by the cavity structure 112 and the cavity structure 120, and the reduction of the resistance can be properly controlled by the size of the cavity structure 120 of the carrier layer 12. In other words, the cavity structure 112 is a well, and the carrier layer encloses the well of the nitride-based semiconductor die 11, and no other material will be diffused or intruded. Therefore, the resistance of the passageway provided by the nitride-based semiconductor die 11 and the carrier layer 12 is under well controlled.

Also, the carrier layer 12 provide a structural support to the antenna structures 13, and, therefore; the antenna structures 13 can be well formed above the nitride-based semiconductor die 11. The distance between the antenna structures 13 and the conductive layer 10 can be unified, and the resistance between the antenna structures 13 and the conductive layer 10 can be controlled by the

cavity structures

120, 112.

In this embodiment, the conductive layer 10 is patterned, and the conductive layer 10 may have metal lines, pads, traces, or combination thereof, such that the conductive layer 10 can form a plurality of circuits. At least one of the circuits is grounded, and at least one of the circuits is the feed of the antenna structures 13. To be specific, at least one of the circuits that is electrically connected to the antenna structures 13 is the feed of the antenna structures. The exemplary materials of the conductive layer 10 can include, for example but are not limited to, conductive materials. The conductive layer 10 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitride thereof, or combinations thereof.

In this embodiment, the exemplary materials of the antenna structures 13 can include, for example but are not limited to, conductive materials. The antenna structure 13 may include Cu. To be specific, the antenna structures 13 may be plating Cu.

In this embodiment, the nitride-based semiconductor die 11 has the nitride-based semiconductor layer 110, the nitride-based semiconductor layer 111, and the 2DEG region. The 2DEG region is formed near an interface between the nitride-based semiconductor layer 110 and the nitride-based semiconductor layer 111. For example, the nitride-based semiconductor layer 110 may include aluminum gallium nitride (AlGaN) , and the nitride-based semiconductor layer 111 may include gallium nitride (GaN) .

To be specific, the exemplary materials of the nitride-based semiconductor layers 110, 111 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InAlN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 110, 111 are selected such that the nitride-based semiconductor layer 110 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 111, which causes electron affinities thereof different from each other and forms the heterojunction therebetween. As such, the nitride-based semiconductor layers 111, 110 can serve as the channel layer and the barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating the two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

In this embodiment, the nitride-based semiconductor die 11 may include a substrate 113. The cavity structure 112 is formed in the substrate 113.

The exemplary materials of the substrate 113 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 113 can include, for example but are not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 113 can include, for example, but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxy (epi) layer, or combinations thereof.

In this embodiment, the cavity structure 112 is a concave structure of the substrate 113. To be specific, the cavity structure 112 is a well, and a periphery of the well is covered by the antenna structures 13. Therefore, the well can reduce the resistance between the antenna structures 13 and the conductive layer 10, and bandwidth and efficiency of the antenna structures 13 can be improved.

Also, the cavity structure 120 is a concave structure of the carrier layer 12. To be specific, the cavity structure 120 is a well, and a periphery of the well is covered by the antenna structures 13. Therefore, the wall can further reduce the resistance between the antenna structures 13 and the conductive layer 10 as well, and bandwidth and efficiency of the antenna structures 13 can be improved.

In this embodiment, the opening of the well of the nitride-based semiconductor die 11 faces towards the opening of the well of the carrier layer 12. The cavity structure 120 and the cavity structure 112 form at least one accommodating space, and the accommodating space is free from the materials of the substrate 113 and the carrier layer 12. The accommodating space is filles with material having low resistance, and the material has the resistance that is lower than the resistance of the materials of the substrate 113 and the carrier layer 12.

In this embodiment, the material of the carrier layer 12 may include silicon or material with dielectric constant that is lower than 11. Therefore, the carrier layer 12 can form the cavity structure 120 and separate materials around the carrier layer 12 from the cavity structure 120.

In one aspect, the nitride-based semiconductor circuit 1A comprises a filling 14, and the filing 14 fills the cavity structure 112 and the cavity structure 120. To be specific, the filling 14 fills the accommodating space formed by the cavity structure 112 and the cavity structure 120. In other words, the cavity structure 112 of this embodiment is a well, and the cavity structure 120 is a well as well, and the filling 14 fills the wells.

The filling 14 possess low resistance, and the nitride-based semiconductor die 11 may provide a passageway with low resistance. Moreover, the filling 14 may further provide a structural support to the carrier layer 12 and the antenna structures 13, and the antenna structures 13 are well disposed above the nitride-based semiconductor die 11.

For example, the filling 14 comprises foam material with low dielectric constant, and the dielectric constant of the filling 14 is lower than 2.25. Therefore, the cavity structure 112 and the cavity structure 120 filled with filling 14 can provide a passageway with low resistance. To be specific, the resistance of the filling 14 is lower than the substrate 113, the carrier layer 12, and a dielectric layer 16 around the nitride-based semiconductor die 11. Therefore, the cavity structure 112 filled with the filling 14 and the cavity structure 120 filled with the filling 14 possess lower resistance, and the cavity structure 112 and the cavity structure 120 may provide a good electrical passageway. In other words, the wells filled with the filling 14 possesses lower resistance, and the reduction of the resistance is controlled by the size of the wells, so as to provide a good electrical connection between the antenna structures 13 and the conductive layer 10, and the bandwidth and the efficiency of the antenna structures 13 may be improved.

In one aspect, part of the cavity structure 112 is located between the antenna structures 13 and the conductive layer 10, and part of the cavity structure 120 is located between the antenna structures 13 and the conductive layer 10. The

cavity structures

112, 120 may reduce the resistance between the antenna structures 13 and the conductive layer 10, and the nitride-based semiconductor die 11 preserves enough space for the antenna structures 13 to form solid electrical connection with the conductive layer 10.

To be specific, the nitride-based semiconductor circuit 1A comprises a plurality of vias 15, and the nitride-based semiconductor die 11 is distributed among the vias 15. Every via 15 connects one of the antenna structures 13 to the conductive layer 10. Moreover, every via 15 penetrate through the carrier layer 12 and the dielectric layer 16 surrounding the nitride-based semiconductor die 11, and the antenna structures 13 are disposed over the vias 15, and part of the cavity structure 112 and part of the cavity structure 120 may be disposed between the antenna structures 13 and the conductive layer 10. Therefore, the bandwidth and the efficiency of the antenna structures 13 may be improved.

For example, in this embodiment, the nitride-based semiconductor circuit 1A has two nitride-based semiconductor dies 11, and the nitride-based semiconductor dies 11 are distributed among the vias 15. The number of the vias 15 and the number of the antenna structures 13 are the same, and the vias 15 electrically connect the antenna structures 13 and the conductive layer 10 respectively.

Also, every via 15 connects the antenna structure 13 and the conductive layer 10, and the nitride-based semiconductor die 11 provide another electrical passageway between the antenna structures 13 and the conductive layer 10 as well. Therefore, the nitride-based semiconductor die 11 and the vias 15 electrically connect the antenna structures 13 and the conductive layer 10 in parallel, and the resistance between the antenna structures 13 and the conductive layer 10 is reduced.

In one aspect, the antenna structures 13 cover a periphery of the cavity structure 112 of the nitride-based semiconductor die 11, and the antenna structures 13 cover a periphery of the cavity structure 120 of the carrier layer 12. Multiple antenna structures 13 can be carried by the

cavity structures

112, 120, and, therefore, the

cavity structures

112, 120 can reduced the resistance between the antenna structures 13 and the conductive layer 10.

In one aspect, the cavity structure 112 comprises a cavity 1120 and a sidewall 1121 surrounding the cavity 1120. The sidewall 1121 can separate the cavity 1120 from the substance around the nitride-based semiconductor die 11, and the cavity 1120 surrounded by the sidewall 1121 can preserve a low resistance area in the nitride-based semiconductor die 11. To be specific, the cavity 1120 surrounded by the sidewall 1121 preserved 40%to 60%of the total volume of the nitride-based semiconductor die 11, and, therefore; the resistance is reduced prominently.

Furthermore, the sidewall 1121 of the cavity structure 112 of the nitride-based semiconductor die 11 is vertical. Therefore, the cavity structure 112 occupies most of the top surface of the nitride-based semiconductor die 11, and, therefore; the nitride-based semiconductor die 11 can provide a passageway with low resistance between the antenna structures 13 and the conductive layer 10.

In this embodiment, the cavity structure 120 comprises a cavity 1200 and a sidewall 1201 surrounding the cavity 1200. The sidewall 1201 is connected to the nitride-based semiconductor die 11, and the sidewall 1201 can separate the cavity 1200 from the substance around the nitride-based semiconductor die 11. The cavity 1200 surrounded by the sidewall 1201 can preserve a low resistance area above the nitride-based semiconductor die 11. The cavity 1200 and the cavity 1120 are connected, and the resistance between the antenna structures 13 and the conductive layer 10 can be further reduced by the cavity 1200.

To be specific, the sidewall 1201 of the cavity structure 120 is vertical, and the sidewall 1201 can stand firmly on the nitride-based semiconductor die 11. Also, since the thickness of the cavity 1200 is unify, the resistance reduction of the cavity structure 120 can be solely controlled by the covering area of the cavity 1200.

Furthermore, in a direction d1, the

cavities

1200, 1120 together have a height h1, and the nitride-based semiconductor die 11 and the carrier layer 12 together have a height h2. The ratio of the height h1 to the height h2 falls in a range from 0.6 to 0.7. Therefore, the reduction of the resistance is significant.

In this embodiment, the cavity 1200 and the cavity 1120 enclose an area, and the area is filled with the filling 14. Since the filling 14 has low resistance, the cavity 1200 and the cavity 1120 can reduce the resistance between the antenna structures 13 and the conductive layer 10. Also, the filling 14 can provide structure support between the nitride-based semiconductor die 11 and the carrier layer 12.

In one aspect, the sidewall 1121 and the sidewall 1201 are continuously connected, and the filling 14 can fill the space properly without forming any bubble or gap. Therefore, the reduction of the resistance is under well control.

In one aspect, the cavity structure 112 of the nitride-based semiconductor die 11 is a well, and the cavity structure 120 of the carrier layer 12 is a well, and a bottom of the well of the nitride-based semiconductor die 11 and a bottom of the well of the carrier layer 12 and an interface between the nitride-based semiconductor die 11 and the conductive layer 10 are parallel. Therefore, the resistance reduction is unified around the horizontal are occupied by the

cavity structures

112, 120. In other words, the thickness of the

cavity structures

112, 120 are unified, and the

cavity structures

112, 120 can properly reduce the resistance between the antenna structures 13 and the conductive layer 10.

In one aspect, the nitride-based semiconductor circuit 1A comprises a passivation layer 18. The passivation layer 18 is disposed on the carrier layer 12, and the passivation layer 18 covers the cavity structure 112 of the nitride-based semiconductor die 11 and the cavity structure 120 of the carrier layer 12. The antenna structures 13 are disposed on the passivation layer 18.

The passivation layer 18 covers the

cavity structures

112, 120 and provide a firm base for the antenna structures 13, so the antenna structures 13 can be disposed on the

cavity structures

112, 120 properly. To be specific, in the direction d1, the nitride-based semiconductor die 11 and the carrier layer 12 has the height h2, and the passivation layer 18 has a height h3, and the direction d1 is parallel to a normal of the interface 17. The ratio of the height h3 to the height h2 ranges from 0.01 to 0.2. Therefore, the passivation layer 18 is a thin layer that supports the antenna structures 13, and the passivation layer 18 won’t affect the reduction of the resistance of the nitride-based semiconductor die 11 and the carrier layer 12. In FIG. 1, the thickness of the passivation layer 18 has been enlarged in order to clearly describe the structure of the nitride-based semiconductor circuit 1A, and the present disclosure is not limited to structural design in the figure.

In one aspect, no layer or opening is formed between the passivation layer 18 and the cavity structure 120 of the carrier layer 12. The carrier layer 12 has a direct contact with the passivation layer 18, and, therefore; the size of the nitride-based semiconductor circuit 1A is compact. Also, other than forming the cavity structure with deposited dielectric material, the substrate 113 and the carrier layer 12 can form the

cavity structures

112, 120 precisely, and the reduction of the resistance can be controlled by the size of the

cavity structures

112, 120.

To be specific, the cavity structures 112 of the nitride-based semiconductor die 11 and the cavity structure 120 of the carrier layer 12 are formed through dry etching, and, therefore; the shapes of the

cavity structures

112, 120 are controlled precisely. Also, the substrate 113 can form the sidewall 1121 that is firm and solid to preserve the cavity 1120, and the carrier layer 12 can form the sidewall 1201 that is firm and solid to preserve the cavity 1200. Therefore, the reduction of the resistance can be controlled precisely.

FIGS. 2-15 are side sectional views of steps of a manufacturing method of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. In some embodiments, a manufacturing method of the nitride-based semiconductor circuit 1A comprises: disposing the nitride-based semiconductor die 11 on a substrate 20. The following will describe the detailed description about the step with reference of FIGS. 2, and 3.

Referring to FIG. 2, the nitride-based semiconductor die 11 comprises the substrate 113, the nitride-based semiconductor layer 111, the nitride-based semiconductor layer 110, a circuit layer 114, and a plurality of connecting pads 118. The nitride-based semiconductor layer 111 is located between the nitride-based semiconductor layer 110 and the substrate 113. The nitride-based semiconductor layer 110 is located between the circuit layer 114 and the nitride-based semiconductor layer 111. The connecting pads 118 are disposed on the circuit layer 114.

To be specific, the nitride-based semiconductor die 11 has a surface 115, a surface 116, and a side surface 117. The surface 115 is opposite to the surface 116, and the side surface 117 connects the surface 115 and the surface 116. The surface 116 is formed by the substrate 113. The surface 115 is formed by the circuit layer 114, and the connecting pads 118 are embedded in the circuit layer 114, and the connecting pads 118 are exposed on the surface 115.

Referring to FIG. 3, the nitride-based semiconductor die 11 is disposed on the substrate 20. To be specific, the nitride-based semiconductor die 11 is disposed on a carrier surface 200 of the substrate 20. The surface 115 of the nitride-based semiconductor die 11 is connected to the substrate 20, and the connecting pads 118 are covered by the substrate 20. While the substrate 20 is located below the nitride-based semiconductor die 11, the nitride-based semiconductor layer 110 is disposed on the circuit layer 114, and the nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and the substrate 113 is disposed on the nitride-based semiconductor layer 111. The substrate 113 is located at the top, and the surface 116 of the nitride-based semiconductor die11 is facing upward, and nothing is covered thereon.

In this embodiment, after the nitride-based semiconductor die 11 is disposed on the substrate 20, the manufacturing method of the nitride-based semiconductor circuit 1A comprises: etching the nitride-based semiconductor die 11 and form the cavity structure 112. The following will describe the detailed description about the step with reference of FIGS. 4, and 5.

Referring to FIG. 4, the dielectric layer 16 is disposed on the substrate 20, and the dielectric layer 16 surround the nitride-based semiconductor die 11. The dielectric layer 16 covers the rest of the carrier surface 200 of the substrate 20 that is not covered by the nitride-based semiconductor die 11. For example, the nitride-based semiconductor circuit 1A of this embodiment has two nitride-based semiconductor dies 11, and the dielectric layer 16 is disposed among the nitride-based semiconductor dies 11.

To be specific, the dielectric layer 16 covers part of the carrier surface 200 of the substrate 20, and the dielectric layer 16 covers the side surfaces 117 of the nitride-based semiconductor die 11. The dielectric layer 16 exposes the surfaces 116 of the nitride-based semiconductor die 11, and the surfaces 116 of the nitride-based semiconductor die 11 and a top surface 160 of the dielectric layer 16 are coplanar.

Referring to FIG. 5, the nitride-based semiconductor die 11 is etched. To be specific, the step has a dry etching process, and the cavity structure 112 is formed in the substrate 113. The cavity structure 112 is concave from the surface 116.

Furthermore, in this embodiment, the step of etching the nitride-based semiconductor die 11 comprises: etching the middle part of the nitride-based semiconductor die 11. Since the middle part of the nitride-based semiconductor die 11 is etched, the cavity structure 112 has the cavity 1120 and the sidewall 1121 surrounding the cavity 1120, and the thickness of the sidewall 1121 can be unified. The cavity 1120 occupies most of the volume of the substrate 113, and, therefore; an electrical passageway with low resistance is formed.

In one aspect, in this embodiment, after the step of etching the nitride-based semiconductor die 11, the manufacturing method comprises: filling the cavity structure 112 with the filling 14. To be specific, the filling 14 is disposed in the cavity 1120 of the cavity structure 112. The filling 14 is solidify and has a top surface 140, and the top surface 140, the surface 116 of the nitride-based semiconductor die 11, and the top surface 160 of the dielectric layer 16 are coplanar. The filling 14 has low electrical resistance, and the filling 14 provide a firm structural base. Therefore, the filling 14 can provide an electrical passageway with low resistance, and other component may be disposed thereon.

In this embodiment, after the nitride-based semiconductor die 11 is etched, the manufacturing method comprises: disposing the carrier layer 12 on the nitride-based semiconductor die 11. The following will describe the detailed description about the step with reference of FIGS. 6, 7, 8, and 9.

Referring to FIG. 6, the carrier layer 12 has a surface 121, a surface 122, and a side surface 123. The surface 121 and the surface 122 are opposite, and the side surface 123 connects the surface 121 and the surface 122. The surface 121 and the surface 121 are plane.

Referring to FIG. 7, the surface 121 of the carrier layer 12 is etched, and the cavity structure 120 is formed. To be specific, in this embodiment, before disposing the carrier layer 12 on the nitride-based semiconductor die 11, the manufacturing method of the nitride-based semiconductor die 11 comprises: etching the carrier layer 12 and form the cavity structure 120. The cavity structure 120 has the cavity 1200 and the sidewall 1201 surrounding the cavity 1200. The cavity 1200 is concaved from the surface 121, and the sidewall 1201 is vertical. The material of the cavity structure 120 includes silicon or material with dielectric constant that is lower than 11, and, therefore; the cavity structure 120 may provide an electrical passageway with low resistance.

Referring to FIG. 8, the cavity structure 120 is filled with the filling 14. To be specific, in this embodiment, the manufacturing method of the nitride-based semiconductor die 11 comprises: filling the cavity structure 120 with the filling 14. The filling 14 fills the cavity 1200 of the cavity structure 120, and the sidewall 1121 limits the location of the filling 14. The filling 14 has low resistance, and, therefore; the cavity structure 120 filled with the filling 14 may provide electrical passageway with low resistance.

Also, a top surface 141 of the filling 14 and the surface 121 of the carrier layer 12 are coplanar, and, therefore; the carrier layer 12 may combine with the nitride-based semiconductor die 11 having the cavity structure 112 filled with the filling 14.

Referring to FIG. 9, the carrier layer 12 is disposed on the nitride-based semiconductor die 11. In this embodiment, the surface 121 of the carrier layer 12 and the top surface 160 of the dielectric layer 16 are connected, and the surface 121 covers the surface 116 of the nitride-based semiconductor die 11. The cavity structure 112 and the cavity structure 120 are combined, and the filling 14 in the cavity structure 112 and the filling 14 in the cavity structure 120 are combined. Therefore, the

cavity structures

112, 120 can form an electrical passageway with low resistance.

To be specific, in this embodiment, after the step of etching the nitride-based semiconductor die 11, the manufacturing method comprises: enclosing the cavity structure 112 of the nitride-based semiconductor die 11 with the carrier layer 12. In other words, the carrier layer 12 covers the cavity structure 112 of the nitride-based semiconductor die 11 with the cavity structure 120. The cavity structure 112 and the cavity structure 120 surround an accommodating space, and the accommodating space is filled with filling 14. The

cavity structures

112, 120 can provide a passageway with low resistance, and the

cavity structures

112, 120 provide a structural support, and components may be disposed on the surface 122 of the carrier layer 12.

In this embodiment, after the carrier layer 12 is disposed, the manufacturing method comprises: disposing the antenna structures 13 (as shown in FIG. 1) over the carrier layer 12. The following will describe the detailed description about the step with reference of FIGS. 10, and 11.

Referring to FIG. 10, the vias 15 are disposed around the nitride-based semiconductor dies 11 and the cavity structures 120. To be specific, in this embodiment, the step of disposing the antenna structures 13 as shown in FIG. 1 comprises disposing the vias 15 around the nitride-based semiconductor dies 11.

In this embodiment, the carrier layer 12 and the dielectric layer 16 are etched and a plurality of openings are formed, and the vias 15 are disposed in these openings. Therefore, the vias 15 pass through the dielectric layer 16 and the carrier layer 12.

Referring to FIG. 11, the antenna structures 13 are disposed over the carrier layer 12. The carrier layer 12 exposes the vias 15, and the antenna structures 13 are disposed on the vias 15 respectively. Since the vias 15 are disposed around the nitride-based semiconductor dies 11, the antenna structures 13 may cover the periphery of the nitride-based semiconductor die 11. To be specific, the antenna structures 13 cover the periphery of the cavity structure 120 of the carrier layer 12 and the periphery of the cavity structure 112 of the nitride-based semiconductor die 11.

In this embodiment, after the vias 15 are disposed, the manufacturing method comprises: covering the carrier layer 12 with the passivation layer 18. The passivation layer 18 also form a structural support to the antenna structures 13, and, therefore; the antenna structures 13 can be properly disposed on the carrier layer 12.

Furthermore, the passivation layer 18 has a plurality of conductive structures 180. Every conductive structure 180 connects one of the vias 15 to one of the antenna structures 13, and the antenna structures 13 are electrically connected to the vias 15 respectively.

In this embodiment, after the antenna structures 13 are disposed, the manufacturing method of the nitride-based semiconductor circuit 1A comprises: disposing a substrate 21 on the antenna structures 13.

Referring to FIG. 12, the substrate 21 is disposed on the antenna structures 13. To be specific, while the nitride-based semiconductor die 11 is located below the antenna structures 13, the antenna structures 13 have top surfaces 130 at the top. The top surfaces 130 of the antenna structures 13 are covered by the substrate 21, and the nitride-based semiconductor die 11 is located between the substrate 20 and the substrate 21.

In this embodiment, after the substrate 21 is disposed on the antenna structures 13, the manufacturing method of the nitride-based semiconductor circuit 1A comprises: flipping the nitride-based semiconductor die 11 and removing the substrate 20.

Referring to FIG. 13, the nitride-based semiconductor die 11 is flipped, and the substrate 20 as shown in FIG. 12 is removed. The antenna structures 13 are located between the carrier layer 12 and the substrate 21. The carrier layer 12 is located between the nitride-based semiconductor die 11 and the antenna structures 13. The surface 115 of the nitride-based semiconductor die 11 is exposed, and the connecting pads 118 are exposed by the surface 115. The connecting pads 118 are located at the top of the nitride-based semiconductor die 11, while the substrate 21 connecting the antenna structures 13 are located below the nitride-based semiconductor die 11. Moreover, the vias 15 are also exposed, and the top surfaces of the vias and the top surfaces of the connecting pads 118 and the surface 115 are coplanar.

In this embodiment, after the substrate 20 is removed, the manufacturing method comprises: disposing the conductive layer 10 over the nitride-based semiconductor die 11.

Referring to FIG. 14, the conductive layer 10 is disposed over the nitride-based semiconductor die 11. To be specific, the conductive layer 10 has a plurality of conductive structures 100, a redistribution layer 102, a plurality of connecting pads 104, a plurality of connecting pads 106, and a plurality of connecting bumps 107. The conductive structures 100, the redistribution layer 102, the connecting pads 104, the connecting pads 106, and the connecting bumps 107 are made of electrically conductive material. The conductive structures 100 are embedded in a dielectric material 101, and the conductive structures 100 are disposed on the connecting pads 118 of the nitride-based semiconductor die 11 and the vias 15. The redistribution layer 102 is embedded in a dielectric material 103, and the redistribution layer 102 is disposed on the conductive structures 100. The connecting pads 104 are disposed on the redistribution layer 102, and the connecting pads 104 are embedded in a dielectric material 105. The connecting pads 106 are disposed on the connecting pads 104 respectively, and the connecting pads 106 are bigger than the connecting pads 104. The connecting bumps 107 are disposed on the connecting pads 106 respectively, so as to provide electrical connection to the external circuits.

The redistribution layer 102 is electrically connected to the vias 15 and the nitride-based semiconductor die 11 through the conductive structures 100. The connecting bumps 107 are electrically connected to the redistribution layer 102 through the connecting pads 104 and the connecting pads 106, and the connecting bumps 107 are electrically connected to the nitride-based semiconductor die 11 and the antenna structures 13.

In this embodiment, after the conductive layer 10 is disposed, the manufacturing method comprises: removing the substrate 21. Referring to FIG. 15, the substrate 21 as shown in FIG. 14 is removed, and the nitride-based semiconductor circuit 1A is formed. The carrier layer 12 is disposed between the antenna structures 13 and the nitride-based semiconductor die 11, and the nitride-based semiconductor die 11 is disposed between the conductive layer 10 and the carrier layer 12. The cavity structure 112 of the nitride-based semiconductor die 11 is facing towards the carrier layer 12, and the cavity structure 120 of carrier layer 12 is facing towards the nitride-based semiconductor die 11. The cavity structure 112 and the cavity structure 120 are connected, and the

cavity structures

112, 120 form an accommodating space together. The accommodating space is located between the antenna structures 13 and the conductive layer 10. Therefore, the resistance between the antenna structures 13 and the conductive layer 10 is reduced, and the bandwidth and the efficiency of the antenna structures 13 are improved. Also, 40%to 60%of the accommodating space are provide by the cavity structure 112 of the nitride-based semiconductor die 11. Therefore, the size of the nitride-based semiconductor circuit 1A is compact while the bandwidth and the efficiency of the antenna structures 13 are improved.

FIG. 16 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. Referring to FIG. 16, the nitride-based semiconductor circuit 1B is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1, and the same components will be denoted with the same reference characters, and the detailed description will not be repeated. The nitride-based semiconductor circuit 1B has a conductive layer 10, a nitride-based semiconductor die 11, a carrier layer 12, and a plurality of antenna structures 13. The nitride-based semiconductor die 11 is disposed over the conductive layer 10, and the carrier layer 12 is disposed on the nitride-based semiconductor die 11, and the antenna structures 13 are disposed over the carrier layer 12. The antenna structures 13 are electrically connected to the conductive layer 10.

In this embodiment, the nitride-based semiconductor die 11B has a nitride-based semiconductor layer 110, a nitride-based semiconductor layer 111, and a cavity structure 112. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and the cavity structure 112 is disposed over the nitride-based semiconductor layer 111.

The nitride-based semiconductor die 11B has a substrate 113, and the substrate 113 is disposed on the nitride-based semiconductor layer 111. The cavity structure 112 is formed in the substrate 113, and the carrier layer 12 is disposed on the substrate 113. The cavity structure 120 of the carrier layer 12 and the cavity structure 112 of the nitride-based semiconductor die 11 are connected, and the cavity structure 112 and the cavity structure 120 are filled with air. Since the air has lower resistance than the substrate 113 and the carrier layer 12, the

cavity structures

112, 120 can improve the bandwidth and efficiency of the antenna structures 13. In other words, the substrate 113 having the cavity structure 112 can reduce the resistance by the cavity 1120.

To be specific, the cavity structure 112 has a cavity 1120 and a sidewall 1121, and the sidewall 1121 surrounds the cavity 1120. The cavity 1120 is filled with air. The cavity structure 120 has a cavity 1200 and a sidewall 1201, and the sidewall 1201 surrounds the cavity 1200. The cavity 1200 is filled with air. The sidewall 1201 and the sidewall 1121 preserve the area to be filles with air.

In other words, the cavity structure 112 is a well, and the cavity structure 120 is a well, and the wells are filled with air. Since the cavity 1120, and the cavity 1200 are filled with air, the

cavities

1120, 1200 possess lower resistance, and a passageway with low resistance is provided. Also, the nitride-based semiconductor circuit 1B may have flexibility to have different design, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1B with design that is different from the designs of the nitride-based semiconductor circuits above.

FIG. 17 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. Referring to FIG. 17, the nitride-based semiconductor circuit 1C is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1, and the same components will be denoted with the same reference characters, and the detailed description will not be repeated. The nitride-based semiconductor circuit 1C has a conductive layer 10, a nitride-based semiconductor die 11C, a carrier layer 12, and a plurality of antenna structures 13. The nitride-based semiconductor die 11C is disposed over the conductive layer 10, and the carrier layer 12 is disposed on the nitride-based semiconductor die 11C, and the antenna structures 13 are disposed over the carrier layer 12. The antenna structures 13 are electrically connected to the conductive layer 10.

In this embodiment, the nitride-based semiconductor die 11C has a nitride-based semiconductor layer 110, a nitride-based semiconductor layer 111, and a cavity structure 112C. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and the cavity structure 112C is disposed over the nitride-based semiconductor layer 111. The cavity structure 112C has a plurality of cavities 1120C and a sidewall 1121C surrounding the cavities 1120C. Therefore, the cavity structure 112C can provide more support to the carrier layer 12, and the resistance between the antenna structures 13 and the conductive layer 10 is reduced by the cavities 1120C. Also, the nitride-based semiconductor circuit 1C may have flexibility to have different design, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1C with design that is different from the designs of the nitride-based semiconductor circuits above. To be specific, the manufacturing method of the nitride-based semiconductor circuit 1C is similar to the manufacturing method of the nitride-based semiconductor circuit 1A, and the step of etching the nitride-based semiconductor die 11C comprises: etching the cavities 1120C in a middle area of the nitride-based semiconductor die 11C.

In this embodiment, the nitride-based semiconductor die 11C has a substrate 113C, and the cavity structure 112C is formed in the substrate 113C. The substrate 113C provide an electrical passageway with low resistance, and the substrate 113C provides a structural support to the carrier layer 12.

The cavity structure 120 of the carrier layer 12 is facing towards the cavities 1120C of the cavity structure 112C, and the cavity structure 120 and the cavity structure 112C are connected. To be specific, the cavity structure 120 has the cavity 1200 and the sidewall 1201, and the cavity 1200 and the cavities 1120C are connected, and the sidewall 1121C and the sidewall 1201 are connected. Therefore, the

cavities

1200, 1120C can reduced the resistance between the antenna structures 13 and the conductive layer 10.

Also, the cavity structure 112C and the cavity structure 120 are filled with the filling 14, and the resistance of the filling 14 is lower than the substrate 113C and the carrier layer 12. Therefore, the cavity structure 112C and the cavity structure 120 can provide an electrical passageway with low resistance between the antenna structures 13 and the conductive layer 10. In some other embodiments, the cavity structure 112C and the cavity structure 120 may be filled with air.

FIG. 18 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. Referring to FIG. 18, the nitride-based semiconductor circuit 1D is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1, and the same components will be denoted with the same reference characters, and the detailed description will not be repeated. The nitride-based semiconductor circuit 1D has a conductive layer 10, a nitride-based semiconductor die 11, a carrier layer 12D, and a plurality of antenna structures 13. The nitride-based semiconductor die 11 is disposed over the conductive layer 10, and the carrier layer 12D is disposed on the nitride-based semiconductor die 11, and the antenna structures 13 are disposed over the carrier layer 12D. The antenna structures 13 are electrically connected to the conductive layer 10.

In this embodiment, the nitride-based semiconductor die 11 has a nitride-based semiconductor layer 110, a nitride-based semiconductor layer 111, and a cavity structure 112. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and the cavity structure 112 is disposed over the nitride-based semiconductor layer 111.

The cavity structure 112 has a cavity 1120 and a sidewall 1121 surrounding the cavity 1120, and the cavity 1120 of the cavity structure 112 can reduce the resistance between the antenna structures 13 and the conductive layer 10. To be specific, the nitride-based semiconductor die 11 has a substrate 113, and the cavity structure 112 is formed in the substrate 113. The substrate 113 provides an electrical passageway with low resistance, and the substrate 113 provides a structural support to the carrier layer 12.

The carrier layer 12D has cavity structure 120D. To be specific, the cavity structure 120D comprises a plurality of cavities 1200D, and a sidewall 1201D surrounding the cavities 1200D. The cavity 1120 of the nitride-based semiconductor die 11 and the cavities 1200D of the cavity structure 120D are connected. Therefore, the

cavities

1120, 1200D can reduce the resistance between the antenna structures 13 and the conductive layer 10. Also, the nitride-based semiconductor circuit 1D may have flexibility to have different design, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1D with design that is different from the designs of the nitride-based semiconductor circuits above. To be specific, the manufacturing method of the nitride-based semiconductor circuit 1D is similar to the manufacturing method of the nitride-based semiconductor circuit 1A, and the step of etching the carrier layer 12D comprises: etching the cavities 1200D in the carrier layer 12D.

For example, the cavities 1200D of this embodiment is separated into groups, and the cavities 1200D may be combined with the cavities 1120 of the nitride-based semiconductor dies 11. In other words, the cavity 1120 of every nitride-based semiconductor die 11 may be combined with a group of the cavities 1200D.

Also, the cavity structure 112 and the cavity structure 120D are filled with the filling 14, and the resistance of the filling 14 is lower than the substrate 113 and the carrier layer 12D. Therefore, the cavity structure 112 and the cavity structure 120D can provide an electrical passageway with low resistance between the antenna structures 13 and the conductive layer 10. In some other embodiments, the cavity structure 112 and the cavity structure 120D may be filled with air.

FIG. 19 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. Referring to FIG. 19, the nitride-based semiconductor circuit 1E is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1, and the same components will be denoted with the same reference characters, and the detailed description will not be repeated. The nitride-based semiconductor circuit 1E has a conductive layer 10, a nitride-based semiconductor die 11E, a carrier layer 12E, and a plurality of antenna structures 13. The nitride-based semiconductor die 11E is disposed over the conductive layer 10, and the carrier layer 12E is disposed on the nitride-based semiconductor die 11E, and the antenna structures 13 are disposed over the carrier layer 12E. The antenna structures 13 are electrically connected to the conductive layer 10.

In this embodiment, the nitride-based semiconductor die 11E has a nitride-based semiconductor layer 110, a nitride-based semiconductor layer 111, and a cavity structure 112E. The nitride-based semiconductor layer 111 is disposed on the nitride-based semiconductor layer 110, and the cavity structure 112E is disposed over the nitride-based semiconductor layer 111. The cavity structure 112E has a plurality of cavities 1120E and a sidewall 1121E surrounding the cavities 1120E. Therefore, the cavity structure 112E can provide more support to the carrier layer 12E, and the resistance between the antenna structures 13 and the conductive layer 10 is reduced by the cavities 1120E.

In this embodiment, the nitride-based semiconductor die 11E has a substrate 113E, and the cavity structure 112E is formed in the substrate 113E. The substrate 113E provide an electrical passageway with low resistance, and the substrate 113E provides a structural support to the carrier layer 12E.

Also, the carrier layer 12E has a cavity structure 120E, and the cavity structure 120E has a plurality of cavities 1200E and a sidewall 1201E surrounding the cavities 1200E. Every cavity 1200E is connected to one of the cavities 1120E, and the sidewall 1201E and the sidewall 1121E are connected. Therefore, the carrier layer 12E provide further support between the antenna structures 13 and the nitride-based semiconductor die 11E, and the

cavities

1120E, 1200E can reduce the resistance between the antenna structures 13 and the conductive layer 10. Also, the nitride-based semiconductor circuit 1E may have flexibility to have different design, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1E with design that is different from the designs of the nitride-based semiconductor circuits above. To be specific, the manufacturing method of the nitride-based semiconductor circuit 1E is similar to the manufacturing method of the nitride-based semiconductor circuit 1A, and the step of etching the nitride-based semiconductor die 11E comprises: etching the cavities 1120E in a middle area of the nitride-based semiconductor die 11E, and the step of etching the carrier layer 12E comprises: etching the cavities 1200E in the carrier layer 12E.

For example, the nitride-based semiconductor circuit 1E has two nitride-based semiconductor dies 11E, and the cavities 1200E are separate into groups, and every group of the cavities 1200E is connected to the cavities 1120E of one of the nitride-based semiconductor dies 11E.

Also, the cavity structure 112E and the cavity structure 120E are filled with the filling 14, and the resistance of the filling 14 is lower than the substrate 113E and the carrier layer 12E. Therefore, the cavity structure 112E and the cavity structure 120E can provide an electrical passageway with low resistance between the antenna structures 13 and the conductive layer 10. In some other embodiments, the cavity structure 112E and the cavity structure 120E may be filled with air.

FIG. 20 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. Referring to FIG. 20, the nitride-based semiconductor circuit 1F is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1, and the same components will be denoted with the same reference characters, and the detailed description will not be repeated. The nitride-based semiconductor circuit 1F has a conductive layer 10, a nitride-based semiconductor die 11, a carrier layer 12F, and a plurality of antenna structures 13. The nitride-based semiconductor die 11 is disposed over the conductive layer 10, and the carrier layer 12F is disposed on the nitride-based semiconductor die 11, and the antenna structures 13 are disposed over the carrier layer 12F. The antenna structures 13 are electrically connected to the conductive layer 10.

In this embodiment, the nitride-based semiconductor die 11 has a cavity structure 112, and the carrier layer 12F has a cavity structure 120F. The cavity structure 120F is wider than the cavity structure 112. Therefore, the resistance of the area near the antenna structures 13 is further reduced, and the bandwidth and the efficiency of the antenna structures 13 are further improved.

To be specific, the cavity structure 112 has a cavity 1120 and a sidewall 1121 surrounding the cavity 1120, and the cavity structure 120F has a cavity 1200F and a sidewall 1201F surrounding the cavity 1200F. The cavity 1120 has a width W1, and the cavity 1200F has a width W2, and the width W2 is larger than the width W1. Therefore, the resistance of the area near the antenna structures 13 are further reduced, and the bandwidth and the efficiency of the antenna structures 13 are further improved. Also, the nitride-based semiconductor circuit 1F may have flexibility to have different design, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1F with design that is different from the designs of the nitride-based semiconductor circuits above.

Also, the cavity structure 112 and the cavity structure 120F are filled with the filling 14, and the resistance of the filling 14 is lower than a substrate 113 of the nitride-based semiconductor die 11 and the carrier layer 12F. Therefore, the cavity structure 112 and the cavity structure 120F can provide an electrical passageway with low resistance between the antenna structures 13 and the conductive layer 10. In some other embodiments, the cavity structure 112 and the cavity structure 120F may be filled with air.

FIG. 21 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. Referring to FIG. 21, the nitride-based semiconductor circuit 1G is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1, and the same components will be denoted with the same reference characters, and the detailed description will not be repeated. The nitride-based semiconductor circuit 1G has a conductive layer 10, a nitride-based semiconductor die 11, a carrier layer 12G, and a plurality of antenna structures 13. The nitride-based semiconductor die 11 is disposed over the conductive layer 10, and the carrier layer 12G is disposed on the nitride-based semiconductor die 11, and the antenna structures 13 are disposed over the carrier layer 12G. The antenna structures 13 are electrically connected to the conductive layer 10.

In this embodiment, the nitride-based semiconductor die 11 has a cavity structure 112, and the carrier layer 12G has a cavity structure 120G. The cavity structure 112 is wider than the cavity structure 120G. Therefore, the carrier layer 12G may provide more structural support to the antenna structures 13.

To be specific, the cavity structure 112 has a cavity 1120 and a sidewall 1121 surrounding the cavity 1120, and the cavity structure 120G has a cavity 1200G and a sidewall 1201G surrounding the cavity 1200G. The cavity 1120 has a width W1, and the cavity 1200G has a width W3, and the width W1 is larger than the width W3. Therefore, the carrier layer 12G provide more structural support to the antenna structures 13, while the

cavity structures

120G, 112 may reduce the resistance between the antenna structures 13 and the conductive layer 10. Also, the nitride-based semiconductor circuit 1G may have flexibility to have different design, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1G with design that is different from the designs of the nitride-based semiconductor circuits above.

Also, the cavity structure 112 and the cavity structure 120G are filled with filling 14, and the resistance of the filling 14 is lower than a substrate 113 of the nitride-based semiconductor die 11 and the carrier layer 12G. Therefore, the cavity structure 112 and the cavity structure 120G can provide an electrical passageway with low resistance between the antenna structures 13 and the conductive layer 10. In some embodiments, the cavity structure 112 and the cavity structures 120G may be filled with air.

FIG. 22 is a side sectional view of a nitride-based semiconductor circuit according to some embodiments of the present disclosure. Referring to FIG. 22, the nitride-based semiconductor circuit 1H is similar to the nitride-based semiconductor circuit 1A as shown in FIG. 1, and the same components will be denoted with the same reference characters, and the detailed description will not be repeated. The nitride-based semiconductor circuit 1H has a conductive layer 10, a nitride-based semiconductor die 11, a carrier layer 12H, and a plurality of antenna structures 13. The nitride-based semiconductor die 11 is disposed over the conductive layer 10, and the carrier layer 12H is disposed on the nitride-based semiconductor die 11, and the antenna structures 13 are disposed over the carrier layer 12H. The antenna structures 13 are electrically connected to the conductive layer 10.

In this embodiment, the nitride-based semiconductor die 11 has a cavity structure 112, and the carrier layer 12H has a cavity structure 120H. The top of the cavity structure 120H is wider than the cavity structure 112. The antenna structures 13 are disposed on the top of the cavity structure 120H, and, therefore, the carrier layer 12H may reduce more resistance of the area near the antenna structures 13.

To be specific, the cavity structure 112 has a cavity 1120 and a sidewall 1121 surrounding the cavity 1120, and the cavity structure 120H has a cavity 1200H and a sidewall 1201H surrounding the cavity 1200H. The sidewall 1121 is vertical, and the sidewall 1201H is oblique. The top of the cavity 1200H has a width W2, and the bottom of the cavity 1200H and the cavity 1120 have a width W1, and the width W2 is larger than the width W1. Therefore, the carrier layer 12H further reduced the resistance of the area near the antenna structures 13. Also, the nitride-based semiconductor circuit 1H may have flexibility to have different design, and the manufacturing method of the present disclosure may have the flexibility to make the nitride-based semiconductor circuit 1H with design that is different from the designs of the nitride-based semiconductor circuits above.

Also, the cavity structure 112 and the cavity structure 120H are filled with filling 14, and the resistance of the filling 14 is lower than a substrate 113 of the nitride-based semiconductor die 11 and the carrier layer 12H. Therefore, the cavity structure 112 and the cavity structure 120H can provide an electrical passageway with low resistance between the antenna structures 13 and the conductive layer 10. In some embodiments, the cavity structure 112 and the cavity structures 120H may be filled with air.

The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor circuit comprising:

a conductive layer;

a nitride-based semiconductor die disposed over the conductive layer;

a carrier layer disposed on the nitride-based semiconductor die; and

a plurality of antenna structures disposed over the carrier layer;

wherein the nitride-based semiconductor die comprises:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap less than a bandgap of the first nitride-based semiconductor layer; and

a first cavity structure disposed over the second nitride-based semiconductor layer;

wherein the antenna structures are electrically connected to the conductive layer;

wherein the carrier layer has a second cavity structure, and the second cavity structure and the first cavity structure are connected.
The nitride-based semiconductor circuit of claim 1 further comprising a filling, and the filling fills the first cavity structure and the second cavity structure.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein materials of the filling comprise foam material with low dielectric constant.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the first cavity structure comprises:

a first cavity; and

a first sidewall surrounding the cavity.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the first sidewall is vertical.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the second cavity structure comprises:

a second cavity; and

a second sidewall surrounding the cavity.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the second sidewall is vertical.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the first cavity structure comprises:

a first cavity; and

a first sidewall surrounding the cavity,

and the first sidewall and the second sidewall are continuously connected.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the first cavity structure comprises:

a plurality of first cavities; and

a first sidewall surrounding the first cavities.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the second cavity structure comprises:

a plurality of second cavities; and

a second sidewall surrounding the second cavities.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the first cavity structure is wider than the second cavity structure.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the second cavity structure is wider than the first cavity structure.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein part of the first cavity structure is located between the antenna structures and the conductive layer, and part of the second cavity structure is located between the antenna structures and the conductive layer.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the antenna structures cover a periphery of the first cavity structure of the nitride-based semiconductor die, and the antenna structures cover a periphery of the second cavity structure of the carrier layer.
The nitride-based semiconductor circuit of any one of the preceding claims, wherein the first cavity structure and the second cavity structure are filled with air.
A manufacturing method of nitride-based semiconductor circuit, comprising:

disposing a nitride-based semiconductor die on a first substrate;

etching the nitride-based semiconductor die and form a first cavity structure;

disposing a carrier layer on the nitride-based semiconductor die;

disposing a plurality of antenna structures over the carrier layer;

disposing a second substrate on the antenna structures;

flipping the nitride-based semiconductor die and removing the first substrate;

disposing a conductive layer over the nitride-based semiconductor die; and

removing the second substrate;

wherein the nitride-based semiconductor die comprises:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap less than a bandgap of the first nitride-based semiconductor layer; and

the first cavity structure disposed over the second nitride-based semiconductor layer;

wherein the antenna structures are electrically connected to the conductive layer;

wherein the carrier layer has a second cavity structure, and the second cavity structure and the first cavity structure are connected.
The manufacturing method of claim 16 further comprising:

etching the carrier layer and form the second cavity structure.
The manufacturing method of any one of the preceding claims, wherein the step of etching the nitride-based semiconductor die comprises:

etching the middle part of the nitride-based semiconductor die.
The manufacturing method of any one of the preceding claims, wherein the step of etching the nitride-based semiconductor die comprises:

etching a plurality of cavities in a middle area of the nitride-based semiconductor die.
The manufacturing method of any one of the preceding claims, after the step of etching the nitride-based semiconductor die, further comprising:

enclosing the first cavity structure of the nitride-based semiconductor die with the carrier layer.
A nitride-based semiconductor circuit comprising:

a conductive layer;

a nitride-based semiconductor die disposed over the conductive layer;

a carrier layer disposed on the nitride-based semiconductor die; and

a plurality of antenna structures disposed over the carrier layer;

wherein the nitride-based semiconductor die comprises:

a first nitride-based semiconductor layer;

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap less than a bandgap of the first nitride-based semiconductor layer; and

a first well disposed over the second nitride-based semiconductor layer;

wherein the antenna structures are electrically connected to the conductive layer;

wherein the carrier layer comprises a second well, and the second well covers the first well of the nitride-based semiconductor die, and an opening of the second well and an opening of the first well are connected.
The nitride-based semiconductor circuit of claim 21 further comprising a filling, wherein the filling fills the first well and the second well.
The nitride-based semiconductor circuit any one of the preceding claims, wherein the carrier layer encloses the first well of the nitride-based semiconductor die.
The nitride-based semiconductor circuit any one of the preceding claims, wherein the first well and the second well are filled with air.
The nitride-based semiconductor circuit any one of the preceding claims, wherein bottoms of the first well and the second well and an interface between the nitride-based semiconductor die and the conductive layer are parallel.