WO2024092612A1

WO2024092612A1 - Semiconductor packaged structure and method for manufacturing thereof

Info

Publication number: WO2024092612A1
Application number: PCT/CN2022/129528
Authority: WO
Inventors: Ergang Xu; Kai Cao; Lei Zhang
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-11-03
Filing date: 2022-11-03
Publication date: 2024-05-10

Abstract

A semiconductor package device includes a die carrier, a first die, a second die, a third die, a first conductive pillar, and a second conductive pillar. The die carrier defines a cavity. The first die is disposed in the cavity. The second die is disposed in the cavity and over the first die. The first die comprises a first pad and a bonding wire. The second die comprises a second pad electrically connected with the first pad via the bonding wire. The third die is disposed in the cavity and over the second die and comprises a third pad. The first conductive pillar is disposed on the second pad. The second conductive pillar is disposed on the third pad.

Description

SEMICONDUCTOR PACKAGED STRUCTURE AND METHOD FOR MANUFACTURING THEREOF

Inventors: Ergang XU; Kai CAO; Lei ZHANG

Field of the Invention:

The present invention generally relates to a semiconductor packaged structure. More specifically, the present invention relates to a III-nitride-based semiconductor packaged structure having dies which are stacked by a spacing less than width thereof.

Background of the Invention:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Invention:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The semiconductor package device includes a die carrier, a first die, a second die, a third die, a first conductive pillar, and a second conductive pillar. The die carrier defines a cavity. The first die is disposed in the cavity. The second die is disposed in the cavity and over the first die. The first die comprises a first pad and a bonding wire. The second die comprises a second pad electrically connected with the first pad via the bonding wire. The third die is disposed in the cavity and over the second die and comprises a third pad. The first conductive pillar is disposed on the second pad. The second conductive pillar is disposed on the third pad.

In accordance with one aspect of the present disclosure, a manufacturing method of the semiconductor device is provided. The method include step as follows: disposing a carrier substrate over a carrier wafer; forming a cavity in the carrier substrate; positioning a first die in the cavity; positioning a second die in the cavity and over the first die; positioning a third die in the cavity and over the second die; forming a first encapsulant to fill up the cavity and encapsulate the first die, the second die, and the third die; and forming a redistribution layer (RDL) over the first die, the second die, and the third die.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The semiconductor package device includes a die carrier, a first die, and a second die. The die carrier defines a cavity. The first die is disposed in the cavity. The second die is disposed in the cavity and over the first die. The first die comprises a first pad and a bonding wire. The second die comprises a second pad electrically connected with the first pad via the bonding wire. An overlapping width between the first die and the second die along a vertical direction is less than a width of the first die.

By applying the above configuration, the dies can be packaged in the die carrier by using vertically stack and horizontally shift, which is advantageous to improve the package dimension flexibility effectively. As such, the overlapping area between the two adjacent dies is less than the single die width, such that the less area is used for connection so the warpage can get reduced.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a cross-sectional view of a semiconductor packaged structure according to some embodiments of the present disclosure; and

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G and FIG. 2H show different stages of a method for manufacturing a semiconductor packaged structure 1A according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a cross-sectional view of a semiconductor packaged structure 1A according to some embodiments of the present disclosure. The semiconductor packaged structure 1A may be a III-nitride-based semiconductor packaged structure. The semiconductor packaged structure 1A may include III-nitride-based dies, which involve with GaN, AlN, InN and various mixtures thereof such as AlGaN, InAlGaN and InAlN with various ratios of metal elements in the nitrides. The semiconductor packaged structure 1A includes

pads

20, 22, conductive pillars 24, an encapsulant 30, a die carrier 40, dies 42, 44, 46, 48, an encapsulant 50, pad54, an isolation layer 56, pads 58, a protection layer 60, and solder balls 62.

The die carrier 40 can define a cavity. More specifically, the die carrier 40 has a bottom and a sidewall connected to the bottom. The sidewall can enclose or surround the cavity so the die carrier 40 can have accommodation space therein. The die carrier 40 may have silicon. The die carrier 40 may formed by removing a portion of a silicon substrate.

In some embodiments, the dies 42, 44, 46, 48 may include at least one III-nitride-based transistor therein. Herein, the III-nitride-based transistor can include two nitride-based semiconductor layers which can serve a channel layer and a barrier layer, two or more source/drain (S/D) electrodes, and at least one gate electrode. The exemplary materials of the nitride-based semiconductor layers can include, for example but are not limited to, nitrides or group III-nitrides, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1. The exemplary materials of the nitride-based semiconductor layers are selected such that the upper nitride-based semiconductor layer has a bandgap (i.e., forbidden band width) greater than a bandgap of the lower nitride-based semiconductor layer, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the lower nitride-based semiconductor layer is an undoped GaN layer having bandgap of approximately 3.4 eV, the upper nitride-based semiconductor layer can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. The S/D electrodes and the gate electrode can be disposed above the 2DEG. Accordingly, the dies 42, 44, 46, 48 are available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The dies 42, 44, 46, 48 are disposed in the cavity of the die carrier 40. The dies 42, 44, 46, 48 are positioned in the cavity of the die carrier 40. The die 44 is disposed over the die 42. The die 46 is disposed over the die 44. The die 48 is disposed over the die 46. The dies 42, 44, 46, 48 are stacked over the bottom of the die carrier 40 in sequence. The dies 42, 44, 46, 48 are positioned with a horizontal shift in sequence. For example, a distance from a left edge of the die carrier 40 to the die 42 is less than the left edge of the die carrier 40 to the die 44; a distance from a left edge of the die carrier 40 to the die 42 is less than the left edge of the die carrier 40 to the die 46; and a distance from a left edge of the die carrier 40 to the die 46 is less than the left edge of the die carrier 40 to the die 48.

The die 42 is closest to a left border of the sidewall among the dies 42, 44, 46, 48. The die 42 is closest to the bottom of the die carrier 40 among the dies 42, 44, 46, 48. The die 42 is attached to the bottom of the die carrier 40. The die 42 includes pads 422 at a top surface thereof. The configuration of the pads 422 is off a center axis of the die 42. For example, the left edge of the die 42 is closer to the symmetry center of the pads 422 than the right edge of the die 42. As such, the die 42 can have the top surface which has an open area for loading another component.

The die 44 is separated from the bottom of the die carrier 40. The die 44 is attached to the top surface of the die 42. In some embodiments, a contact interface between the dies 42 and 44 is in non-conductive so no carrier will pass through the contact interface therebetween. An overlapping width between the dies 42 and 44 along a vertical direction is less than a width of the die 42 or 44. The pads 422 of the die 42 horizontally overlap with the die 44. The die 44 includes pads 442 at a top surface thereof. The configuration of the pads 442 is off a center axis of the die 44. The die 42 further includes bonding wires extending from the pads 422 to the pads 442. The pads 422 can be electrically connected with the pads 442 via the bonding wires. The reason for the use of the bonding wires of the die 42 is that the dies 42 is the bottom one of the dies 42, 44, 46, 48, so positioning of conductive pillars with respect to the dies 42 may fail in practical situations.

The die 46 is separated from the bottom of the die carrier 40. The die 46 is attached to the top surface of the die 44. In some embodiments, a contact interface between the dies 44 and 46 is in non-conductive so no carrier will pass through the contact interface therebetween. An overlapping width between the dies 44 and 46 along a vertical direction is less than a width of the die 44 or 46. The pads 442 of the die 44 horizontally overlap with the die 46. The die 46 includes pads 462 at a top surface thereof. The configuration of the pads 462 is off a center axis of the die 46.

The die 48 is separated from the bottom of the die carrier 40. The die 48 is attached to the top surface of the die 46. In some embodiments, a contact interface between the dies 46 and 48 is in non-conductive so no carrier will pass through the contact interface therebetween. An overlapping width between the dies 46 and 48 along a vertical direction is less than a width of the die 46 or 48. The pads 462 of the die 46 horizontally overlap with the die 48. The die 48 includes pads 482 at a top surface thereof. The configuration of the pads 482 is off a center axis of the die 48.

The semiconductor packaged structure 1A includes conductive pillars connected to the

pads

442, 462, 482. The conductive pillars are disposed on the

pads

442, 462, 482 respectively. The conductive pillars longitudinally extend from the

pads

442, 462, 482. The conductive pillars connected to the pads 442 are longer than the conductive pillars connected to the pads 462. The conductive pillars connected to the pads 462 are longer than the conductive pillars connected to the pads 482. The conductive pillars connected to the pads 442 are parallel with the conductive pillars connected to the pads 462. The conductive pillars connected to the pads 462 are parallel with the conductive pillars connected to the pads 482.

The encapsulant 50 is disposed within the cavity of the die carrier 40. The encapsulant 50 can encapsulate the dies 42, 44, 46, 48. The encapsulant 50 can fill up the cavity of the die carrier 40. Bottom surfaces of the dies 44, 46, 48 can be covered by the encapsulant 50. The conductive pillars connected to the

pads

442, 462, 482 can penetrate the encapsulant 50. The conductive pillars connected to the

pads

442, 462, 482 are free from coverage of the encapsulant 50. In some embodiments, the encapsulant 50 can be formed by driving an encapsulant compound and then curing the encapsulant compound. In some embodiments, the encapsulant compound can include epoxy, fillers, particles, and combinations thereof. In practical cases, the encapsulant 50 may be selected from a molding compound.

The dies 42, 44, 46, 48 can be packaged in the die carrier 40 by using vertically stack and horizontally shift, which is advantageous to improve the package dimension flexibility effectively. Moreover, since the overlapping area between the two adjacent dies is less than the die width, the less area is used for connection so the warpage can get reduced.

The pads 54 and the isolation layer 56 are disposed on the die carrier 40. The pads 54 can be arranged within the isolation layer 56. At least one of the pads 54 is disposed on the encapsulant 50. The pads 54 can be electrically connected to the dies 44, 46, 48 via the conductive pillars. At least one of the pads 54 can make contact with the conductive pillars connected to the dies 44, 46, 48.

The pads 58 are disposed on the isolation layer 56. The pads 58 can be correspondingly connected to the pads 54. The pads 58 can collectively serve as a redistribution layer (RDL) for better access to the pads 58 from the external source. The protection layer 60 is disposed on the isolation layer 56. The protection layer 60 covers the pads 58. Some regions of the pads 58 of the RDL are free from coverage of the protection layer 60. The solder balls 62 can be positioned to make contact with the pads 58 of the RDL. The solder balls 62 can serve as electrical nodes such that an external electrical signal is easily to enter the structure.

The encapsulant 30 can surround or enclose the die carrier 40. At least one of the pads 54 is disposed on the encapsulant 30. In some embodiments, the encapsulant 30 can be formed by using encapsulant compound. In some embodiments, the encapsulant compound can include epoxy, fillers, particles, and combinations thereof. In practical cases, the encapsulant 30 may be selected from a molding compound.

The conductive pillars 24 are disposed out the cavity of the die carrier 40. The conductive pillars 24 can have ends making contact with at least one of the pads 54. The conductive pillars 24 can penetrate the encapsulant 30. The length of the conductive pillars 24 is greater than a thickness of the die carrier 40. The conductive pillars 24 can downward extend to a position deeper than the die carrier 40. The conductive pillars 24 can be formed as being parallel with the conductive pillars connected to the

pads

442, 462, 482.

The

pads

20 and 22 are encapsulated by the encapsulant 30. The pads 22 can make contact with the die carrier 40. The pads 20 can be connected to the pads 22. The conductive pillars 24 can make contact with at least one of the pads 20. As such, the structure has electrical nodes to be connected at a front surface and a back surface. For example, in the exemplary illustration of FIG. 1, the left one of the conductive pillars 24 can act as a part of a longitudinal electrically path so two components which are positioned over and beneath the structure can communicate with each other; and the right one of the conductive pillars 24 can act as a part of an electrically path from at least one of dies 44, 46, 48 to the pads 20 via the RDL so a component which is positioned beneath the structure can communicate with the at least one of dies 44, 46, 48. Furthermore, since there are several electrically paths built in the structure, it means the paths can provide heat dissipation as well.

In some embodiments, the die carrier 40 can include active components therein. For example, the die carrier 40 can include a silicon substrate and active components formed on the silicon substrate. The cavity of the die carrier 40 can be formed by removing a portion of the silicon substrate. The removal is terminated such that only the portion of the silicon substrate is removed. The active components of the die carrier 40 can be kept in the bottom of the die carrier 40. The active components of the die carrier 40 can be electrically coupled to the pads 22 so as to receive an external electrical signal.

Different stages of a method for manufacturing the semiconductor packaged structure 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G and FIG. 2H, as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, pads 20 can be formed on a carrier wafer 70 by using the deposition techniques. Conductive pillars 24 can be formed to extend from the pads 20 by using electroplating manners.

Referring to FIG. 2B, a carrier substrate 80 is disposed over the carrier wafer 70. In some embodiments, pads 22 are formed in contact with the carrier substrate 80. When attaching the carrier substrate 80 to the carrier wafer 70, the pads 22 align with the pads 20, such that the pads 22 can be attached to the pads 20. In some embodiments, the carrier substrate 80 may include a silicon substrate and active components formed on the silicon substrate, as afore mentioned.

Referring to FIG. 2C, an encapsulant 30 can be formed by driving an encapsulant compound and then curing the encapsulant compound. The encapsulant 30 can fill at least one gap between the carrier wafer 70 and the carrier substrate 80. In some embodiments, after curing the encapsulant compound, some of the encapsulant compound are removed so the conductive pillars 24 are exposed from the encapsulant 30.

Referring to FIG. 2D, a portion of the carrier substrate 80 is removed so a cavity 402 is formed in the carrier substrate 80. After the removal, the carrier substrate 80 can become a die carrier 40 with the cavity 402. In some embodiments, the removal includes an etching process. Specifically, a mask can be formed on the structure and a desired area to be removed is exposed from the mask.

Referring to FIG. 2E, dies 42, 44, 46, 48 are disposed over the die carrier 40. The die 42 is positioned in the cavity 402. The die 44 is positioned in the cavity 402 and over the die 42. The die 46 is positioned in the cavity 402 and over the die 44. The die 48 is positioned in the cavity 402 and over the die 46. In some embodiments, at least one adhesive is used when positioning of the dies 42, 44, 46, 48. In this stage, bonding wires from the die 42 to the die 44 and conductive pillars connected to the dies 44, 46, 48 are in the cavity 402 as well.

Referring to FIG. 2F, an encapsulant 50 is formed to fill up the cavity of the die carrier 40. The encapsulant 50 encapsulates the dies 42, 44, 46, 48. In some embodiments, the encapsulant 50 can be formed by driving an encapsulant compound and then curing the encapsulant compound. In some embodiments, after curing the encapsulant compound, some of the encapsulant compound are removed so the conductive pillars connected to the dies 44, 46, 48 are exposed from the encapsulant 50.

Referring to FIG. 2G, pads 54 and an isolation layer 56 are formed over the encapsulant 50. Referring to FIG. 2H, a redistribution layer including pads 58 and a protection 60 is formed over the isolation layer 56. The RDL is located over the dies 42, 44, 46, 48. Thereafter, solder balls 62 are formed to make contact with the pads 58 of the RDL.

After the formation of the solder balls 62, the carrier wafer 70 can be thinned. In some embodiments, the carrier wafer 70 can be thinned until an entirety of the carrier wafer 70 is removed, such that pads 20 are exposed. In some embodiments, the carrier wafer 70 can be thinned until a desired thickness of the carrier wafer 70 is achieved. In some embodiments, the carrier wafer 70 may includes a dissipation substrate, so at least one electrical path directed to the carrier wafer 70 can transmit heat to the carrier wafer 70 for dissipation.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A semiconductor package device, comprising:

a die carrier defining a cavity;

a first die disposed in the cavity;

a second die disposed in the cavity and over the first die, wherein the first die comprises a first pad and a bonding wire, and the second die comprises a second pad electrically connected with the first pad via the bonding wire;

a third die disposed in the cavity and over the second die and comprising a third pad;

a first conductive pillar disposed on the second pad; and

a second conductive pillar disposed on the third pad.
The semiconductor package device of any one of the preceding claims, wherein a contact interface between the first die and the second die is in non-conductive.
The semiconductor package device of any one of the preceding claims, wherein a contact interface between the second die and the third die is in non-conductive.
The semiconductor package device of any one of the preceding claims, wherein the die carrier has a sidewall, and the first die is closest to the sidewall among the first die, the second die, and the third die.
The semiconductor package device of any one of the preceding claims, wherein the second die and the third die are separated from a bottom of the die carrier.
The semiconductor package device of any one of the preceding claims, wherein the second die is attached to a top surface of the first die.
The semiconductor package device of any one of the preceding claims, further comprising:

a first encapsulant disposed within the cavity of the die carrier and encapsulating the first die, the second die, and the third die.
The semiconductor package device of any one of the preceding claims, wherein the first encapsulant fills up the cavity of the die carrier.
The semiconductor package device of any one of the preceding claims, further comprising a second encapsulant surrounding the die carrier.
The semiconductor package device of any one of the preceding claims, wherein the first conductive pillar and the second pillar penetrate the first encapsulant and are free from coverage of the first encapsulant.
The semiconductor package device of any one of the preceding claims, wherein bottom surfaces of the second die and the third die are covered by the first encapsulant.
The semiconductor package device of any one of the preceding claims, wherein an overlapping width between the first die and the second die along a vertical direction is less than a width of the first die.
The semiconductor package device of any one of the preceding claims, wherein the first pad horizontally overlaps with the second die.
The semiconductor package device of any one of the preceding claims, wherein the first conductive pillar is parallel with the second conductive pillar.
The semiconductor package device of any one of the preceding claims, further comprising:

a third conductive pillar disposed out the cavity of the die carrier and is parallel with the first conductive pillar and the second conductive pillar.
A manufacturing method of the semiconductor device, comprising:

disposing a carrier substrate over a carrier wafer;

forming a cavity in the carrier substrate;

positioning a first die in the cavity;

positioning a second die in the cavity and over the first die;

positioning a third die in the cavity and over the second die;

forming a first encapsulant to fill up the cavity and encapsulate the first die, the second die, and the third die; and

forming a redistribution layer (RDL) over the first die, the second die, and the third die.
The manufacturing method of any one of the preceding claims, further comprising:

forming a second encapsulant encapsulating the carrier substrate prior to forming the cavity in the carrier substrate.
The manufacturing method of any one of the preceding claims, wherein an overlapping width between the first die and the second die along a vertical direction is less than a width of the first die.
The manufacturing method of any one of the preceding claims, wherein a contact interface between the first die and the second die is in non-conductive.
The manufacturing method of any one of the preceding claims, wherein the carrier substrate has a sidewall, and the first die is closest to the sidewall among the first die, the second die, and the third die.
A semiconductor package device, comprising:

a die carrier defining a cavity;

a first die disposed in the cavity; and

a second die disposed in the cavity and over the first die, wherein the first die comprises a first pad and a bonding wire, and the second die comprises a second pad electrically connected with the first pad via the bonding wire, wherein an overlapping width between the first die and the second die along a vertical direction is less than a width of the first die.
The semiconductor package device of any one of the preceding claims, wherein a contact interface between the first die and the second die is in non-conductive.
The semiconductor package device of any one of the preceding claims, further comprising:

a third die disposed in the cavity and over the second die.
The semiconductor package device of any one of the preceding claims, wherein a contact interface between the second die and the third die is in non-conductive.
The semiconductor package device of any one of the preceding claims, wherein the carrier substrate has a sidewall, and the first die is closest to the sidewall among the first die, the second die, and the third die.