JP2022186602A - 濡れ性側面付きパッケージ構造、その製造方法、及び垂直パッケージモジュール - Google Patents
濡れ性側面付きパッケージ構造、その製造方法、及び垂直パッケージモジュール Download PDFInfo
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- JP2022186602A JP2022186602A JP2022073061A JP2022073061A JP2022186602A JP 2022186602 A JP2022186602 A JP 2022186602A JP 2022073061 A JP2022073061 A JP 2022073061A JP 2022073061 A JP2022073061 A JP 2022073061A JP 2022186602 A JP2022186602 A JP 2022186602A
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Abstract
Description
本発明の上記及び/又は付加的な態様、及び利点は、以下の図面を参照しながら実施例を説明することにより、明らかになりかつ理解しやすくなる。
図1及び図2を参照すると、本実施例は、第1誘電体層110と、チップ200(マイクロ回路、マイクロチップ又は集積回路とも呼ばれる)と、配線層300とを含む濡れ性側面付きパッケージ構造を開示する。第1誘電体層110の材料はガラス繊維布、高分子重合体又はセラミック材料のうちの少なくとも1種である。第1誘電体層110にはパッケージキャビティ101が設けられ、具体的には、パッケージキャビティ101は第1誘電体層110の中央部に位置し、第1誘電体層110の側壁であってパッケージキャビティ101の外側に第1側壁パッド120が設けられ、第1側壁パッド120の数は、チップ200の活性面におけるピン201の数及び実際の配線のニーズに応じて決定される。チップ200はパッケージキャビティ101内にパッケージされ、且つチップ200の活性面におけるピン201は第1誘電体層110の第1面に面しており、ここで、チップ200をパッケージするためのパッケージ材料103は、味の素株式会社製のビルドアップ材料、重合体基質を有する材料、感光性絶縁材料、パッケージ成形コンパウンドやポリイミドなどであってもよい。パッケージ材料103によってチップ200をパッケージキャビティ101内に包み、且つチップ200の一部はパッケージ材料103から露出し、これにより、電気的接続や放熱可能な接続が実現される。図1、図3及び図4を参照すると、配線層300は第1誘電体層110の第1面に設けられ、配線層300は第1側壁パッド120及びチップ200の活性面におけるピン201に直接又は間接的に接続され、第1側壁パッド120とチップ200の活性面におけるピン201との間の電気的接続を可能とする。なお、ピン201は第1誘電体層110の2つの対向する面のうちのいずれかに面してもよいが、説明の便宜上、本発明の実施例では、ピン201の向きを基準として、第1誘電体層110の第1面を特定し、即ち、第1誘電体層110のうちピン201が面している面を第1面とする。
本発明の実施例は、ステップS100、ステップS200、ステップS300、及びステップS400を含むパッケージ構造の製造方法を提供し、以下、各ステップについて詳細に説明する。
図17を参照すると、チップ200の活性面におけるピン201が第1仕掛け品の第1面に面しており且つチップ200の放熱面が第1仕掛け品に埋設されたときに、第1仕掛け品の第2面に、チップ200の放熱面に連通する第2導通孔105を開ける。本実施例では、チップ200の放熱面はチップ200の裏面に位置し、チップ200の放熱面及びチップ200の活性面におけるピン201はそれぞれチップ200の対向する両面に位置する。
図19又は図20を参照すると、第1仕掛け品に第1表面保護層510を付与して、第2仕掛け品を得る。第1表面保護層510は、機械的保護や水蒸気バリアの機能を果たすために、半田レジスト層又はプラスチックパッケージ層としてもよい。放熱層400が加工された場合、パターントランスファープロセス、プラズマエッチングやレーザプロセスによって第1表面保護層510を部分的に除去して、対応する放熱金属を露出させる。ここで、第1表面保護層510のプラスチックパッケージ材料はパッケージ材料103であってもよい。
本発明の実施例は、実施例2のパッケージ構造の製造方法によって得られるパッケージ構造を開示する。従来のパッケージ構造に比べて、本発明の実施例では、チップ200のピン201を介して配線層300を引き出すことによって、ボンディングワイヤや金属バンプを省略し、パッケージ体積を減少させ、電気信号の伝達距離を短くし、パッケージ構造の小型化、及び電気信号伝達の損失や遅延の最適化に有利である。さらに、本実施例では、第1側壁パッド120が設けられることにより、単位面積あたりのパッケージ構造により多くのパッドを配置することが可能になり、これにより、増えつつあるI/Oの数への要件を満たす。第1側壁パッド120の設計によりパッケージ構造の表面実装、側面実装又は垂直実装が可能になり、各種の場面の実装の要件が満たされ、パッケージ構造の適用性の向上に有利である。使用する際には、第1側壁パッド120に半田が濡れたときに、自動光検出機器を用いて第1側壁パッド120への半田濡れの状況を調べて、半田の品質を判定し、さらにチップ200の半田性能の有効性を判断することができ、関連電子製品の組立後の信頼性を向上させるのに有利であり、自動車グレードの要件を満たすことができる。
本発明の実施例は、実施例1のパッケージ構造又は実施例3のパッケージ構造を含む垂直パッケージモジュールを開示する。本発明の実施例では、チップ200の活性面におけるピン201を介して配線層300を引き出すことによって、ボンディングワイヤや金属バンプを省略し、パッケージ体積を減少させ、電気信号の伝達距離を短くし、パッケージ構造の小型化、及び電気信号伝達の損失や遅延の最適化に有利である。さらに、本実施例では、第1側壁パッド120が設けられることにより、単位面積あたりのパッケージ構造により多くのパッドを配置することが可能になり、これにより、増えつつあるI/Oの数への要件を満たす。第1側壁パッド120の設計によりパッケージ構造の表面実装、側面実装又は垂直実装が可能になり、各種の場面の実装の要件が満たされ、パッケージ構造の適用性の向上に有利である。
図21を参照すると、本発明の実施例は、プリント回路基板700と、パッケージユニット800と、パッケージデバイス810とを含む垂直パッケージモジュールを開示し、パッケージユニット800に第2側壁パッド820が設けられ、パッケージユニット800は第2側壁パッド820を介してプリント回路基板700に溶接され、パッケージユニット800の第1面はプリント回路基板700に垂直であり、パッケージデバイス810は機能エリア811を有し、ここで、機能エリア811は実施例1の機能領域202に対応し、即ち、機能エリア811は、信号送信端、信号接受信端、信号伝達端又は信号検知端として機能してもよく、もちろん、機能エリア811は、信号送信端と信号受信端を集積した信号受送信端としてもよい。機能エリア811は空気に晒されるものであるので、保護材料で被覆されることにより保護されてもよい。
Claims (23)
- 第1誘電体層であって、前記第1誘電体層にパッケージキャビティが設けられ、前記パッケージキャビティの外側である前記第1誘電体層の側壁に第1側壁パッドが設けられる第1誘電体層と、
前記パッケージキャビティ内にパッケージされ、且つ活性面のピンが前記第1誘電体層の第1面に面しているチップと、
前記第1誘電体層の第1面に設けられ、前記第1側壁パッド及び前記チップの活性面におけるピンに直接又は間接的に接続される配線層とを含む、ことを特徴とする濡れ性側面付きパッケージ構造。 - 前記配線層は、前記第1側壁パッドに直接接続される、又は第2導電性ビアポストを介して前記第1側壁パッドに接続され、前記配線層は、さらに前記チップの活性面におけるピンに直接接続される、又は第1導電性ビアポストを介して前記チップの活性面におけるピンに接続される、ことを特徴とする請求項1に記載の濡れ性側面付きパッケージ構造。
- 前記配線層は複数層あり、隣接する2層の前記配線層は第3導電性ビアポストを介して接続されている、ことを特徴とする請求項2に記載の濡れ性側面付きパッケージ構造。
- 前記第1誘電体層の第2面に放熱層が設けられ、前記放熱層は前記チップの放熱面に直接接続される、又は第1熱伝達性ビアポストを介して前記チップの放熱面に接続されている、ことを特徴とする請求項1に記載の濡れ性側面付きパッケージ構造。
- 前記配線層には底部パッドが設けられ、前記第1側壁パッド及び前記底部パッドのうちの少なくとも1つに半田ボールが植え付けられている、ことを特徴とする請求項1から4のいずれかに記載の濡れ性側面付きパッケージ構造。
- 前記チップの活性面に機能領域が設けられ、前記機能領域は前記第1誘電体層から露出している、ことを特徴とする請求項1に記載の濡れ性側面付きパッケージ構造。
- 前記チップの活性面に透明な第2表面保護層が設けられている、ことを特徴とする請求項6に記載の濡れ性側面付きパッケージ構造。
- 前記チップの活性面に非透明な第2表面保護層が設けられ、前記第2表面保護層に、前記機能領域に対応する窓掛け部位が設けられている、ことを特徴とする請求項6に記載の濡れ性側面付きパッケージ構造。
- 誘電体枠を提供するステップであって、前記誘電体枠に少なくとも1つのパッケージキャビティが設けられ、前記誘電体枠の、前記パッケージキャビティの外側に第1金属柱が設けられ、前記第1金属柱の2つの端面がそれぞれ前記誘電体枠の対向する両面に露出しているステップと、
パッケージ対象のチップを前記パッケージキャビティ内にパッケージして、前記チップの活性面におけるピンがその第1面に面している第1仕掛け品を得るステップと、
前記第1金属柱及び前記チップの活性面におけるピンに直接又は間接的に接続される配線層を前記第1仕掛け品の第1面に製造して、第2仕掛け品を得るステップと、
前記第2仕掛け品を切断して、第1側壁パッドを有するパッケージユニットを得るステップであって、少なくとも1本の切断経路は前記第1金属柱を通っているステップとを含む、ことを特徴とするパッケージ構造の製造方法。 - 配線層を前記第1仕掛け品の第1面に製造するステップは、
前記チップの活性面におけるピンが前記第1仕掛け品の第1面に面しており且つ第1面に露出しているときに、前記チップの活性面におけるピンに直接接続される前記配線層を前記第1仕掛け品の第1面に製造して、前記第2仕掛け品を得るステップを含む、ことを特徴とする請求項9に記載のパッケージ構造の製造方法。 - 配線層を前記第1仕掛け品の第1面に製造するステップは、
前記チップの活性面におけるピンが前記第1仕掛け品の第1面に面しており且つ前記第1仕掛け品に埋設されたときに、前記チップの活性面におけるピンに連通する第1導通孔を前記第1仕掛け品の第1面に開けるステップと、
電気めっきによって、前記第1導通孔内で、第1端が前記チップの活性面におけるピンに接続され、第2端が前記第1仕掛け品の第1面に露出している第1導電性ビアポストを加工するステップと、
前記第1導電性ビアポストに接続され、前記第1導電性ビアポストを介して前記チップの活性面におけるピンに接続される前記配線層を前記第1仕掛け品の第1面に製造して、前記第2仕掛け品を得るステップとを含む、ことを特徴とする請求項9に記載のパッケージ構造の製造方法。 - 前記配線層は複数層あり、隣接する2層の前記配線層は第3導電性ビアポストを介して接続され、最外層の前記配線層は第4導電性ビアポストを介して前記第1金属柱に接続される、ことを特徴とする請求項10又は11に記載のパッケージ構造の製造方法。
- 配線層を前記第1仕掛け品の第1面に製造するステップは、
前記チップの活性面におけるピンが前記第1仕掛け品の第1面に面しており且つ前記チップの放熱面が前記第1仕掛け品内に埋設されたときに、前記第1仕掛け品の第2面に、前記チップの放熱面に連通する第2導通孔を開けるステップと、
電気めっきによって、前記第2導通孔内で、第1端が前記チップの放熱面に接続され、第2端が前記第1仕掛け品の第2面に露出している第1熱伝達性ビアポストを加工するステップと、
前記配線層を前記第1仕掛け品の第1面に製造し、前記第1熱伝達性ビアポストに接続される放熱層を前記第1仕掛け品の第2面に製造して、前記第2仕掛け品を得るステップとを含む、ことを特徴とする請求項9に記載のパッケージ構造の製造方法。 - 配線層を前記第1仕掛け品の第1面に製造するステップは、
前記チップの活性面におけるピンが前記第1仕掛け品の第1面に面しており且つ前記チップの放熱面が前記第1仕掛け品の第2面に露出しているときに、前記配線層を前記第1仕掛け品の第1面に製造し、前記チップの放熱面に直接接続される放熱層を前記第1仕掛け品の第2面に製造して、前記第2仕掛け品を得るステップを含む、ことを特徴とする請求項9に記載のパッケージ構造の製造方法。 - 前記チップの活性面に機能領域が設けられ、パッケージ対象の前記チップを前記パッケージキャビティ内にパッケージするステップは、
前記パッケージキャビティの底部に仮負荷面を提供するステップと、
前記チップを前記パッケージキャビティ内に実装し、且つ前記チップの活性面を前記仮負荷面上に実装するステップと、
パッケージ材料を用いて前記チップをパッケージするステップと、
前記仮負荷面を除去して、前記チップの活性面における前記機能領域を露出させるステップとを含む、ことを特徴とする請求項9に記載のパッケージ構造の製造方法。 - 前記第2仕掛け品を切断した後、
前記チップの活性面に透明な第2表面保護層を加工するステップをさらに含む、ことを特徴とする請求項15に記載のパッケージ構造の製造方法。 - 前記第2仕掛け品を切断した後、
前記チップの活性面に非透明な第2表面保護層を加工するステップと、
前記第2表面保護層において前記機能領域に対応する位置に窓をかけるステップとをさらに含む、ことを特徴とする請求項15に記載のパッケージ構造の製造方法。 - 請求項9から17のいずれか一項に記載のパッケージ構造の製造方法によって得られる、ことを特徴とする濡れ性側面付きパッケージ構造。
- 請求項1から8のいずれか一項に記載の濡れ性側面付きパッケージ構造、又は請求項18に記載の濡れ性側面付きパッケージ構造を含む、ことを特徴とする垂直パッケージモジュール。
- プリント回路基板と、
第2側壁パッドが設けられ、前記第2側壁パッドを介して前記プリント回路基板に溶接され、第1面が前記プリント回路基板に垂直であるパッケージユニットと、
前記パッケージユニット内にパッケージされ、且つ前記第2側壁パッドに電気的に接続され、機能エリアが前記パッケージユニットの第1面に面している、前記機能エリアを有するパッケージデバイスとを含む、ことを特徴とする垂直パッケージモジュール。 - 前記プリント回路基板の表面又は側辺に窪みが設けられ、前記窪み内に第1パッドが設けられ、前記第2側壁パッドは前記第1パッドに溶接により接続されている、ことを特徴とする請求項20に記載の垂直パッケージモジュール。
- 前記プリント回路基板の上面又は下面に凸部が設けられる、ことを特徴とする請求項20又は21に記載の垂直パッケージモジュール。
- 前記凸部に第2パッドが設けられ、
前記パッケージユニットには底部パッドがさらに設けられ、前記底部パッドは前記第2パッドに溶接により接続されている、ことを特徴とする請求項22に記載の垂直パッケージモジュール。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002359343A (ja) * | 2001-05-31 | 2002-12-13 | Nec Corp | 半導体装置 |
JP2008244451A (ja) * | 2007-02-21 | 2008-10-09 | Advanced Chip Engineering Technology Inc | ダイ収容スルーホールおよびスルーホール接続構造を有する半導体素子パッケージおよびその方法 |
JP2009044160A (ja) * | 2007-08-10 | 2009-02-26 | Samsung Electronics Co Ltd | 埋め込まれた導電性ポストを備える半導体パッケージ及びその製造方法 |
JP2009302221A (ja) * | 2008-06-12 | 2009-12-24 | Nec Electronics Corp | 電子装置及びその製造方法 |
JP2021052148A (ja) * | 2019-09-26 | 2021-04-01 | 京セラ株式会社 | 回路基板、電子部品および電子モジュール |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200802634A (en) * | 2006-06-02 | 2008-01-01 | Siliconware Precision Industries Co Ltd | Semiconductor package and method for fabricating the same |
US10199311B2 (en) * | 2009-01-29 | 2019-02-05 | Semiconductor Components Industries, Llc | Leadless semiconductor packages, leadframes therefor, and methods of making |
KR101107770B1 (ko) * | 2009-05-26 | 2012-01-20 | 일진반도체 주식회사 | 발광 다이오드 패키지 및 백라이트 유닛 |
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CN103280424B (zh) * | 2012-12-12 | 2015-10-28 | 贵州振华风光半导体有限公司 | 一种高集成度功率厚膜混合集成电路的集成方法 |
KR102157942B1 (ko) * | 2014-09-26 | 2020-09-21 | 인텔 코포레이션 | 플렉시블 패키징 아키텍처 |
CN104793298B (zh) * | 2015-04-13 | 2017-03-22 | 华进半导体封装先导技术研发中心有限公司 | 一种带侧面焊盘的载板结构及其制作方法 |
US10930581B2 (en) * | 2016-05-19 | 2021-02-23 | Stmicroelectronics S.R.L. | Semiconductor package with wettable flank |
CN107768323B (zh) * | 2017-11-24 | 2023-12-05 | 安徽芯动联科微系统股份有限公司 | 抗高过载电子器件封装管壳 |
CN111863775B (zh) * | 2020-06-16 | 2022-07-26 | 珠海越亚半导体股份有限公司 | 散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板 |
CN111564374A (zh) * | 2020-07-15 | 2020-08-21 | 珠海越亚半导体股份有限公司 | 封装基板制作方法 |
CN111599797B (zh) * | 2020-07-27 | 2020-10-27 | 甬矽电子(宁波)股份有限公司 | 柔性基板堆叠封装结构和柔性基板堆叠封装方法 |
CN112164677A (zh) * | 2020-08-25 | 2021-01-01 | 珠海越亚半导体股份有限公司 | 一种线路预排布散热嵌埋封装结构及其制造方法 |
CN112702836B (zh) * | 2020-12-28 | 2022-03-15 | 华进半导体封装先导技术研发中心有限公司 | 一种带侧壁焊盘的载片结构及其制作方法 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002359343A (ja) * | 2001-05-31 | 2002-12-13 | Nec Corp | 半導体装置 |
JP2008244451A (ja) * | 2007-02-21 | 2008-10-09 | Advanced Chip Engineering Technology Inc | ダイ収容スルーホールおよびスルーホール接続構造を有する半導体素子パッケージおよびその方法 |
JP2009044160A (ja) * | 2007-08-10 | 2009-02-26 | Samsung Electronics Co Ltd | 埋め込まれた導電性ポストを備える半導体パッケージ及びその製造方法 |
JP2009302221A (ja) * | 2008-06-12 | 2009-12-24 | Nec Electronics Corp | 電子装置及びその製造方法 |
JP2021052148A (ja) * | 2019-09-26 | 2021-04-01 | 京セラ株式会社 | 回路基板、電子部品および電子モジュール |
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