TWI804889B - 半導體裝置結構及製造方法 - Google Patents

半導體裝置結構及製造方法 Download PDF

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TWI804889B
TWI804889B TW110121845A TW110121845A TWI804889B TW I804889 B TWI804889 B TW I804889B TW 110121845 A TW110121845 A TW 110121845A TW 110121845 A TW110121845 A TW 110121845A TW I804889 B TWI804889 B TW I804889B
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layer
source
feature
dielectric layer
semiconductor device
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TW110121845A
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TW202201639A (zh
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朱家宏
王菘豊
梁順鑫
張旭凱
時定康
洪宗佑
蔡邦彥
林耕竹
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台灣積體電路製造股份有限公司
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Abstract

根據本揭露的半導體裝置結構包括源極部件以及汲極部件，於源極部件以及汲極部件之間延伸的至少一通道結構，環繞至少一通道結構的每一個的閘極結構，於閘極結構上的半導體層，於半導體層上的介電層，延伸穿過半導體層以及介電層以接觸源極部件的摻雜半導體部件，於摻雜半導體部件上的金屬接觸插塞，以及設置於金屬接觸插塞上的埋置電源軌。

Description

半導體裝置結構及製造方法
本發明實施例是關於一種半導體裝置結構及製造方法，特別是關於一種具有接觸結構的半導體裝置結構及製造方法。
半導體積體電路(integrated circuit, IC)工業已經歷指數型成長。在積體電路的材料和設計上的技術進展已經產生了數個積體電路世代，每一個世代比先前的世代具有更小且更複雜的電路。在積體電路發展的過程中，隨著幾何尺寸（例如：使用製造過程可以產生的最小元件或線）縮減的同時，功能密度（例如：每一個晶片面積內互相連接的裝置數量）通常也在增加。尺寸縮減製程通常藉由增加生產效率和降低伴隨的成本而提供好處。這樣的尺寸縮減也增加了處理與製造積體電路的複雜度。
舉例來說，積體電路(IC)技術製程來到更小的技術節點，導入多閘極裝置以藉由增加閘極－通道耦合、減少關閉狀態電流(off-state current)以及減少短通道效應(short-channel effects, SCEs)來改善閘極控制。多閘極裝置通常是指具有閘極結構或者其一部分的裝置，設置於通道區的一側以上的上方。鰭式場效電晶體(FinFETs)以及多橋接通道(multi-bridge-channel, MBC)電晶體為多閘極裝置的例子，其已成為用於高效能與低漏電流的應用的受歡迎且有發展性的候選裝置。鰭式場效電晶體具有較高的通道，其在一側以上的上方被閘極包覆（例如，閘極包覆從基板延伸的半導體材料的「鰭片」的頂部和側壁）。MBC電晶體具有可部分或完全圍繞著通道區延伸的閘極結構，以提供至通道區的兩側或更多側的通路(access)。因為閘極結構環繞通道區，因此MBC電晶體亦可稱為環繞閘極電晶體(surrounding gate transistor, SGT)或全繞式閘極 (gate-all-around, GAA)電晶體。MBC電晶體的通道區可以奈米線(nanowire)、奈米片(nanosheet)、其他奈米結構及／或其他適合的結構來形成。通道區的形狀亦為MBC電晶體提供了替代名稱，例如奈米片電晶體或奈米線電晶體。
多閘極電晶體的實施例減少了裝置尺寸並增加了裝置封裝密度，這為形成電源和訊號佈線(routing)的方面帶來挑戰。埋置電源軌的發展減輕了在密集封裝的裝置形成電源和訊號佈線的壓力。背側接觸件和磊晶源極／汲極部件之間的界面處的電阻是降低接觸電阻的瓶頸。儘管現有的埋置電源軌結構通常足以滿足其預期目的，但尚未完全滿足所有方面。
本揭露提供一種半導體裝置結構，此裝置結構包括源極部件以及汲極部件，於源極部件以及汲極部件之間延伸的至少一通道結構，環繞至少一通道結構的每一個的閘極結構，於閘極結構上的半導體層，於半導體層上的介電層，延伸穿過半導體層以及介電層以接觸源極部件的摻雜半導體部件，於摻雜半導體部件上的金屬接觸插塞，以及設置於金屬接觸插塞上的埋置電源軌。
本揭露提供一種半導體裝置，此裝置包括源極部件以及汲極部件，沿著一方向設置於源極部件以及汲極部件之間的複數個通道元件，環繞複數個通道結構的每一個的閘極結構，設置於閘極結構上的矽層，設置於矽層上的第一介電層，設置於第一介電層上的第二介電層，設置於第二介電層中且於源極部件上的金屬接觸部件，以及設置於源極部件與金屬接觸部件之間的磊晶延伸部件。第二介電層的一部分延伸穿過矽層與第一介電層以與汲極部件接觸。磊晶延伸部件延伸穿過矽層以及第一介電層。
本揭露提供一種半導體裝置結構形成方法，此方法包括接收一工件，此工件包括設置於基板上的源極部件以及汲極部件，於源極部件以及汲極部件之間延伸的複數個通道元件，此複數個通道元件設置於底部矽層與底部介電層上，以及環繞複數個通道元件的每一個的閘極結構，接合工件的前側至載體基板並且翻轉工件，選擇性地移除基板以從工件的背側露出源極部件以及汲極部件，其中背側與前側為相反側，沉積介電層於工件的背側上，在沉積介電層之後，形成穿過介電層的背側源極接觸開口以露出源極部件，以磊晶沉積延伸部件於背側源極接觸開口中，以及沉積金屬填充層於延伸部件上。
以下內容提供了許多不同的實施例或範例，用於實施所提供之標的之不同部件。組件和配置的具體範例描述如下，以簡化本揭露實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中若提及第一部件形成於第二部件之上或上方，可能包含形成第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。此外，本揭露實施例在不同範例中可重複使用參考數字及/或字母。此重複是為了簡化和清楚之目的，並非代表所討論的不同實施例及/或組態之間有特定的關係。
此外，其中可能用到與空間相對用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」及類似的用詞，這些空間相對用語係為了便於描述圖示中一個（些）元件或部件與另一個（些）元件或部件之間的關係，這些空間相對用語包含使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），則其中所使用的空間相對形容詞也將依轉向後的方位來解釋。此外，當使用「約」、「大約」等來描述數量或數量範圍時，除非另有說明，否則此用詞旨在包括在所述數字的+/-10%內的數字。舉例來說，用詞「約5nm」包括4.5nm至5.5nm的尺寸範圍。
本揭露一般是關於背側接觸結構以及其形成方法，且更特定地關於磊晶延伸部件，其增加背側源極接觸件與源極部件之間的界面面積。
通常，基板上的電晶體的源極／汲極接觸件和閘極接觸件將電晶體的源極／汲極部件連接至基板的前側上方的互連結構。隨著IC裝置的尺寸縮小，源極接觸件和閘極接觸件之間的緊密接近會降低形成這些接觸件的製程裕度(process window)，並且可能會增加它們之間的寄生電容(parasitic capacitance)。埋置電源軌(buried power rail, BPR)結構是一種現代化的解決方案，用於提高先進技術節點的電力輸送網路(power delivery network, PDN)的性能，並減輕了接觸件的擁擠。為了降低埋置電源軌結構中的電阻，其挑戰在於減少金屬－半導體界面處的電阻。 儘管藉由通過導入新材料（例如釕、鈷、鎢或鈦）和新製程（例如無阻障接觸(barrier-less contact)或無晶種製程(seed-free processes)）而取得了進步，但由金屬－半導體界面所引起的較高的接觸件至源極／汲極的電阻(contact-to-source/drain resistance, Rcsd)仍然是一個問題。當接觸導孔的底部尺寸小於10奈米時，較小界面面積的電阻成為決定接觸電阻的瓶頸。
本揭露提供具有減少的電阻的埋置電源軌結構的實施例。根據本實施例，在源極部件從工件的背側露出之後，從露出的源極部件上磊晶成長摻雜半導體部件以作為源極部件的延伸。摻雜半導體部件延伸穿過底部介電層，且包括表面積大於源極部件的表面積的端點部分。接著在端點部分上形成背側接觸部件，以將端點部分連接至埋置電源軌。增加的端點部分的表面積幫助降低源極部件與埋置電源軌之間的電阻。
以下將參照圖式更詳細地描述本揭露的各個面向。在這方面，根據本揭露的實施例，第1圖繪示從工件200（至少顯示於第2-10、11A至15A以及11B至15B圖中）製造半導體裝置的方法100的流程圖。方法100僅為示例，且並非旨在將本揭露限制為方法100中明確繪示的內容。可在方法100之前、期間以及之後提供額外的步驟，並且本文所敘述的一些步驟可在此方法的額外實施例中被取代、刪去或者移動。為了簡單表示，在本文並未敘述所有的步驟的細節。下面結合第2-10圖、第11A-15A圖以及第11B-15B圖來描述方法100，其為根據方法100的實施例的在不同製造階段的工件的局部剖面圖。為了更佳地繪示本揭露的各個方面，第2-10圖、第11A-15A圖以及第11B-15B圖可包括沿著不同方向的剖面圖。由於完成製造過程後，工件200將被製造成半導體裝置200，因此根據上下文，工件200可稱為半導體裝置200。
請參考第1-5圖，方法100包括方框102，其中形成工件200。第5圖中顯示的工件200的製造過程可代表性地繪示於第1-5圖中。可從第2圖中顯示的接收一基板20來開始工件200的製造。基板20可為絕緣上覆矽(silicon-on-insulator, SOI)基板，其包括底矽層(base silicon layer)201、絕緣層202以及頂矽層203。在一些實施方法中，底矽層201與頂矽層203以矽形成，以及絕緣層202包括氧化矽。請參考第3圖，底部犧牲層204、底部半導體層205以及堆疊物207沉積於基板20上。底部犧牲層204可包括矽鍺(SiGe)，以及底部半導體層205可包括矽(Si)。堆疊物207包括以複數個犧牲層206交錯的複數個通道層208。雖然圖式中繪示三個犧牲層206與三個通道層208，但並未限制本揭露。根據各種設計需求，犧牲層206與通道層208的數量可介於2與10之間。在一些情況下，複數個通道層208可包括矽(Si)，以及複數個犧牲層206可包括矽鍺(SiGe)。雖然底部犧牲層204以及複數個犧牲層206皆以矽鍺形成，但可能具有不同的鍺含量。可使用分子束磊晶(molecular beam epitaxy, MBE)、氣相磊晶(vapor-phase epitaxy, VPE)、超高真空CVD(ultra-high vacuum CVD, UHV-CVD)及／或其他適合的磊晶成長製程來磊晶沉積底部犧牲層204、底部半導體層205以及堆疊物207。
請參考第4圖，堆疊物207、底部半導體層205、底部犧牲層204以及頂矽層203被圖案化成鰭狀構造210，其沿著Y方向縱向延伸。在一些實施方式中，可使用對半導體材料具有選擇性的蝕刻化學品來圖案化鰭狀構造210。在這些實施方法中，以氧化矽形成的絕緣層202作為蝕刻停止層。在形成鰭狀構造210之後，在鰭狀構造210之間形成隔離部件212（於第11B-15B圖中顯示），同時一部分的鰭狀構造210超過隔離部件。隔離部件212也可稱為淺溝槽隔離(STI)部件。隔離部件212可包括氧化矽、氮化矽、氮氧化矽、氟摻雜矽酸鹽玻璃(fluorine-doped silicate glass, FSG)、低介電常數介電質、上述的組合及／或其他適合的材料。
請參考第5圖，在形成絕緣部件之後，在鰭狀構造210的通道區10C上形成虛置閘極堆疊（未繪示）以及閘極間隔物222。以虛置閘極堆疊以及閘極間隔物作為蝕刻遮罩，鰭狀構造210的源極區10S以及汲極區10D被凹蝕以形成露出複數個犧牲層206及通道層208的側壁的源極凹槽與汲極凹槽。犧牲層206接著被部分地且選擇性地凹蝕以形成內部間隔物凹槽。內部間隔物部件224沉積至內部間隔物凹槽中。在一些實施例中，內部間隔物部件224可包括氮氧化矽、碳氮化矽、碳氧化矽、碳氮氧化矽、氮化矽、富碳碳氮化矽或者適合的介電材料。在形成內部間隔物部件224之後，底部犧牲層204由底部介電層2040替代。在一些實施例中，底部犧牲層204可先被氧化以形成矽鍺氧化物層，且矽鍺氧化物層被選擇性地移除以留下在頂矽層203與底部半導體層205之間的底部開口。之後，在底部開口中沉積底部介電層2040。在一些實施例中，底部介電層2040可包括氧化矽、氮化矽、氧化鋁、氧化鉿、氧化鋯或其他適合的介電材料。在一些情況下，底部介電層2040可沿著Z方向具有介於約10奈米及約30奈米之間的厚度。在形成內部間隔物部件的期間，底部半導體層205的厚度可能減少。在一些極端的例子中，底部半導體層205具有相對薄的初始厚度，且在形成內部間隔物部件的期間，其整體厚度可能會被蝕刻去除。在一些情況下，第5圖中的工件200中的底部半導體層205可具有介於約0奈米以及約40奈米之間的厚度。
在形成底部介電層1040之後，在源極區10S上沉積源極部件225S，並且在汲極區10D上沉積汲極部件225D。可使用分子束磊晶(MBE)、氣相磊晶(VPE)、超高真空CVD(UHV-CVD)及／或其他適合的磊晶成長製程來磊晶沉積源極部件225S與汲極部件225D。在繪示的實施例中，每個源極部件225S與汲極部件225D可包括外層(outer layer)226與內層(inner layer)228。依序形成外層226與內層228。藉由從通道層208的側壁以及頂矽層203露出的表面上磊晶成長來沉積外層226。接著從外層226的表面磊晶成長內層228。源極部件225S與汲極部件225D可具有不同的組成，取決於將要在工件200上的MBC電晶體的種類。當需要n型MBC電晶體時，源極部件225S與汲極部件225D可包括矽，且可以n型摻雜物來摻雜，例如磷(P)、砷(As)或銻(Sb)。當需要p型MBC電晶體時，源極部件225S與汲極部件225D可包括矽鍺，且可以p型摻雜物來摻雜，例如硼(B)或鎵(Ga)。外層226的組成與內層228的組成可為不同的。在一些實施例中，外層226與內層228可用不同的摻雜物種類來摻雜。舉例來說，外層226可以砷摻雜，以及內層228可以磷摻雜。在一些其他的實施例中，外層226與內層228可包括不同的摻雜物濃度。舉例來說，為了減少接觸電阻，內層228的摻雜物濃度可大於外層226的摻雜物濃度。如第5圖所示，內層228藉由外層226來與通道層208（在第5圖中作為通道元件(channel members)2080釋出）及頂矽層203分隔。
再請參考第5圖。形成源極部件225S與汲極部件225D之後，在源極部件225S與汲極部件225D上形成接觸蝕刻停止層(CESL)230以及第一層間介電質(ILD)層232。在一些例子中，接觸蝕刻停止層230可包括氮化矽、氮氧化矽及／或其他本發明所屬技術領域中所習知的材料。可藉由ALD、電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition, PECVD)製程及／或其他適合的沉積或者氧化製程來形成接觸蝕刻停止層230。接著在接觸蝕刻停止層230上沉積第一層間介電質層232。在一些實施例中，第一層間介電質層232的材料包括例如四乙氧基矽烷(tetraethylorthosilicate, TEOS)氧化物、未摻雜的矽酸鹽玻璃或者例如硼磷矽酸鹽玻璃(borophosphosilicate glass, BPSG)、 熔融矽石玻璃(f used silica glass, FSG)、磷矽酸鹽玻璃(phosphosilicate glass, PSG)、硼摻雜矽酸鹽玻璃(boron doped silicon glass, BSG) 的摻雜的氧化矽、碳氧化矽、碳氮氧化矽及／或其他適合的介電材料。可藉由PECVD製程或其他適合的沉積技術來沉積第一層間介電質層232。在一些實施例中，在形成第一層間介電質層232之後，可將工件200退火來改善第一層間介電質層232的結構完整性(integrity)。在沉積接觸蝕刻停止層230與第一層間介電質層232之後，可藉由平坦化製程來平坦化工件200，以露出虛置閘極堆疊。虛置閘極堆疊與犧牲層206接著被選擇性地移除，以在通道區10C中釋出通道層208，作為通道元件2080。
閘極結構220接著沉積於通道區10C上，以環繞各個通道元件2080。各個閘極結構220可包括界面層214、界面層214上的閘極介電層216以及閘極介電層216上的閘極電極層218。在一些實施例中，界面層214可包括介電材料，例如氧化矽、矽酸鉿或氮氧化矽。閘極介電層216可包括高介電常數介電材料，例如氧化鉿。在本文中，高介電常數介電材料意指介電常數大於氧化矽的介電常數(~3.9)的介電材料。替代地，閘極介電層216可包括其他高介電常數介電質，例如氧化鉿(HfO)、氧化鈦(TiO2 )、氧化鋯鉿(HfZrO)、氧化鉭(Ta2 O5 )、氧化矽鉿(HfSiO4 )、氧化鋯(ZrO2 )、氧化矽鋯(ZrSiO2 )、氧化鑭(La2 O3 )、氧化鋁(Al2 O3 )、氧化鋯(ZrO)、氧化釔(Y2 O3 )、SrTiO3 (STO)、BaTiO3 (BTO)、BaZrO、氧化鉿鑭 (HfLaO)、氧化矽鑭(LaSiO)、氧化矽鋁(AlSiO)、氧化鉭鉿 (HfTaO)、氧化鈦鉿(HfTiO)、(Ba,Sr)TiO3(BST)、氮化矽(SiN)、氧氮化矽(SiON)、上述的組合或其他適合的材料。閘極電極層218可包括單一層，或者替代地包括多層結構，例如具有經由選擇以提升裝置效能的功函數的金屬層的各種組合（功函數金屬層）、襯層、潤濕層(wetting layer)、黏合層、金屬合金或者金屬矽化物。舉例來說，閘極電極層218可包括Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他適合的金屬材料或上述的組合。在各種實施例中，沉積閘極電極層218之後，可執行平坦化製程（例如化學機械研磨(CMP)製程）以從工件200移除多餘的金屬，從而提供閘極結構220實質上平坦的頂面。在形成閘極結構時，MBC結構實質上形成於工件200上。
形成MBC結構之後，執行進一步的製程以形成與MBC結構互連的結構。再請參考第5圖。在一些實施例中，閘極蓋層234與第一介電層236依序沉積於閘極結構220上，且形成閘極接觸導孔238以耦合至閘極結構。如第5圖中所示，閘極接觸導孔238垂直延伸穿過閘極蓋層234與第一介電層236。第二介電層240沉積於閘極接觸導孔238上，且金屬線242沉積於第二介電層240中以電性耦合至閘極接觸導孔238。在一些實施例中，第一介電層236與第二介電層240可與第一層間介電質層232具有相同的組成。各個閘極接觸導孔238與金屬線242可包括金屬填充層，以及將金屬填充層與周圍的介電層隔開的阻障層。在一些實施方法中，阻障層可包括金屬氮化物，例如氮化鈦或氮化鉭，以及金屬填充層可包括金屬，例如銅、釕、鎢、鎳或鈷。雖然在第5圖中並未明確繪示，可在金屬線242上形成額外的互連層。在一些實施例中，在將工件200接合至載體基板（例如載體基板248，將於下文描述）之前形成整個前側互連結構（包括第二介電層240與金屬線242）。此外，雖然並未明確繪示，可形成一個或多個前側源極／汲極接觸導孔以耦合至源極部件225S或汲極部件225D。此種前側源極接觸導孔可延伸穿過接觸蝕刻停止層230、第一層間介電質層232、閘極蓋層234以及第一介電層236。如第5圖中所示，為了準備工件200以接合至載體基板，在金屬線242與第二介電層240上沉積第一氧化物層244。第一氧化物層244可包括氧化矽。
請參考第1、6及7圖，方法100包括方框104，其中載體基板248接合至工件200的前側。在方框104，藉由熔融接合(fusion bonding)、黏合層或上述的組合來將載體基板248接合至工件200。在一些情況下，載體基板248可以半導體材料（例如矽）、藍寶石、玻璃、聚合材料或其他適合的材料來形成。在使用熔融接合的實施例中，載體基板248包括第二氧化物層246。在第一氧化物層244和第二氧化物層246都經過處理之後，使它們彼此齊平接觸(flush contact)以在室溫或高溫下直接結合。一旦載體基板248接合至工件200的前側，將工件200翻轉，如第7圖所示。如第7圖中所繪示，將工件200翻轉之後，基板20朝上，使得底矽層201設置在絕緣層202上。
請參考第1圖及第8圖，方法100包括方框106，其中移除基板的一部分。如第8圖所示，在方框處，以研磨製程或平坦化製程（例如CMP製程）移除底矽層201與絕緣層202，直到隔離部件212（如第11B-15B圖中所示）與頂矽層203變平坦。
請參考第1圖及第9圖，方法100包括方框108，其中源極部件225S與汲極部件225D從工件200的背側被選擇性地凹蝕。在一些實施例中，頂矽層203、源極部件225S及汲極部件225D被選擇性地凹蝕，而底部介電層2040並未實質上地被凹蝕。在一些實施方法中，方框108的凹蝕為非等向性的，使得底部半導體層205並未實質上地被凹蝕。如第9圖所示，方框108的凹蝕可移除與頂矽層203接觸的外層226的一部分。亦即，方框108的凹蝕可露出源極部件225S或汲極部件225D的內層228。
請簡要地參考第13A圖與第14A圖。源極部件225S與汲極部件225D的內層228可具有如第13圖中所示的凸型表面(convex surface)268或者如第14圖中所示的在X-Y平面上的實質上的平坦表面270，取決於內層228的晶格結構以及方框108的選擇性蝕刻的化學藥劑。凸型表面268可包括介於約2奈米及約10奈米之間的凹槽。
再請參考第1及第9圖，方法100包括方框110，其中於基板20的背側上沉積蝕刻停止層(ESL)250與第二層間介電質(ILD)層252。在一些實施例中，蝕刻停止層250可與接觸蝕刻停止層230有相同的組成，並且第二層間介電質層252可與第一層間介電質層232有相同的組成。如第9圖所示，可使用ALD、PECVD或其他適合的沉積方法來保形地(conformally)沉積蝕刻停止層250，並且設置於底部半導體層205與底部介電層2040的側壁上，以及設置於源極部件225S與汲極部件225D上。可藉由CVD、流動式CVD或者旋轉塗佈來在工件200的背側上沉積第二層間介電質層252。藉由蝕刻停止層250來將第二層間介電質層252與底部半導體層205的側壁、底部介電層2040的側壁、源極部件225S及汲極部件225D隔開。如第9圖所示，至少一部分的蝕刻停止層250與第二層間介電質層252延伸穿過源極區10S與汲極區10D中的底部半導體層205及底部介電層2040。
請參考第1、9及10圖，方法100包括方框112，其中選擇性地形成穿過蝕刻停止層250與第二層間介電質層252的背側源極接觸開口256。在第9圖中顯示的一些實施例中，光阻遮罩254可形成於工件200的背側上。光阻遮罩254直接設置於汲極部件225D上，且包括遮罩開口255。使用光阻遮罩254作為蝕刻遮罩，將蝕刻停止層250與第二層間介電質層252非等向性地蝕刻以露出在背側源極接觸開口256中的源極部件225S。如第10圖所示，背側源極接觸開口256沿著Z方向垂直延伸穿過第二層間介電質層252、蝕刻停止層250、底部介電層2040以及底部半導體層205，以露出源極部件225S的內層228。
為了更詳細說明本揭露的實施例，特別聚焦於在第10圖中以虛線區域顯示的背側接觸區300，並且在第11A-15A圖和第11B-15B圖中提供了背側接觸區300的放大剖面圖。應注意的是，以大寫字母「A」結尾的圖式包括跨越汲極部件225D及源極部件225S的背側接觸區300的沿著Y方向的觀看方向的局部剖面圖，以及以大寫字母「B」結尾的圖式包括只跨越源極部件225S的沿著X方向的觀看方向的局部剖面圖。第11B-15B圖顯示在第2-10圖中並未明確顯示的部件。舉例來說，第11B-15B圖繪示形成於鰭狀結構210之間的隔離部件212以及介電鰭片215。介電鰭片215可包括氧化矽、氮化矽、氮氧化矽、碳氮氧化矽、碳氮化矽、氧化鋁、氧化鋯、氧化鉿或其他適合的介電材料。介電鰭片215的功能為隔開相鄰的源極部件225S或汲極部件225D，並避免它們彼此合併。
請參考第1、11A及11B圖，方法100包括方框114，其中襯層258形成於背側源極接觸開口256中。在一些實施例中，襯層258可包括氮化矽，且可沉積於工件200的背側上，並且於源極部件225S的內層228、底部半導體層205的側壁、底部介電層2040的側壁、底部介電層2040露出的頂面、第二層間介電質層252的側壁以及隔離部件212的側壁上。沉積襯層258之後，執行非等向性回蝕刻製程以從朝向頂部的表面上移除襯層258，例如從底部介電層2040的頂面、第二層間介電質層252的頂面、隔離部件212的頂面以及源極部件225S的內層228的頂面。在一些實施例中，源極部件225S的外層226並未在背側源極接觸開口256中露出。
請參考第1、12A及12B圖，方法100包括方框116，其中在背側源極接觸開口256中沉積磊晶延伸部件260。在一些實施例中，使用分子束磊晶(MBE)、氣相磊晶(VPE)、超高真空CVD(UHV-CVD)及／或其他適合的磊晶成長製程將磊晶延伸部件260沉積於源極部件225S的露出的內層228上。磊晶延伸部件260可包括摻雜的半導體材料。在需要n型MBC電晶體的實施例中，磊晶延伸部件260可包括矽，其以n型摻雜物摻雜，例如磷(P)、砷(As)或銻(Sb)。在需要p型MBC電晶體的實施例中，磊晶延伸部件260可包括矽鍺，其以p型摻雜物來摻雜，例如硼(B)或鎵(Ga)。在一些實施方法中，在磊晶沉積製程期間原位摻雜磊晶延伸部件260。在磊晶沉積製程期間，可從源極部件225S的內層228上選擇性地生長磊晶延伸部件260，而介電襯層258阻止磊晶延伸部件260的直接生長。如此一來，磊晶延伸部件260的形成是以由下而上(bottom-up)的方式形成。就此觀點而言，磊晶延伸部件260的形成亦為自對準的，因為其並沒有從第二層間介電質層252，隔離部件212或底部介電層2040上磊晶生長。
在一些實施例中，磊晶延伸部件260與源極部件225S的內層228可以相同的半導體材料形成，例如矽或矽鍺。在這些實施例中，磊晶延伸部件260與源極部件225S的內層228亦可包括同類型的摻雜物與相同的摻雜物種類。舉例來說，磊晶延伸部件260與源極部件225S的內層228皆可以磷摻雜矽(Si:P)、砷摻雜矽(Si:As)、銻摻雜矽(Si:Sb)、硼摻雜矽鍺(SiGe:B)或鎵摻雜矽鍺(SiGe:Ga)來形成。在一些情況下，為了減少接觸電阻，磊晶延伸部件260中的摻雜濃度大於源極部件225S的內層228中的摻雜濃度。舉例來說，當磊晶延伸部件260與源極部件225S的內層228皆以磷摻雜矽(Si:P)形成時，磊晶延伸部件260中的磷濃度可大於源極部件225S的內層228中的磷濃度。為了避免閘極結構220與前側互連結構發生熱變質(thermal deterioration)，形成磊晶延伸部件260的製程溫度小於400°C，例如介於約260°C與約400°C之間。當製程溫度大於400°C，前側互連結構中的銅可能發生電遷移(electro-migration)，從而形成空隙(voids)、凹坑(pits)或擠壓(extrusion)。
磊晶延伸部件260的功能為源極部件225S的內層228的延伸。一旦磊晶延伸部件260延伸穿過底部半導體層205與底部介電層2040，則在不同的實施例中，得以使磊晶延伸部件260的尺寸沿著Z方向和X方向在第一端點部分2602（如第12A圖中所示）或第二端點部分2604（如圖15A中所示）中擴展。舉例來說，沿著X方向以及在底部介電層2040的水平面上，背側源極接觸開口256和磊晶延伸部件260的寬度可以介於約8奈米和20奈米之間。第一端點部分2602（在第12A圖中顯示的實施例中）或第二端點部分2604（在第15A圖所示的替代實施例中）可具有介於約8奈米與約30奈米之間的較大寬度。第一端點部分2602可為等向性磊晶成長的結果，且具有圓化的形狀(rounded shape)或者蘑菇形狀。第二端點部分2604可為刻面成長(faceted growth)的結果，且具有斜方形(rhombus)形狀或箭頭形狀。在一些情況下，第二端點部分2604可包括介於約30°與約70°之間的刻面角度θ。相較於內層228，第一端點部分2602與第二端點部分2604提供更多表面積以與以金屬形成的背側源極接觸件264接合。
請參考第1、13A、13B、14A、14B、15A及15B圖，方法100包括方框118，其中矽化物層262形成於磊晶延伸部件260上。為了減少磊晶延伸部件260與背側源極接觸件264之間的接觸電阻，矽化物層262可形成於磊晶延伸部件260的第一端點部分2602（在第13A或14A圖中顯示的實施例中）或第二端點部分2604（在第15A圖所示的替代實施例中）上，視情況而定。為了形成矽化物層262，在磊晶延伸部件260上沉積金屬層，且執行退火製程以在金屬層和磊晶延伸部件260之間引起矽化反應。適合的金屬層可包括鈦(Ti)、鉭(Ta)、鎳(Ni)、鈷(Co)或鎢(W)。矽化物層262可包括矽化鈦(TiSi)、氮化鈦矽(TiSiN)、矽化鉭(TaSi)、矽化鎢(WSi)、矽化鈷(CoSi)或矽化鎳(NiSi)。在磊晶延伸部件260包括鍺的實施例中，矽化物層262亦可包括金屬鍺化物或鍺錫(GeSn)。矽化物層262通常追蹤(track)磊晶延伸部件260的第一端點部分2602（第13A圖或14A圖中所示）或第二端點部分2604（第15A圖所示）的形狀，視情況而定。儘管未明確顯示，但是可以在方框118移除未形成矽化物層262的多餘金屬層。
請參考第1、13A、13B、14A、14B、15A及15B圖，方法100包括方框120，其中背側源極接觸件264形成於矽化物層262上。在形成矽化物層262之後，可在背側源極接觸開口256中沉積金屬填充層以形成背側源極接觸件264。金屬填充層可包括鋁(Al)、釕(Rh)、釕(Ru)、銅(Cu)、銥(Ir)或鎢(W)。可接著以平坦化製程（例如CMP製程）來移除多餘的材料，並提供平坦的頂面。背側源極接觸件264包覆(wrap)在磊晶延伸部件260的突出的第一端點部分2602（在第13A圖或14A圖所示的實施例中）或第二端點部分2604（在第15A圖所示的替代實施例中）上。結果，磊晶延伸部件260的第一端點部分2602（在第13A圖或14A圖所示的實施例中）或第二端點部分2604（在第15A圖所示的替代實施例中）延伸進入背側源極接觸件264。從底部介電層2040的頂面至埋置電源軌266（將在下文描述）的底面測量，背側源極接觸件264可具有介於約10奈米及約60奈米之間的厚度。沿著X方向，背側源極接觸件264可具有介於約20奈米及約40奈米的寬度。背側源極接觸件264亦可稱為背側金屬插塞264。
請參考第1、13A、13B、14A、14B、15A及15B圖，方法100包括方框122，其中在背側源極接觸件264上形成埋置電源軌266。雖然並未明確顯示，埋置電源軌266可以被定義在絕緣層中。在示例性的製程中，可在工件200的背側上設置具有與第一層間介電質層232相似的組成的絕緣層，包括在第二層間介電質層252上以及背側源極接觸件264上。接著，可在絕緣層中圖案化電源軌溝槽。接著在電源軌溝槽中沉積阻障層與金屬填充材料以形成埋置電源軌266。在一些實施例中，埋置電源軌266中的阻障層可包括氮化鈦、氮化鉭、鉭化鈷、鉭化鎳或氮化鎢，以及埋置電源軌266中的金屬填充材料可包括鈦(Ti)、釕(Ru)、銅(Cu)、鎳(Ni)、鈷(Co)、鎢(W)、鉭(Ta)或鉬(Mo)。可使用PVD、CVD、ALD或無電解電鍍(electroless plating)來沉積阻障層與金屬填充層。可執行平坦化製程（例如CMP製程）來移除多餘的材料。在一些情況下，埋置電源軌266可沿著Z方向具有介於約10奈米及約60奈米之間的厚度。
現在請參考第16圖，其繪示本揭露的替代實施例。儘管本揭露的磊晶延伸部件260可以增加界面面積並減少與源極部件225S的接觸電阻，但是如果期望進一步地降低接觸電阻，則亦可形成前側源極接觸件280。如第16圖所示，半導體裝置200的源極部件225S耦合至前側源極接觸件280和磊晶延伸部件260。雖然並未明確顯示，但前側源極接觸件280藉由前側矽化物層282耦合至前側互連結構中的前側電源軌。磊晶延伸部件260藉由矽化物層262以及背側源極接觸件264電耦合至埋置電源軌266。如此一來，第16圖中的半導體裝置200的源極部件225S耦合至兩個電源軌－前側電源軌和埋置電源軌266。
本揭露的實施例提供一些優點。舉例來說，本揭露提供背側接觸結構的實施例，其中磊晶延伸部件設置於源極部件與背側源極接觸件之間。磊晶延伸部件以摻雜半導體材料形成，且提供增加的表面積以與背側源極接觸件接合。增加的表面積可減少在金屬半導體界面的電阻，並減輕接觸電阻的瓶頸。
在一示例性方面，本揭露針對一種半導體裝置結構。此半導體裝置結構包括源極部件以及汲極部件，於源極部件以及汲極部件之間延伸的至少一通道結構，環繞至少一通道結構的每一個的閘極結構，於閘極結構上的半導體層，於半導體層上的介電層，延伸穿過半導體層以及介電層以接觸源極部件的摻雜半導體部件，於摻雜半導體部件上的金屬接觸插塞，以及設置於金屬接觸插塞上的埋置電源軌。
在一些實施例中，半導體層包括矽。在一些實施方式中，源極部件、汲極部件以及摻雜半導體部件包括矽、矽鍺或鍺。在一些情況下，源極部件、汲極部件以及摻雜半導體部件更包括磷、砷、銻、硼或鎵。在一些實施例中，半導體裝置結構可更包括設置於摻雜半導體部件與金屬接觸插塞之間的界面上的矽化物層。在一些實施例中，摻雜半導體部件部分地延伸至金屬接觸插塞之中。在一些實施例中，源極部件包括與至少一通道結構接觸的外層，以及與至少一通道結構分隔的內層。在一些實施方式中，摻雜半導體部件與內層接觸，且與外層分隔。
在另一個示例性方面，本揭露針對一種半導體裝置。此半導體裝置包括源極部件以及汲極部件，沿著一方向設置於源極部件以及汲極部件之間的複數個通道元件，環繞複數個通道結構的每一個的閘極結構，設置於閘極結構上的矽層，設置於矽層上的第一介電層，設置於第一介電層上的第二介電層，設置於第二介電層中且於源極部件上的金屬接觸部件，以及設置於源極部件與金屬接觸部件之間的磊晶延伸部件。第二介電層的一部分延伸穿過矽層與第一介電層以與汲極部件接觸。磊晶延伸部件延伸穿過矽層以及第一介電層。
在一些實施例中，源極部件、汲極部件以及磊晶延伸部件包括矽、矽鍺或鍺。在一些實施方式中，源極部件、汲極部件以及磊晶延伸部件更包括磷、砷、銻、硼或鎵。在一些情況下，半導體裝置更包括設置於磊晶延伸部件與金屬接觸部件之間的界面上的矽化物層。在一些實施例中，磊晶延伸部件包括延伸至金屬接觸部件中的端點部分。在一些情況下，端點部分包括斜方形。在一些實施例中，端點部分包括圓化的形狀。
在另一個示例性方面，本揭露針對一種方法。此方法包括接收一工件，此工件包括設置於基板上的源極部件以及汲極部件，於源極部件以及汲極部件之間延伸的複數個通道元件，此複數個通道元件設置於底部矽層與底部介電層上，以及環繞複數個通道元件的每一個的閘極結構，接合工件的前側至載體基板並且翻轉工件，選擇性地移除基板以從工件的背側露出源極部件以及汲極部件，其中背側與前側為相反側，沉積介電層於工件的背側上，在沉積介電層之後，形成穿過介電層的背側源極接觸開口以露出源極部件，以磊晶沉積延伸部件於背側源極接觸開口中，以及沉積金屬填充層於延伸部件上。
在一些實施例中，此方法可更包括在沉積介電層之前沉積蝕刻停止層於工件的背側上。在一些實施方式中，背側源極接觸開口延伸穿過介電層、底部矽層以及底部介電層。在一些情況下，在沉積金屬填充層之後，延伸部件部分地延伸進入金屬填充層。在一些實施例中，金屬填充層並未延伸穿過底部矽層以及底部介電層。
以上概述數個實施例之部件，使得在所屬技術領域中具有通常知識者可以更加理解本發明實施例的面向。在所屬技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並未悖離本發明實施例的精神與範圍，且他們能在不違背本發明實施例之精神和範圍下，做各式各樣的改變、取代和替換。
10C:通道區 10D:汲極區 10S:源極區 20:基板 100:方法 102,104,106,108,110,112,114,116,118,120,122:方框 200:工件(半導體裝置) 201:底矽層 202:絕緣層 203:頂矽層 204:底部犧牲層 205:底部半導體層 206:犧牲層 207:堆疊物 208:通道層 210:鰭狀構造 212:隔離部件 214:界面層 215:介電鰭片 216:閘極介電層 218:閘極電極層 220:閘極結構 222:閘極間隔物 224:內部間隔物部件 225D:汲極部件 225S:源極部件 226:外層 228:內層 230:接觸蝕刻停止層 232:第一層間介電質層 234:閘極蓋層 236:第一介電層 238:閘極接觸導孔 240:第二介電層 242:金屬線 244:第一氧化物層 246:第二氧化物層 248:載體基板 250:蝕刻停止層 252:第二層間介電質層 254:光阻遮罩 255:遮罩開口 256:背側源極接觸開口 258:襯層 260:磊晶延伸部件 262:矽化物層 264:背側源極接觸件 266:埋置電源軌 268:凸型表面 270:平坦表面 300:背側接觸區 2040:底部介電層 2080:通道元件 2602:第一端點部分 2604:第二端點部分 θ:角度
結合所附圖式來閱讀以下細節描述為理解本揭露的最佳方式。應注意的是，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，為了能清楚地討論，可以任意地放大或縮小各種特徵的尺寸。 第1圖根據本揭露的一個或多個面向繪示製造包括埋置電源軌(power rail)的半導體裝置的方法的流程圖。 第2、3、4、5、6、7、8、9、10、11A、12A、13A、14A、15A以及11B、12B、13B、14B、15B圖繪示根據本揭露的一個或多個面向的根據第1圖中的方法的製造過程當中的工件的局部剖面視圖。 第16圖繪示根據本揭露的一個或多個面向的包括與兩個源極接觸件耦合的源極部件的半導體裝置的局部剖面視圖。
200:工件
205:底部半導體層
220:閘極結構
225D:汲極部件
225S:源極部件
226:外層
228:內層
252:第二層間介電質層
258:襯層
260:磊晶延伸部件
262:矽化物層
264:背側源極接觸件
266:埋置電源軌
270:平坦表面
300:背側接觸區
2040:底部介電層
2602:第一端點部分

Claims (14)

  1. 一種半導體裝置結構，包括：一源極部件以及一汲極部件；至少一通道結構，於該源極部件以及該汲極部件之間延伸；一閘極結構，環繞至少一通道結構的每一個；一半導體層，於該閘極結構上；一介電層，於該半導體層上；一摻雜半導體部件，延伸穿過該半導體層以及該介電層，以接觸該源極部件；一金屬接觸插塞，於該摻雜半導體部件上；以及一埋置電源軌(pewer rail)，設置於該金屬接觸插塞上。
  2. 如請求項1所述之半導體裝置結構，更包括：一矽化物層，設置於該摻雜半導體部件與該金屬接觸插塞之間的一界面上。
  3. 如請求項1所述之半導體裝置結構，其中該摻雜半導體部件部分地延伸至該金屬接觸插塞之中。
  4. 如請求項1至3任一項所述之半導體裝置結構，其中該源極部件包括一外層(outer layer)，其與至少一通道結構接觸，以及一內層(inner layer)，與至少一通道結構分隔。
  5. 如請求項4所述之半導體裝置結構，其中該摻雜半導體部件與該內層接觸，且與該外層分隔。
  6. 一種半導體裝置，包括：一源極部件以及一汲極部件；複數個通道元件(channel members)，沿著一方向設置於該源極部件以及該汲 極部件之間；一閘極結構，環繞該複數個通道結構的每一個；一矽層，設置於該閘極結構上；一第一介電層，設置於該矽層上；一第二介電層，設置於該第一介電層上；一金屬接觸部件，設置於該第二介電層中，且於該源極部件上；以及一磊晶延伸部件，設置於該源極部件與該金屬接觸部件之間，其中該第二介電層的一部分延伸穿過該矽層與該第一介電層以與該汲極部件接觸，其中該磊晶延伸部件延伸穿過該矽層以及該第一介電層。
  7. 如請求項6所述之半導體裝置，其中該源極部件、該汲極部件以及該磊晶延伸部件包括矽、矽鍺或鍺。
  8. 如請求項7所述之半導體裝置，其中該源極部件、該汲極部件以及該磊晶延伸部件更包括磷、砷、銻、硼或鎵。
  9. 如請求項7所述之半導體裝置，更包括：一矽化物層，設置於該磊晶延伸部件與該金屬接觸部件之間的一界面上。
  10. 如請求項6至9任一項所述之半導體裝置，其中該磊晶延伸部件包括一端點部分，其延伸至該金屬接觸部件中。
  11. 如請求項10所述之半導體裝置，其中該端點部分包括斜方形(rhombus shape)或圓化的形狀(rounded shape)。
  12. 一種半導體裝置結構的製造方法，包括：接收一工件，包括： 一源極部件以及一汲極部件，設置於一基板上，複數個通道元件，於該源極部件以及該汲極部件之間延伸，該複數個通道元件設置於一底部矽層與一底部介電層上，以及一閘極結構，環繞該複數個通道元件的每一個；接合該工件的一前側至一載體基板，並且翻轉(flipping)該工件；選擇性地移除該基板以從該工件的一背側露出該源極部件以及該汲極部件，其中該背側與該前側為相反側；在沉積一蝕刻停止層於該工件的該背側上之後，沉積一介電層於該工件的該背側上；在沉積該介電層之後，形成穿過該介電層的一背側源極接觸開口以露出該源極部件；以磊晶沉積一延伸部件於該背側源極接觸開口中；以及沉積一金屬填充層於該延伸部件上。
  13. 如請求項12所述之半導體裝置結構製造方法，其中該背側源極接觸開口延伸穿過該介電層、該底部矽層以及該底部介電層。
  14. 如請求項12至13任一項所述之半導體裝置結構的製造方法，其中在沉積該金屬填充層之後，該延伸部件部分地延伸進入該金屬填充層。
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