TWI797697B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI797697B
TWI797697B TW110128104A TW110128104A TWI797697B TW I797697 B TWI797697 B TW I797697B TW 110128104 A TW110128104 A TW 110128104A TW 110128104 A TW110128104 A TW 110128104A TW I797697 B TWI797697 B TW I797697B
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semiconductor device
controller
graphite sheet
heat conduction
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TW110128104A
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TW202215635A (zh
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鴨田涼
高橋秀樹
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日商鎧俠股份有限公司
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Abstract

實施方式提供一種能實現電磁波之屏蔽與散熱性之提高之半導體裝置及其製造方法。  實施方式之半導體裝置包含基板、半導體記憶體、控制器、第1導熱板、石墨片、封裝部及外部電極。基板具有第1面、及位於第1面之相反側之第2面。半導體記憶體設置於第1面。控制器設置於第1面，能控制半導體記憶體。第1導熱板配置於控制器之上。石墨片配置於第1導熱板之上。封裝部將半導體記憶體、控制器、第1導熱板及石墨片封裝。外部電極以複數個設置於基板之第2面。

Description

半導體裝置及其製造方法
本發明之實施方式係關於一種半導體裝置及其製造方法。
近年來，一般的半導體裝置係以利用樹脂加以塑模之封裝狀態使用。作為近年之半導體裝置，球柵陣列(BGA: Ball Grid Array)型固態驅動器(SSD: Solid State Drives)之性能尤其得到了提高。BGA型SSD隨著性能之提高，遭遇了電磁波輻射及發熱量增加之問題。
本發明之實施方式所欲解決之問題係，提供一種能實現電磁波之屏蔽與散熱性之提高之半導體裝置及其製造方法。
實施方式之半導體裝置包含基板、半導體記憶體、控制器、第1導熱板、石墨片、封裝部及外部電極。基板具有第1面、及位於第1面之相反側之第2面。半導體記憶體設置於第1面。控制器設置於第1面，能控制半導體記憶體。第1導熱板配置於控制器之上。石墨片配置於第1導熱板之上。封裝部將半導體記憶體、控制器、第1導熱板及石墨片封裝。外部電極以複數個設置於基板之第2面。
接下來，參照圖式對實施方式進行說明。以下說明之圖式之記載中，相同或類似之部分被標註相同或類似之符號。圖式係模式化之圖。又，以下所示之實施方式係例示用以將技術思想具體化之裝置及方法者，並不對零件之材質、形狀、構造、配置等進行特定。實施方式可加以各種變更。
(第1實施方式)  圖1係表示搭載有本實施方式之半導體裝置1之電子機器2之一例的概略構成圖。電子機器2包含殼體3。殼體3收容電路基板(主板)4。電路基板4包含半導體裝置1及主機控制器5(例如CPU(Central Processing Unit，中央處理單元))。半導體裝置1例如作為BGA型SSD而構成。半導體裝置1作為電子機器2之記憶裝置發揮功能。主機控制器5控制包含半導體裝置1之電子機器2整體之動作。主機控制器5例如包含南橋。
圖2係模式化表示電路基板4之構成之一部分的方塊圖。於電路基板4設置有電源電路7。電源電路7經由電源線8(8a、8b)連接於半導體裝置1及主機控制器5。電源電路7經由電源線8(8a)將電源電壓供給至主機控制器5。又，電源電路7經由電源線8(8b)將電源電壓供給至半導體裝置1。
半導體裝置1與主機控制器5之間設置有複數根信號線6。半導體裝置1經由信號線6與主機控制器5之間進行信號收發。半導體裝置1及主機控制器5例如具有符合快速周邊組件互連(PCI-express: Peripheral Component Interconnect Express，以下稱為PCIe)標準之介面。半導體裝置1及主機控制器5所具有之介面亦可未必為符合PCIe標準之介面。主機控制器5及半導體裝置1所具有之介面例如亦可為符合SAS(Serial Attached Small Computer System Interface ，串列連接之小型電腦系統介面)或SATA(Serial Advanced Technology Attachment，串列進階附接技術)標準之介面。又，主機控制器5及半導體裝置1所具有之介面亦可為符合NVMe(Non Volatile Memory Express，高速非揮發性記憶體)、USB(Universal Serial Bus，通用串列匯流排)等其他標準之介面。
(半導體裝置之構成)  接下來，對半導體裝置1之構成進行說明。
圖3係表示半導體裝置1之構成之一例的方塊圖。圖4係第1實施方式之半導體裝置1之剖視圖。圖5係第1實施方式之半導體裝置1之俯視圖。半導體裝置1具備控制器11、半導體記憶體12、RAM(Random Access Memory，隨機存取記憶體)13、振盪器(OSC)14、EEPROM(Electrically Erasable and Programmable Read Only Memory，電子可抹除可程式化唯讀記憶體)15、溫度感測器16、基板21(封裝基板)、接合線22M及22C、絕緣膜17、第1導熱板34、絕緣片30、石墨片32、封裝部(塑模材料)23、安裝膜24以及焊球(外部電極)25。
控制器11係控制半導體記憶體12之動作之積體電路。控制器11於積體電路之1個晶片上集成有處理器核心、微控制器等。處理器核心、微控制器等協同工作，而作為SoC(System-on-chip，晶片上系統)發揮功能。
半導體記憶體12例如為NAND(Not And，反及)快閃記憶體。半導體記憶體12除了NAND快閃記憶體以外，例如亦可應用NOR(Not Or，反或)型快閃記憶體、阻變記憶體(ReRAM: Resistive Random Access Memory)、相變記憶體(PCM: Phase-Change Memory)、鐵電記憶體(FeRAM: Ferroelectric Random Access Memory)、磁穿隧接面(MTJ: Magneto Tunnel Junction)阻變元件。
RAM13係揮發性記憶體。RAM13例如為DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)。RAM13記憶半導體記憶體12之管理資訊。RAM13例如用於資料之快取等。
振盪器(OSC)14將規定頻率之動作信號供給至控制器11。
EEPROM15係非揮發性記憶體。EEPROM15記憶控制程式等作為固定資訊。
溫度感測器16測量半導體裝置1內之溫度。溫度感測器16將所測量出之溫度作為溫度資訊發送至控制器11。
基板21係多層配線基板。基板21具有第1面21a、及位於第1面21a之相反側之第2面21b。基板21具有電源層28及接地層29。
接合線22M及22C例如為銅線、銀線、金線。接合線22M及22C之粗細例如為直徑20 μm～50 μm左右。
絕緣膜17係具有柔軟性之絕緣膜。對絕緣膜17應用線上膜(Film On Wire，FOW)技術。因此，能使接合線22C之一部分內置於絕緣膜17中。絕緣膜17之厚度例如為約50 μm左右。絕緣膜17之厚度係足以將接合線22C之一部分埋入之厚度。
第1導熱板34例如為矽基板。第1導熱板34亦可為矽基板以外之高導熱性基板。第1導熱板34介隔絕緣膜17配置於控制器11上。又，第1導熱板34配置於絕緣膜17與絕緣片30之間。藉由第1導熱板34，能將產自控制器11之熱高效地傳遞至石墨片32。
絕緣片30例如為氧化鋁片。絕緣片30保護石墨片32。絕緣片30防止石墨片32帶電。
石墨片32作為散熱片使用。半導體記憶體12之熱經由封裝部(塑模材料)23傳遞至石墨片32。又，控制器11之熱經由第1導熱板34傳遞至石墨片32。石墨片32之導熱具有各向異性。石墨片32例如具有於與基板21平行之方向上熱導率高之配向。又，石墨片32亦可具有於與基板21平行之方向、及與基板21垂直之方向上熱導率高之配向。石墨片32之導電性較高。石墨片32例如為電性浮動狀態。又，石墨片32亦可為接地電位。石墨片32配置於第1導熱板34上。石墨片32係以俯視下覆蓋第1導熱板34及控制器11之方式配置。又，石墨片32係以俯視下介隔封裝部(塑模材料)23覆蓋半導體記憶體12之方式配置。石墨片32小於封裝部23。石墨片32小於基板21。石墨片32與絕緣片30之面積大致相等。
封裝部23例如為環氧系樹脂等塑模材料。封裝部23設置於基板21之第1面21a。封裝部23將半導體記憶體12、控制器11、第1導熱板34、絕緣膜17、石墨片32、絕緣片30、接合線22M及接合線22C封裝。
安裝膜24係接著膜。安裝膜24用以將半導體記憶體12及控制器11固定於基板21。
焊球25係連接構件。焊球25例如為焊料。焊球25例如為球狀。焊球25作為將半導體裝置1與外部連接之外部電極使用。焊球25設置於基板21之第2面21b。
(半導體裝置之構造)  接下來，對半導體裝置1之構造進行說明。
如圖4所示，半導體記憶體12載置於基板21之第1面21a。半導體記憶體12藉由安裝膜24固定於第1面21a。複數個半導體記憶體12經由基板21電性連接於控制器11。又，於第1面21a上，將半導體記憶體12與控制器11排列之方向設為X方向，將與X方向正交之方向設為Y方向。又，將與第1面21a垂直之方向設為Z方向。
再者，複數個半導體記憶體12亦可積層。複數個半導體記憶體12於X方向上錯開而沿Z方向積層。又，複數個半導體記憶體12藉由安裝膜24而固定。又，複數個半導體記憶體12藉由接合線22M電性連接於基板21。亦可對安裝膜24應用FOW技術，使其中內置接合線22M。以下，將複數個半導體記憶體12中最下層之半導體記憶體特設為半導體記憶體12Z。半導體記憶體12Z於基板21之第1面21a上，與控制器11隔開距離X1而配置。距離X1之值例如為數mm。
圖6係將第1實施方式之半導體裝置1之一部分構成除外而顯示的圖。於第1實施方式中，控制器11、RAM13及溫度感測器16安裝於與半導體記憶體12相鄰之區域A。
控制器11載置於基板21之第1面21a。控制器11例如藉由安裝膜24固定於基板21之第1面21a。又，控制器11藉由接合線22C電性連接於基板21。
RAM13載置於基板21之第1面21a。再者，RAM13藉由未予圖示之安裝膜24固定於第1面21a。RAM13經由接合線電性連接於基板21。RAM13經由基板21電性連接於控制器11。
溫度感測器16載置於基板21之第1面21a。溫度感測器16例如位於控制器11附近。更具體而言，半導體記憶體12Z、控制器11及RAM13中，控制器11與溫度感測器16之距離最短。
(石墨片)  圖7係第1實施方式之石墨片之構成圖。石墨片32包含石墨烯GF1、GF2、GF3、…、GFn。石墨烯GF1、GF2、GF3、…、GFn構成石墨片32之積層構造。石墨烯GF1、GF2、GF3、…、GFn於1個結晶構造中具有多個六方晶系之共價鍵。相鄰之石墨烯GF1、GF2、GF3、…、GFn彼此藉由凡得瓦力而鍵結。石墨烯GF1、GF2、GF3、…、GFn具有於晶面方向上(XY面上)較於Z軸之厚度方向上大之導熱度(高熱導率)。
作為石墨片32，可使用第1石墨片GF(XY)與第2石墨片GF(XZ)2種石墨片。2種石墨片之配向不同。
圖8係例示第1實施方式之第1石墨片GF(XY)之圖。第1石墨片GF(XY)具有XY配向(第1配向)。第1石墨片GF(XY)之面方向上之熱導率高於厚度方向上之熱導率。第1石墨片GF(XY)例如具有X＝1500(W/mK)左右、Y＝1500(W/mK)左右、Z＝5(W/mK)左右之熱導率。
圖9係例示第1實施方式之第2石墨片GF(XZ)之圖。第2石墨片GF(XZ)具有XZ配向(第2配向)。第2石墨片GF(XZ)之厚度方向上之熱導率高於面方向上之熱導率。第2石墨片GF(XZ)例如具有X＝1500(W/mK)左右、Y＝5(W/mK)左右、Z＝1500(W/mK)左右之熱導率。
第1實施方式之半導體裝置1能使控制器11之熱有效率地向封裝外部逸散。根據第1實施方式，能緩和半導體記憶體12之溫度上升。又，根據第1實施方式，由於溫度感測器16設置於控制器11附近，故而能提高半導體裝置1之溫度檢測精度。又，第1實施方式之半導體裝置1藉由內置石墨片32，能對半導體裝置之內部進行電磁屏蔽。又，第1實施方式之半導體裝置1藉由內置石墨片32，能提高散熱性。
(第1實施方式之變化例)  圖10係第1實施方式之變化例之半導體裝置1之剖視圖。圖11係第1實施方式之變化例之半導體裝置1之俯視圖。圖10及圖11中省略了半導體裝置1所具備之振盪器14及EEPROM15。又，圖11中省略了半導體裝置1之構成中之封裝部(塑模材料)23。
第1實施方式之變化例之半導體裝置1具備基板21(封裝基板)、控制器11、半導體記憶體12、接合線22M及22C、第1導熱板34、絕緣膜17、石墨片32、絕緣片30、封裝部(塑模材料)23、安裝膜24以及焊球25。
圖12係將第1實施方式之變化例之半導體裝置之一部分構成除外而顯示的圖。於第1實施方式之變化例中，控制器11、RAM13及溫度感測器16安裝於與半導體記憶體12相鄰之區域B。複數根接合線22M將最下層之半導體記憶體12Z之端部與基板21電性連接。複數根接合線22C將控制器11周圍之端部與基板21電性連接。
第1實施方式之變化例之半導體裝置1能使控制器11之熱有效率地向封裝外部逸散。根據第1實施方式之變化例，能緩和半導體記憶體12之溫度上升。又，第1實施方式之變化例之半導體裝置1藉由內置石墨片32，能對半導體裝置1之內部進行電磁屏蔽。又，第1實施方式之變化例之半導體裝置1藉由內置石墨片32，能提高散熱性。
(第2實施方式)  圖13係第2實施方式之半導體裝置1之剖視圖。圖13中省略了半導體裝置1所具備之振盪器14、EEPROM15、RAM13及溫度感測器16。
於第2實施方式之半導體裝置1中，接合線22M將半導體記憶體12與基板21電性連接。
第2實施方式之半導體裝置1具備基板21(封裝基板)、控制器11、半導體記憶體12、接合線22M及22C、第1導熱板34、第2導熱板36、絕緣膜17、石墨片32、絕緣片30、封裝部(塑模材料)231及232、安裝膜24以及焊球25。
第2導熱板36係用以使傳導至石墨片32之熱向半導體裝置1之外部釋散之導熱板。第2導熱板36例如為矽基板。再者，第2導熱板36亦可為矽基板以外之高導熱性基板。第2導熱板36配置於石墨片32之上表面。
封裝部231例如為環氧系樹脂等塑模材料。封裝部231將半導體記憶體12、控制器11、第1導熱板34、絕緣膜17、石墨片32、絕緣片30、接合線22M及接合線22C封裝。
封裝部232例如為環氧系樹脂等塑模材料。封裝部232將石墨片32與第2導熱板36封裝。
圖14係第2實施方式之半導體裝置1之俯視圖。圖14中省略了除第1導熱板34、第2導熱板36、絕緣膜17、石墨片32、絕緣片30、封裝部(塑模材料)231及232以外之構成。圖15係將第2實施方式之半導體裝置1之一部分構成除外而顯示的俯視圖。圖15中省略了封裝部(塑模材料)231及232。
第1導熱板34配置於控制器11之上。於控制器11配置有絕緣膜17。第1導熱板34亦可還配置於RAM或溫度感測器之上方。
第2導熱板36大於第1導熱板34。第2導熱板36之上表面露出於封裝部232之外部。因此，能經由第2導熱板36將熱高效地向半導體裝置1之外部釋散。
根據第2實施方式，半導體裝置1內置石墨片32。石墨片32之上配置有第2導熱板36。能使半導體記憶體12及控制器11之熱經由石墨片32逸散至第2導熱板36。又，根據第2實施方式，半導體裝置1具有第1導熱板34與第2導熱板36之間夾著石墨片32之構造。根據第2實施方式，能提高半導體記憶體12及控制器11之散熱速度。又，根據第2實施方式，能使控制器之熱有效率地向封裝外部逸散。根據第2實施方式，能緩和半導體記憶體之溫度上升。又，根據第2實施方式，藉由內置石墨片，能對半導體裝置之內部進行電磁屏蔽。又，根據第2實施方式，藉由內置石墨片，能提高散熱性。
(製造方法)  圖16A係第2實施方式之半導體裝置1之第1剖視圖。
(A1)首先，如圖16A所示，形成基板21，該基板21具有第1面21a、及位於第1面21a之相反側之第2面21b。基板21係多層配線基板，具有電源層28及接地層29。
(A2)接下來，如圖16A所示，於第1面21a側形成半導體記憶體12。半導體記憶體12被多層化。與最下層之半導體記憶體12Z沿X方向隔開距離X1，而形成能控制半導體記憶體12及12Z之控制器11。
(A3)繼而，如圖16A所示，於控制器11之上表面形成接合線22C。又，於半導體記憶體12及12Z之上表面形成接合線22M。
圖16B係第2實施方式之半導體裝置1之第2剖視圖。
(B1)接下來，如圖16B所示，於第1導熱板34上預先形成絕緣膜17。
(B2)繼而，如圖16B所示，於控制器11之上表面配置絕緣膜17與第1導熱板34之積層構造。第1導熱板34以絕緣膜17接合於控制器11之上表面。再者，第1導熱板34亦可介隔絕緣膜17倒裝配置於控制器11之上表面。
圖16C係第2實施方式之半導體裝置1之第3剖視圖。
(C1)接下來，如圖16C所示，於控制器11之上表面介隔絕緣膜17形成第1導熱板34。控制器11之上表面之接合線22C藉由FOW技術，一部分內置於絕緣膜17中。
(C2)繼而，如圖16C所示，於石墨片32之背面一體形成絕緣片30。
(C3)接下來，如圖16C所示，於第1導熱板34之上介隔絕緣片30形成石墨片32。
(C4)繼而，如圖16C所示，形成將半導體記憶體12及12Z、控制器11、接合線22M及22C、絕緣膜17、第1導熱板34、絕緣片30以及石墨片32封裝之封裝部231。要使石墨片32之上表面自第1封裝部231露出。
圖16D係第2實施方式之半導體裝置1之第4剖視圖。
(D)接下來，如圖16D所示，於石墨片32上之與絕緣片30對向之面形成第2導熱板36。
(E1)繼而，如圖13所示，形成將封裝部231、石墨片32及第2導熱板36封裝之第2封裝部232。要使第2導熱板36之上表面自第2封裝部232露出。
(E2)接下來，如圖13所示，於第2面21b側形成複數個焊球25。
(第2實施方式之變化例)  圖17係第2實施方式之變化例之半導體裝置之剖視圖。第2實施方式之變化例之半導體裝置中，與半導體記憶體12連接之接合線22M之連接構造不同。其他構成與第2實施方式之半導體裝置相同。圖17中省略了半導體裝置1所具備之振盪器14、EEPROM15、RAM13及溫度感測器16。以下，對與第2實施方式不同之構成進行說明。
於第2實施方式之變化例之半導體裝置中，接合線22M將複數個半導體記憶體12連接。又，接合線22M將最下層之半導體記憶體12Z與基板21電性連接。
第2實施方式之半導體裝置1具備基板21(封裝基板)、控制器11、半導體記憶體12、接合線22M及22C、第1導熱板34、第2導熱板36、絕緣膜17、石墨片32、絕緣片30、封裝部(塑模材料)231及232、安裝膜24以及焊球25。
根據第2實施方式之變化例，半導體裝置1內置石墨片32。石墨片32之上配置有第2導熱板36。能使半導體記憶體12及控制器11之熱經由石墨片32逸散至第2導熱板36。又，根據第2實施方式之變化例，半導體裝置1具有第1導熱板34與第2導熱板36之間夾著石墨片32之構造。根據第2實施方式之變化例，能提高半導體記憶體12及控制器11之散熱速度。又，根據第2實施方式之變化例之半導體裝置，能使控制器之熱有效率地向封裝外部逸散。根據第2實施方式之變化例，能緩和半導體記憶體之溫度上升。又，根據第2實施方式之變化例之半導體裝置，藉由內置石墨片，能對半導體裝置1之內部進行屏蔽。又，根據第2實施方式之半導體裝置，藉由內置石墨片，能提高散熱性。
(第3實施方式)  圖18係第3實施方式之半導體裝置1之剖視圖。又，圖19係第3實施方式之半導體裝置1之俯視圖。
根據第3實施方式之半導體裝置1，能使第1導熱板34之熱向半導體裝置1之外部逸散。第3實施方式之半導體裝置1中，於控制器11之上部介隔絕緣膜17配置有第1導熱板34。第1導熱板34之上表面自封裝部231露出。
根據第3實施方式之半導體裝置1，能防止半導體裝置1之內部積熱。控制器11之上配置有第1導熱板34以吸熱。第1導熱板34之上表面自封裝部231露出。即，設置有能使控制器11之熱向半導體裝置1之外部逸散之路徑。
(第4實施方式)  圖20係第4實施方式之半導體裝置之剖視圖。
第4實施方式之半導體裝置中，於控制器11之上部介隔絕緣膜17配置有第1導熱板34。進而，第1導熱板34之上表面與基板21之間連接有接合線22T。接合線22T藉由封裝部23而封裝。
接合線22T係用以導熱之引線。接合線22T例如為銅線、銀線或金線。接合線22T之粗細例如為直徑20 μm～50 μm左右。藉由接合線22T，能使產自控制器11之熱向基板21及焊球25側逸散。為了提高熱導率，亦可增加接合線22T之根數。
根據第4實施方式之半導體裝置，能使控制器之熱有效率地向封裝外部逸散。根據第4實施方式之半導體裝置，能緩和半導體記憶體之溫度上升。
(比較例)  SSD於1個封裝內搭載有SoC(System-on-a-chip)與NAND。因此，NAND易受SoC發熱之影響。關於將NAND與SoC之熱阻斷之技術，已知有PoP(Package on Package，堆疊式封裝)及散熱導孔(TMV: Thermal Via)。PoP係一種使IC(Integrated Circuit，積體電路)或零件積層安裝於IC封裝之上之技術。TMV係一種使利用基板之表面安裝零件之散熱效果提高之技術。TMV就構造而言，係一種於基板設置貫通孔，將基板正面與背面之銅箔相連，增加用於散熱之面積與體積，即降低熱阻之方法。
實施方式係例示，發明之範圍並不限定於此。例如，於上述各實施例中，控制器與基板之間係以接合線之方式接合，但亦可取而代之，以覆晶之方式接合。覆晶係不經引線，而將設置於晶片表面之凸塊與基底基板直接接合。藉由該覆晶接合，能縮小控制器之厚度，相應地，能將導熱板厚膜化而使其散熱性進一步提高。
[相關申請案]  本申請案享受以日本專利申請案2020-164568號(申請日：2020年9月30日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1:半導體裝置 2:電子機器 3:殼體 4:電路基板(主板) 5:主機控制器(CPU) 6:信號線 7:電源電路 8:電源線 8a:電源線 8b:電源線 11:控制器 12:半導體記憶體(NAND) 12Z:半導體記憶體(NAND) 13:RAM 14:振盪器(OSC) 15:EEPROM 16:溫度感測器 17:絕緣膜(FOW) 21:基板 21a:第1面 21b:第2面 22C:接合線 22M:接合線 22T:接合線 23:封裝部(塑模材料) 24:安裝膜 25:焊球 28:電源層 29:接地層 30:絕緣片 32:石墨片 34:第1導熱板 36:第2導熱板 231:封裝部(塑模材料) 232:封裝部(塑模材料) GF(XY):第1石墨片 GF(XZ):第2石墨片 GF1,GF2,GF3,…,GFn:石墨烯 X1:X方向之距離
圖1係表示搭載有第1實施方式之半導體裝置之電子機器之一例的概略構成圖。  圖2係模式化表示第1實施方式之電路基板之構成之一部分的方塊圖。  圖3係表示第1實施方式之半導體裝置之構成之一例的方塊圖。  圖4係第1實施方式之半導體裝置之剖視圖。  圖5係第1實施方式之半導體裝置之俯視圖。  圖6係將第1實施方式之半導體裝置之一部分構成除外而顯示的圖。  圖7係可應用於第1實施方式之半導體裝置之石墨片之構成圖。  圖8係例示可應用於第1實施方式之半導體裝置之第1石墨片GF(XY)之圖。  圖9係例示可應用於第1實施方式之半導體裝置之第2石墨片GF(XZ)之圖。  圖10係第1實施方式之變化例之半導體裝置之剖視圖。  圖11係第1實施方式之變化例之半導體裝置之俯視圖。  圖12係將第1實施方式之變化例之半導體裝置之一部分構成除外而顯示的圖。  圖13係第2實施方式之半導體裝置之剖視圖。  圖14係第2實施方式之半導體裝置之俯視圖。  圖15係將第2實施方式之半導體裝置之一部分構成除外而顯示的俯視圖。  圖16A係第2實施方式之半導體裝置之第1剖視圖  圖16B係第2實施方式之半導體裝置之第2剖視圖。  圖16C係第2實施方式之半導體裝置之第3剖視圖。  圖16D係第2實施方式之半導體裝置之第4剖視圖。  圖17係第2實施方式之變化例之半導體裝置之剖視圖。  圖18係第3實施方式之半導體裝置之剖視圖。  圖19係第3實施方式之半導體裝置之俯視圖。  圖20係第4實施方式之半導體裝置之剖視圖。
1:半導體裝置
11:控制器
12:半導體記憶體
12Z:半導體記憶體
17:絕緣膜
21:基板
21a:第1面
21b:第2面
22C:接合線
22M:接合線
23:封裝部(塑模材料)
24:安裝膜
25:焊球
28:電源層
29:接地層
30:絕緣片
32:石墨片
34:第1導熱板
X1:X方向之距離

Claims (20)

  1. 一種半導體裝置，其包含：基板，其具有第1面、及位於上述第1面之相反側之第2面；半導體記憶體，其設置於上述第1面；控制器，其設置於上述第1面，能控制上述半導體記憶體；第1導熱板，其配置於上述控制器之上；石墨片，其配置於上述第1導熱板之上；第1封裝部，其將上述半導體記憶體、上述控制器、上述第1導熱板及上述石墨片封裝；及複數個外部電極，其等設置於上述第2面；其中上述第1封裝部之一部分係設置於上述半導體記憶體與上述石墨片之間。
  2. 如請求項1之半導體裝置，其中上述石墨片係以覆蓋上述半導體記憶體、上述控制器及上述第1導熱板之方式配置。
  3. 如請求項1或2之半導體裝置，其中於與上述第1面對向之上述石墨片之面進而具備絕緣片。
  4. 如請求項3之半導體裝置，其進而包含：第1接合線，其與上述控制器之上表面連接；及 絕緣膜，其包含上述第1接合線之一部分，配置於上述控制器之上表面；且上述第1導熱板配置於上述絕緣膜與上述絕緣片之間。
  5. 如請求項4之半導體裝置，其包含：第2導熱板，其配置於上述石墨片之上表面；及第2封裝部，其將上述石墨片與上述第2導熱板封裝。
  6. 如請求項5之半導體裝置，其中上述石墨片與上述絕緣片之面積大致相等。
  7. 如請求項1或2之半導體裝置，其中上述石墨片小於上述第1封裝部。
  8. 如請求項1或2之半導體裝置，其中上述石墨片小於上述基板。
  9. 如請求項5之半導體裝置，其中上述第2導熱板大於上述第1導熱板。
  10. 如請求項1或2之半導體裝置，其中上述石墨片具有與上述基板垂直之方向相比，於與上述基板平行之方向上熱導率高之配向。
  11. 如請求項1或2之半導體裝置，其中上述石墨片具有與上述基板平行之方向相比，於與上述基板垂直之方向上熱導率高之配向。
  12. 如請求項1或2之半導體裝置，其中上述半導體記憶體有複數個，且複數個上述半導體記憶體係於複數個上述半導體記憶體與上述控制器之排列方向上錯開而積層。
  13. 如請求項1或2之半導體裝置，其進而包含溫度感測器，且上述溫度感測器安裝於上述第1面之與上述半導體記憶體相鄰之區域。
  14. 一種半導體裝置，其包含：基板，其具有第1面、及位於上述第1面之相反側之第2面；半導體記憶體，其設置於上述第1面；控制器，其設置於上述第1面，能控制上述半導體記憶體；導熱板；封裝部，其將上述半導體記憶體、上述控制器及上述導熱板封裝；及複數個外部電極，其等設置於上述第2面；其中上述封裝部具有上表面，上述導熱板於上述封裝部之上述上表面露 出，上述封裝部係設置於上述半導體記憶體與上述封裝部之上述上表面之間。
  15. 如請求項14之半導體裝置，其進而包含：第1接合線，其與上述控制器之上表面連接；及絕緣膜，其包含上述第1接合線之一部分，配置於上述控制器之上表面；且上述導熱板介隔上述絕緣膜配置於上述控制器之上表面。
  16. 如請求項14之半導體裝置，其進而包含：將上述導熱板之上表面與上述基板連接之第2接合線。
  17. 如請求項16之半導體裝置，其中上述封裝部將上述第2接合線封裝。
  18. 如請求項15之半導體裝置，其中上述導熱板之上表面露出於上述封裝部之外部。
  19. 一種半導體裝置之製造方法，其中準備基板，該基板具有第1面、及位於上述第1面之相反側之第2面；於上述第2面形成複數個焊球；於上述第1面形成半導體記憶體；於上述第1面，與上述半導體記憶體隔開，而形成能控制上述半導體 記憶體之控制器；於上述控制器之上表面介隔絕緣膜形成第1導熱板；於上述第1導熱板之上形成石墨片；以於上述半導體記憶體與上述石墨片之間設置第1封裝部之一部分之方式，形成將上述半導體記憶體、上述控制器及上述石墨片封裝之上述第1封裝部；於上述石墨片之上形成第2導熱板；及形成將上述石墨片與上述第2導熱板封裝之第2封裝部。
  20. 如請求項19之半導體裝置之製造方法，其中於上述控制器之上形成第1接合線；於上述第1導熱板之上形成上述絕緣膜；及於上述控制器之上介隔上述絕緣膜形成上述第1導熱板。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102867793A (zh) * 2012-08-14 2013-01-09 日月光半导体制造股份有限公司 热界面材料及半导体封装结构
US20200027818A1 (en) * 2018-07-20 2020-01-23 Samsung Electronics Co., Ltd. Semiconductor package
TW202010071A (zh) * 2018-08-14 2020-03-01 台灣積體電路製造股份有限公司 半導體封裝

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9721868B2 (en) * 2009-07-30 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit (3DIC) having a thermally enhanced heat spreader embedded in a substrate
JP2013184921A (ja) * 2012-03-07 2013-09-19 Shiseido Co Ltd 時計遺伝子の発現調節剤
US8475775B1 (en) * 2012-08-24 2013-07-02 The Uab Research Foundation Retinoids and use thereof
WO2014045671A1 (ja) 2012-09-21 2014-03-27 株式会社村田製作所 電子機器
KR20140057979A (ko) * 2012-11-05 2014-05-14 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR20140057982A (ko) * 2012-11-05 2014-05-14 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
JP6235423B2 (ja) * 2014-06-30 2017-11-22 東芝メモリ株式会社 半導体装置
JP2016192444A (ja) 2015-03-30 2016-11-10 株式会社東芝 半導体装置
US9823691B2 (en) * 2015-07-23 2017-11-21 Toshiba Memory Corporation Semiconductor storage device
JP2018018853A (ja) 2016-07-25 2018-02-01 レノボ・シンガポール・プライベート・リミテッド 電子デバイス及び電子機器
CN106735078B (zh) * 2016-11-18 2019-07-05 中国科学院金属研究所 一种非晶合金或其复合材料的连续精密成形设备和工艺
KR102439761B1 (ko) * 2017-12-22 2022-09-02 삼성전자주식회사 전자 장치 및 전자 장치의 제조 방법
KR102507541B1 (ko) * 2018-10-24 2023-03-09 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US20210098381A1 (en) * 2019-09-29 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102867793A (zh) * 2012-08-14 2013-01-09 日月光半导体制造股份有限公司 热界面材料及半导体封装结构
US20200027818A1 (en) * 2018-07-20 2020-01-23 Samsung Electronics Co., Ltd. Semiconductor package
TW202010071A (zh) * 2018-08-14 2020-03-01 台灣積體電路製造股份有限公司 半導體封裝

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