TWI779569B - 應用於功率轉換器的封裝結構 - Google Patents

應用於功率轉換器的封裝結構 Download PDF

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TWI779569B
TWI779569B TW110114295A TW110114295A TWI779569B TW I779569 B TWI779569 B TW I779569B TW 110114295 A TW110114295 A TW 110114295A TW 110114295 A TW110114295 A TW 110114295A TW I779569 B TWI779569 B TW I779569B
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power
electrode
power transistor
metal
chip
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TW110114295A
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TW202209608A (zh
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方遲清
葉佳明
趙晨
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大陸商矽力杰半導體技術（杭州）有限公司
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Abstract

本發明提供了一種適用於功率轉換器的封裝結構，其中，第一功率電晶體和控制和驅動電路集成於同一顆晶片，可以更好地實現第一功率電晶體的高頻開關動作，提高第一功率電晶體的工作頻率，降低開關損耗。第二功率電晶體集成於獨立的第二晶片中，第一晶片和第二晶片分立於封裝結構中，對第二功率電晶體的控制和驅動動作不會對第一晶片產生干擾或者其他負面影響，提高了可靠性。第一晶片和第二晶片之間可以通過大面積的連接結構進行連接，實現了較低的互連電阻，提升了大電流處理能力。

Description

應用於功率轉換器的封裝結構
本發明係關於半導體技術領域，更具體地，關於一種應用於功率轉換器的封裝結構。
功率轉換器是一種將輸入電壓轉換為恆定的輸出電壓或者輸出電流的轉換電路。根據輸入電壓和輸出電壓之間的大小關係，功率轉換器可以設置為不同的功率拓撲結構，例如降壓型，升壓型或者升降壓型。相同的是，功率轉換器包括主功率開關和整流開關，以及電感和輸出電容。四個基本器件之間不同的連接方式來獲得不同的功率級拓撲結構。控制和驅動電路控制主功率開關工作在高頻狀態，根據輸出電壓的回饋資訊，控制主功率開關的導通占空比，從而在輸出端獲得恆定的輸出電壓。 電子技術的發展，使得對小型化和集成化的要求越來越高。通過現有的製造製程，可以將主功率開關、整流開關和控制和驅動電路分別製造，然後通過封裝製程將主功率開關、整流開關和控制和驅動電路封裝於一顆晶片中。這樣的方式，不可避免的晶片面積會比較大。另一種方式為將主功率開關、整流開關和控制和驅動電路全部集成，這樣可以減小晶片的面積，但是對製造製程的要求非常高。
有鑑於此，本發明的目的在於提供一種能夠兼顧小型化和製造製程難度的新型的應用於功率轉換器的封裝結構。 根據本發明的一方面，提供一種應用於功率轉換器的封裝結構，包括： 第一晶片，至少包括第一功率電晶體和第一控制和驅動電路； 第二晶片，至少包括第二功率電晶體； 連接裝置，用以在所述封裝結構內部，通過所述連接裝置將所述第一功率電晶體和第二功率電晶體依次串聯耦接在所述封裝結構的引線框架的高電平引腳和低電平引腳之間； 所述第一功率電晶體和所述第二功率電晶體的公共連接點通過低互連電阻的金屬連接結構耦接至所述引線框架的輸出引腳。 較佳的，所述第二功率電晶體被配置為具有垂直電流流向的功率器件。 較佳的，所述第一功率電晶體與所述高電平引腳之間的連接，所述第二功率電晶體與所述低電平引腳之間的連接，通過低互連電阻的金屬連接結構或者通過堆疊式的直接連接方式來實現。 較佳的，低互連電阻的金屬連接結構被配置為片狀的金屬夾結構或者重佈線金屬結構。 較佳的，所述第一功率電晶體的控制電極和第一功率電極和第二功率電極位於所述第一晶片的同一表面。 較佳的，所述第二功率電晶體的第一功率電極和所述第二功率電極位於所述第二晶片的不同表面。 較佳的，所述第一晶片和第二晶片並行排列。 較佳的，所述連接裝置包括金屬夾結構，以通過焊接層與所述第一功率電晶體的第二功率電極和所述第二功率電晶體的第一功率電極電耦接，並連接至引線框架的相應引腳。 較佳的，所述連接裝置包括金屬重佈線結構，所述第一功率電晶體的第二電極和所述第二功率電晶體的第一電極，通過焊接製程，與所述金屬重佈線層連接，並經由所述金屬重佈線結構連接至引線框架的相應引腳。 較佳的，所述第一功率電晶體的第一功率電極和第二功率電極的電位區域位於所述第一晶片的相對兩側區域，所述第一功率電晶體的第二功率電極的電位區域位於靠近第二晶片的一側。 較佳的，所述連接裝置包括低互連電阻的金屬連接結構，以在所述封裝結構內部將所述第二功率電晶體的第一功率電極和所述第一功率電晶體的第二功率電極進行連接，以容納大電流和降低互連電阻。 較佳的，所述低互連電阻的金屬連接結構包括與所述第一功率電晶體的第二功率電極相連的第一部分和與所述第二功率電晶體的第一功率電極相連的第二部分，所述第一部分和第二部分相接觸。 較佳的，所述第一部分被配置為圖案化的重佈線金屬結構，以將所述第一功率電晶體的第二功率電極引出。 較佳的，所述第二部分被配置為金屬夾結構。 較佳的，所述圖案化的重佈線金屬結構包括電氣引線和指狀結構；所述指狀結構與電極引出結構相連接，所述電氣引線與所述指狀結構相連接，以將相應的電位引出。 較佳的，其特徵在於，所述圖案化的重佈線金屬結構包括第一金屬層，焊接結構和第二金屬層；所述第一金屬層的第一表面與相同電位的電極引出相連接，所述焊接結構與所述第一金屬層的第二表面相連接，並將所述電極電位重新佈設於第一晶片的相應區域；所述第二金屬層的第一表面與所述焊接結構相連接，並通過第二表面與外部連接。 較佳的，所述第一晶片和第二晶片堆疊排列。 較佳的，所述第二晶片正裝，所述第一晶片倒裝，部分堆疊於所述第二晶片上方。 較佳的，所述第一功率電晶體的第二功率電極區域和所述第二功率電晶體的第一功率電極區域沿所述封裝結構的垂直方向重疊。 較佳的，所述連接裝置包括金屬連接結構，其第一表面通過可焊接結構與所述第一功率電晶體的第二功率電極電連接，第二表面通過可焊接結構與所述第二功率電晶體的第一功率電極電連接，並通過所述金屬連接結構連接至引線框架的相應引腳。 較佳的，所述第一控制和驅動電路中的驅動電極通過金屬連接結構連接至所述第二功率電晶體的控制電極，所述控制電極與所述第一功率電極位於同一表面。 較佳的，所述金屬連接結構配置為金屬凸塊或者金屬重佈線結構。 較佳的，所述第一功率電晶體的第一功率電極通過金屬凸塊或者金屬重佈線結構連接至引線框架的相應引腳。 較佳的，所述第二功率電晶體的第一功率電極和所述第二功率電極位於所述第二晶片的同一表面。 較佳的，所述第一功率電晶體與所述高電平引腳之間的連接，所述第二功率電晶體與所述低電平引腳之間的連接，以及所述第二功率電晶體的第一功率電極和所述第二功率電極之間的連接通過低互連電阻的金屬連接結構或者通過堆疊式的直接連接方式來實現。 較佳的，所述第二功率電晶體的控制電極與第一功率電極位於不同表面，所述第一控制和驅動電路中的驅動電極和所述第一功率電極通過金屬連接結構連接至所述引線框架的同一引腳。 較佳的，還包括塑封體，以包覆所述第一晶片，第二晶片，所述連接裝置和引線框架，並將所述引腳部分裸露於所述塑封體外。 通過依據本發明的封裝結構，第一功率電晶體和控制和驅動電路集成於同一顆晶片，可以更好地實現第一功率電晶體的高頻開關動作，提高第一功率電晶體的工作頻率，降低開關損耗。第二功率電晶體集成於獨立的第二晶片中，第一晶片和第二晶片分立於封裝結構中，對第二功率電晶體的控制和驅動動作不會對第一晶片產生干擾或者其他負面影響，提高了可靠性。第一晶片和第二晶片之間可以通過大面積的連接結構進行連接，實現了較低的互連電阻，提升了大電流處理能力。
以下將參照附圖更詳細地描述本發明。在各個附圖中，相同的元件採用類似的附圖標記來表示。為了清楚起見，附圖中的各個部分沒有按比例繪製。此外，可能未示出某些公知的部分。 應當理解，在描述結構時，當將一層、一個區域稱為位於另一層、另一個區域“上面”或“上方”時，可以指直接位於另一層、另一個區域上面，或者在其與另一層、另一個區域之間還包含其它的層或區域。並且，如果將結構翻轉，該一層、一個區域將位於另一層、另一個區域“下面”或“下方”。 如果為了描述直接位於另一層、另一個區域上面的情形，本文將採用“A直接在B上面”或“A在B上面並與之鄰接”的表述方式。在本申請中，“A直接位於B中”表示A位於B中，並且A與B直接鄰接。 在下文中描述了本發明的許多特定的細節，例如結構、材料、尺寸、處理製程和技術，以便更清楚地理解本發明。但正如本領域的技術人員能夠理解的那樣，可以不按照這些特定的細節來實現本發明。 本發明提供了一種適用於功率轉換器的封裝結構，包括：第一晶片，至少包括第一功率電晶體和第一控制和驅動電路；第二晶片，至少包括第二功率電晶體；連接裝置，用以在所述封裝結構內部，通過所述連接裝置將所述第一功率電晶體和第二功率電晶體依次串聯耦接在所述封裝結構的引線框架的高電平引腳和低電平引腳之間；所述第一功率電晶體和所述第二功率電晶體的公共連接點通過低互連電阻的金屬連接結構耦接至所述引線框架的輸出引腳。 通過這種封裝結構，第一方面，第一功率電晶體和控制和驅動電路集成於同一顆晶片，控制電極和驅動信號的連接可以直接通過晶片內部的連接結構進行，例如金屬層等。因此不再需要類似現有技術中心的晶片外部的實現方式，例如金屬打線方式，更甚者，或者是在封裝外部的引腳連接的實現方式。這樣的實現方式，可以更好地實現第一功率電晶體的高頻開關動作，提高第一功率電晶體的工作頻率，降低開關損耗。第二方面，第二功率電晶體集成於獨立的第二晶片中，第一晶片和第二晶片分立於封裝結構中，對第二功率電晶體的控制和驅動動作不會對第一晶片產生干擾或者其他負面影響，提高了可靠性。同時，當第二晶片僅作為第二功率電晶體時，晶片的面積可以做的更大，從而降低導通電阻，進一步的降低導通損耗。第三方面，所述第二功率電晶體被配置為具有垂直電流流向的功率器件。第二功率電晶體被配置為第一功率電極和第二功率電極之間的電流流向為垂直方向，例如，第二晶片可以為VDMOS電晶體，或者source down LDMOS電晶體。與第一晶片中的第一功率電晶體的類型不相同，例如，第一功率電晶體可以為LDMOS電晶體。不同類型的功率電晶體的選擇，可以方便的在封裝結構內部完成第一功率電晶體和第二功率電晶體相互之間的連接，並通過封裝結構的引腳串聯連接在高電位(例如輸入電壓源)和低電位(例如地電位)之間，抗干擾能力增強。 另一方面，第二功率電晶體的第一功率電極和第二功率電極也可以位於第二晶片的同一表面。 第一功率電晶體與高電平引腳之間的連接，第二功率電晶體與所述低電平引腳之間的連接，以及第二功率電晶體的第一功率電極和所述第二功率電極之間的連接通過低互連電阻的金屬連接結構或者通過堆疊式的直接連接方式來實現。 以下以功率轉換器為降壓型功率級拓撲結構，以及主功率電晶體(第一功率電晶體)和整流功率電晶體(第二功率電晶體)為MOSFET電晶體為例來進行本實施例的說明。對應的，第一功率電極為MOSFET電晶體的汲極，第二功率電極為MOSFET電晶體的源極，控制電極為MOSFET電晶體的閘極。 參考圖1A所示的降壓型功率轉換器的原理圖。在降壓型拓撲結構中，第一功率電晶體Q1的汲極接收輸入電壓Vin，第一功率電晶體Q1的源極和第二功率電晶體Q2的汲極相連接後與電感L的一端相連接，第二功率電晶體Q2的源極連接至地電位。控制和驅動電路5根據接收到的輸出電壓Vout的資訊和基準電壓資訊Vref生成的主管驅動信號GH至第一功率電晶體Q1的閘極，進而控制第一功率電晶體Q1的開關動作，以及整流管驅動信號GL至第二功率電晶體Q2的閘極，進而控制第二功率電晶體Q2的開關動作。通過這種逐週期的高頻控制，使得輸出電壓Vout維持為與基準電壓Vref相一致。 參考圖1B，所示為依據本發明第一實施例的應用於功率轉換器的封裝結構。 依據該實施例的封裝結構包括： 第一晶片1，將主功率電晶體和控制和驅動電路單顆集成；其第一功率電極11(汲極)、第二功率電極12(源極)以及控制和驅動電極(13)均位於第一晶片的同一表面(上表面)上。 第二晶片2，將整流功率電晶體單顆集成；其第一功率電極21(汲極)和第二功率電極22(源極)位於第二晶片的不同表面上，使得流過第一功率電極21(汲極)和第二功率電極22(源極)的電流流向為垂直方向；這裡，第一功率電極21(汲極)位於第二晶片的上表面，第二功率電極22(源極)位於第二晶片的下表面(圖中未示出)；控制和驅動電極(13)可以位於第二晶片的上表面或者下表面。在本實施例中，控制和驅動電極(13)與第一功率電極21(汲極)均位於第二晶片的上表面。 引線框架，包括位於內部區域的基底31和位於外緣區域的引腳32。基底31用以給第一晶片1和第二晶片2提供機械支撐以及必要的電性連接。這裡，第一晶片1和第二晶片2並行排列，均位於基底31的上表面上。 連接裝置，用以在封裝結構內部，將需要進行電性連接的不同電極進行連接。包括但不限於第一連接結構41和第二連接結構42。在降壓型拓撲結構中，第一功率電晶體的汲極接收輸入電壓，第一功率電晶體的源極和第二功率電晶體的汲極相連接後與電感的一端相連接，第二功率電晶體的源極連接至地電位。 為了實現上述連接關係，第一功率電晶體的汲極通過第一連接結構41連接至相應的引腳32，引腳32用以接收輸入電壓源，從而實現了第一功率電晶體的汲極和輸入電壓源之間的連接通路。第一連接結構41配置為片狀連接結構，具有較大的面積以及較低的導通電阻以容納較大的電流。第一連接結構41可以為銅夾等結構，通過位於銅夾和第一功率電晶體的汲極區域的焊接層進行連接，並通過銅夾連接至對應的引線框架的引腳。 第一功率電晶體的源極和第二功率電晶體的汲極通過第二連接結構42相連接。位於第二晶片2的下表面的源極(圖中未示出)，可以理解，通過另一導電連接結構連接至相應的引腳32。 如圖1B所示，將第一晶片1的控制和驅動電極13和第一功率電晶體的電極(源極和汲極)位於同一表面(上表面)。佈設控制和驅動電極13和第一功率電晶體的電極，使得第一功率電晶體的電極和控制和驅動電極13位於第一晶片1的上表面的相對兩側。當需要增加第一功率電晶體的性能時，例如耐壓或者電流，可以沿著遠離控制和驅動電極的方向衍生，方便拓展而不必受控制和驅動電極13的位置的影響，以及可以不改變原有控制和驅動電極13的位置。 在該實施例中，第二晶片2的控制電極23(閘極)和第一晶片1的控制和驅動電極13均位於遠離基底31的一側。因此，第一晶片1中的控制和驅動電路所產生的驅動信號GL對應的控制和驅動電極可以在封裝結構內部，通過金屬連接結構，例如鍵合引線，連接至第二晶片2的控制電極23。 參考圖1C，所示為圖1B所示的依據本發明應用於功率轉換器的封裝結構沿A--A’的第一示例剖面圖。 在該示例中，第一功率電晶體的源極和第二功率電晶體的汲極通過第二連接結構42相連接。第二連接結構42被配置為銅夾結構42。第二晶片2上表面的汲極電極通過焊接層25與銅夾結構42相連接。第一晶片1上表面的源極電極通過焊接層15也與銅夾結構42相連接。因此，通過銅夾結構42將第一功率電晶體的源極和第二功率電晶體的汲極連接在一起，並通過銅夾結構42引出至相應的引腳32。 位於第二晶片2的下表面的源極電極可以通過導電層24引出。一種實現方式為，導電層24可以直接與圖案化的基底31相連接，進而引出至相應的引腳32。可以理解，導電層可以設置為包括焊接層和金屬層，或者僅包括可黏接導電層等不同形式的導電結構。另一種實現方式為，導電層24可以設置為重佈線層結構，以將源極電極引出至相應的引腳32。重佈線層結構和基底31之間可以設置黏接層，以將第二晶片2安裝固定於基底31上。第一晶片1的下表面可以通過設置絕緣的黏接層14安裝固定於基底31上。 大面積的成片狀的銅夾結構，可以承受較大的電流，並且具有較小的導通電阻，降低損耗。 參考圖1D，所示為圖1B所示的依據本發明應用於功率轉換器的封裝結構沿A--A’的第二示例剖面圖。 與圖1C所示的第一示例不同的是，第二連接結構42被配置為重佈線金屬結構42。 第二晶片2上表面的汲極電極通過金屬凸塊層25與重佈線金屬結構42相連接。 第一晶片1上表面的源極電極通過金屬凸塊層15也與重佈線金屬結構42相連接。因此，通過重佈線金屬結構42將第一功率電晶體的源極和第二功率電晶體的汲極連接在一起，並通過重佈線金屬結構42引出至相應的引腳32。 類似的，大面積的成片狀的重佈線金屬結構，可以承受較大的電流，並且具有較小的導通電阻，降低損耗。 應當理解，圖1C和圖1D所示的封裝結構僅示出了源極電極和引腳之間實現電連接關係的示意圖，焊接層25的上下表面，導電層24的上下表面均可以佈設所需要的其他層。 以上依據本發明第一實施例的封裝結構，還包括塑封體，用以將引線框架，第一晶片，第二晶片，連接裝置進行塑封，並將引線框架的引腳裸露所述塑封體外，以通過引腳實現外部連接。 參考圖2A，所示為依據本發明第二實施例的應用於功率轉換器的封裝結構。 與圖1A所示的實施例不同的是，在該實施例中，第一晶片1和第二晶片2堆疊排列，顯然進一步的降低了封裝面積。 具體的，第二晶片2正裝於基底31之上，第一晶片1倒裝於第二晶片2之上。並且，根據第一晶片1的電極分佈區域，沿著垂直方向，第一晶片1和第二晶片2部分重疊。 第二功率電晶體的第一功率電極21(汲極)區域和第一功率電晶體的第二功率電極12(源極)區域沿著封裝結構的垂直方向重疊。 第一功率電晶體的第二功率電極12(源極)區域倒扣於第二功率電晶體的第一功率電極21(汲極)區域上方，使得第一功率電晶體的第二功率電極12(源極)和第二功率電晶體的第一功率電極21(汲極)直接相連接。 一種實現方式為，設置位於第一功率電晶體的第二功率電極12(源極)和第二功率電晶體的第一功率電極21(汲極)之間的第一連接結構41，將兩者進行連接後，並連接至引線框架的相應引腳32。 第二晶片2的控制電極23和相應的第一晶片1的控制和驅動電極13之間的連接，可以在封裝結構內部，通過金屬連接結構將兩者進行連接。例如，佈設第二晶片2的控制電極23對應的焊墊和相應的第一晶片1的控制和驅動電極13對應的焊墊的位置，使之沿垂直方向重疊。這樣，兩者之間通過金屬凸塊進行電連接，實現製程簡易，連接的可靠性也比較高。如果第二晶片2的控制電極23對應的焊墊和相應的第一晶片1的控制和驅動電極13對應的焊墊無法滿足上述的垂直位置關係，也可以通過重佈線層製程來實現兩者之間的連接。 剩餘的第一晶片1的控制和驅動電極13，通過倒裝封裝製程佈設於圖案化的引腳32上。 第一晶片1的第一功率電極11與對應的引腳32的之間的連接，可以通過連接在第一晶片1的第一功率電極11和圖案化的引腳32之間的金屬凸塊進行連接；或者可以通過重佈線層製程來實現。 圖2A所示的封裝結構，相比於圖1A所示的封裝結構，一方面，封裝面積可以進一步的減小；另一方面，晶片與引腳的之間，以及晶片之間的相互連接，均可以不再用金屬打線的連接方式，可靠性更高。 參考圖2B，所示為圖2A所示的依據本發明應用於功率轉換器的封裝結構沿B--B’的示例剖面圖。 在該示例中，第一功率電晶體的源極和第二功率電晶體的汲極通過第二連接結構42相連接。第二連接結構42被配置為銅夾結構42。第二晶片2上表面的汲極電極通過焊接層25與銅夾結構42相連接。第一晶片1上表面的源極電極通過焊接層15也與銅夾結構42相連接。因此，通過銅夾結構42將第一功率電晶體的源極和第二功率電晶體的汲極連接在一起，並通過銅夾結構42引出至相應的引腳32。 第一晶片1的第一功率電極11和引腳32的之間的連接通過第一連接結構41來實現。第一連接結構41可以設置為金屬凸塊，一端與引腳32相連接，另一端與第一功率電極11對應的焊墊或者金屬層相連接，從而將第一功率電極11通過引腳32向外引出。 位於第二晶片2的下表面的源極電極可以通過導電層24引出。一種實現方式為，導電層24可以直接與圖案化的基底31相連接，進而引出至相應的引腳32。可以理解，導電層可以設置為包括焊接層和金屬層，或者僅包括可黏接導電層等不同形式的導電結構。另一種實現方式為，導電層24可以設置為重佈線層結構，以將源極電極引出至相應的引腳32。重佈線層結構和基底31之間可以設置黏接層，以將第二晶片2安裝固定於基底31上。第一晶片1的下表面可以通過設置絕緣的黏接層14安裝固定於基底31上。 可以推知的，第二連接結構42也可以被配置為重佈線金屬結構42。 第二晶片2上表面的汲極電極通過金屬凸塊層25與重佈線金屬結構42相連接。 第一晶片1上表面的源極電極通過金屬凸塊層15也與重佈線金屬結構42相連接。因此，通過重佈線金屬結構42將第一功率電晶體的源極和第二功率電晶體的汲極連接在一起，並通過重佈線金屬結構42引出至相應的引腳32。 大面積的成片狀的銅夾結構或者重佈線金屬結構，可以承受較大的電流，並且具有較小的導通電阻，降低損耗。 應當理解，圖2B所示的封裝結構僅示出了源極電極和引腳之間實現電連接關係的示意圖，焊接層15和焊接層25的上下表面，導電層24的上下表面均可以佈設所需要的其他層。 以上依據本發明第二實施例的封裝結構，還包括塑封體，用以將引線框架，第一晶片，第二晶片，連接裝置進行塑封，並將引線框架的引腳裸露所述塑封體外，以通過引腳實現外部連接。 以上所描述的實施例中，第二晶片的閘極和汲極位於同一表面。可以理解，第二晶片的閘也可以位於與汲極不同的表面，而與源極處於相同的表面。此時，可以通過將閘極引出至相應的引腳，以及將對應的控制和驅動電極引出至該引腳，從而封裝外部實現兩者之間的電性連接。 第二晶片的源極電極和相應的引腳之間的連接，可以將背面的源極電極直接貼裝於大面積的圖案化的引腳上，作為引腳連接結構，這將有利於晶片的散熱。在塑封過程中，也可以將引腳連接結構的背面裸露，以進一步的提高散熱能力。 另外，在上述實施例中，第二功率級電晶體的控制和驅動電路集成於第一晶片中。可以理解，第二功率級電晶體的控制和驅動電路可以獨立為一單獨的晶片。在封裝結構內部或者通過封裝結構的引腳，將兩者對應的電極進行電性連接。 如圖1B和2A所示的以上所描述的實施例中，第一晶片的第一功率電極和第二功率電極的區域已經進行了劃分，並分別佔據位於第一晶片上表面的上方的不同的大片的面積區域，以方便後續不同電極之間的相互連接以及電極和引線框架的引腳之間的連接。 以下將根據具體實施例對實現上述第一晶片1的第一功率電極和第二功率電極的區域設置的具體實現方式進行說明。 參考圖3A，所示為依據本發明一實施例的第一晶片的功率電極引出結構示意圖。仍以MOSFET電晶體為例，第一功率電極為汲極，第二功率電極為源極。 在該實施例中，第一晶片包括多個晶胞單元；每一晶胞單元以連續的汲-閘-源的形式連續設置並彼此並聯。方便說明，圖中僅示出汲極和源極的排列。汲極和源極交叉並行排列。 圖案化的第一連接結構33配置為將所有的汲極連接在一起。具體的，第一連接結構33包括多個第一指狀結構332和第一電氣引線331。第一功率電極接合區域311是第一指狀結構332和第一晶片的汲極電極相接合的區域，據此使得第一連接結構33具有與汲極相同的電位。 類似的，圖案化的第二連接結構34配置為將所有的源極連接在一起。具體的，第二連接結構33包括多個第二指狀結構342和第二電氣引線341。第二功率電極接合區域321是第二指狀結構342和第一晶片的源極電極相接合的區域，據此使得第二連接結構34具有與源極相同的電位。 通過圖案化的第一連接結構33和第二連接結構34，將汲極和源極分別排布於不同的區域。 一種實現為，圖案化的第一連接結構33和第二連接結構34被配置為重佈線金屬結構。 參考圖3B，所示為圖3A所示的第一晶片的功率電極引出結構沿C--C’的剖面圖。 第一晶片1的源極焊墊通過金屬凸塊45連接至第二指狀結構342，兩者的接合區域即為第二功率電極接合區域321。也可以為金屬凸塊45之外的連接結構，比如，焊接層或者焊球等其他的連接結構。 通過圖3A和圖3B所示的功率電極引出結構，源極電位和汲極電位被排列於相對兩側區域。通過第二電氣引線341引出的源極電位位於靠近第二晶片的區域。第一晶片的源極和第二晶片的汲極的連接，可以通過上述所述大面積的片狀連接結構，例如銅夾，將第二連接結構34的第二電氣引線341和第二晶片的汲極相連接。第一晶片的汲極和引腳的連接，也可以通過大面積的片狀連接結構，例如銅夾，將第一電氣引線331和引腳相連接。 第一晶片的功率電極引出結構，也可以通過分層式的具有不同高度的第一連接結構和第二連接結構來實現。例如，連接至汲極焊墊的第一連接結構具有相對較高的高度。連接至源極焊墊的圖案化的第二連接結構的高度相對較低，也可以實現將源極和汲極排列於相對的兩側區域。 參考圖4A，所示為依據本發明另一實施例的第一晶片的功率電極引出結構示意圖，以及圖4B所示的圖4A所示的依據本發明實施例的第一晶片的功率電極引出結構沿軸線D--D’的剖面圖。 仍以MOSFET電晶體為例，第一功率電極為汲極，第二功率電極為源極。 所述圖案化的重佈線金屬結構包括第一金屬層，焊接結構和第二金屬層；所述第一金屬層的第一表面與相同電位的電極引出相連接，所述焊接結構與所述第一金屬層的第二表面相連接，並將所述電極電位重新佈設於第一晶片的相應區域；所述第二金屬層的第一表面與所述焊接結構相連接，並通過第二表面與外部連接。 具體的，圖案化的重佈線金屬結構包括第一金屬層，焊接結構和第二金屬層。 按照第一晶片1上的焊錫球的矩陣排列方式，圖案化的重佈線金屬結構(汲極重分佈單元)通過第一金屬層402(汲極)的第一表面與汲極焊錫球401相連接，並通過第二表面上的焊接結構403(例如焊錫球結構)與位於上部區域的第二金屬層404相連接，將汲極電極性引至第一晶片的上半側區域。類似的，重佈線金屬結構(源極重分佈單元)通過第一金屬層406(源極)的第一表面與源極焊錫球405相連接，並通過第二表面上的焊接結構407(例如焊錫球結構)與位於下部區域的第二金屬層408相連接，將源極電極性引至第一晶片的下半區域，從而將汲極電極性和源極電極性分割為兩個獨立並且相互不重疊的區域。 第二金屬層的面積和厚度可以設置為較大的數值，在實現電氣連接的同時，也減小了電流傳導路徑的電阻，降低了功率損耗。 除了上述已示例說明的晶圓外的連接結構，例如第一連接結構和第二連接結構來實現汲極電位和源極電位的重新排列，也可以在晶圓層面以將汲極電位和源極電位進行了重佈設，例如通過晶圓的金屬層來實現。 因此，依據本發明的不同電極電位之間的連接結構，以及電極電位和引腳之間的連接結構是指可以將不同電位連接在一起的連接構件，可以包括一個或者多個不同的部分，各部分之間可以是一體，也可以是分立的；可以是相同或者不相同的材料；可以包括晶圓外的部分以及晶圓內的部分。 應當說明的是，在本文中，諸如第一和第二等之類的關係術語僅僅用來將一個實體或者操作與另一個實體或操作區分開來，而不一定要求或者暗示這些實體或操作之間存在任何這種實際的關係或者順序。而且，術語“包括”、“包含”或者其任何其他變體意在涵蓋非排他性的包含，從而使得包括一系列要素的過程、方法、物品或者設備不僅包括那些要素，而且還包括沒有明確列出的其他要素，或者是還包括為這種過程、方法、物品或者設備所固有的要素。在沒有更多限制的情況下，由語句“包括一個……”限定的要素，並不排除在包括所述要素的過程、方法、物品或者設備中還存在另外的相同要素。 依照本發明實施例如上文所述，這些實施例並沒有詳盡敘述所有的細節，也不限制該發明僅為所述的具體實施例。顯然，根據以上描述，可作很多的修改和變化。本說明書選取並具體描述這些實施例，是為了更好地解釋本發明的原理和實際應用，從而使所屬技術領域技術人員能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍及其全部範圍和等效物的限制。
1:第一晶片 11:第一功率電極 12:第二功率電極 13:控制和驅動電極 14:黏接層 15:焊接層/金屬凸塊 2:第二晶片 21:第一功率電極 23:控制電極 24:導電層 25:焊接層/金屬凸塊層 31:基底 311:第一功率電極接合區域 32:引腳 321:第二功率電極接合區域 331:第一電氣引線 332:第一指狀結構 341:第二電氣引線 342:第二指狀結構 41:第一連接結構 42:第二連接結構 45:金屬凸塊 401:焊錫球 402:第一金屬層 403:焊接結構 404:第二金屬層 405:焊錫球 406:第一金屬層 407:焊接結構 408:第二金屬層 5:控制和驅動電路
通過以下參照附圖對本發明實施例的描述，本發明的上述以及其他目的、特徵和優點將更為清楚，在附圖中： [圖1A]所示的降壓型功率轉換器的原理圖； [圖1B]所示為依據本發明第一實施例的應用於功率轉換器的封裝結構； [圖1C]所示為圖1B所示的依據本發明應用於功率轉換器的封裝結構沿A--A’的第一示例剖面圖； [圖1D]所示為圖1B所示的依據本發明應用於功率轉換器的封裝結構沿A--A’的第二示例剖面圖； [圖2A]所示為依據本發明第二實施例的應用於功率轉換器的封裝結構示意圖； [圖2B]所示為圖2A所示的依據本發明應用於功率轉換器的封裝結構沿B--B’的示例剖面圖； [圖3A]所示為依據本發明一實施例的第一晶片的功率電極引出結構示意圖； [圖3B]所示為圖3A所示的第一晶片的功率電極引出結構沿C--C’的剖面圖； [圖4A]所示為依據本發明另一實施例的第一晶片的功率電極引出結構示意圖； [圖4B]所示的圖4A所示的依據本發明實施例的第一晶片的功率電極引出結構沿軸線D--D’的剖面圖。
1:第一晶片
2:第二晶片
11:第一功率電極
12:第二功率電極
13:控制和驅動電極
21:第一功率電極
23:控制電極
31:基底
32:引腳
41:第一連接結構
42:第二連接結構

Claims (26)

  1. 一種應用於功率轉換器的封裝結構，包括：第一晶片，至少包括第一功率電晶體和第一控制和驅動電路，其中，該第一功率電晶體的控制電極和第一功率電極和第二功率電極位於該第一晶片的同一表面；第二晶片，至少包括第二功率電晶體；連接裝置，用以在該封裝結構內部，通過該連接裝置將該第一功率電晶體和第二功率電晶體依次串聯耦接在該封裝結構的引線框架的高電平引腳和低電平引腳之間；該第一功率電晶體和該第二功率電晶體的公共連接點通過低互連電阻的金屬連接結構耦接至該引線框架的輸出引腳。
  2. 根據請求項1所述的封裝結構，其中，該第二功率電晶體被配置為具有垂直電流流向的功率器件。
  3. 根據請求項1所述的封裝結構，其中，該第一功率電晶體與該高電平引腳之間的連接，該第二功率電晶體與該低電平引腳之間的連接，通過低互連電阻的金屬連接結構或者通過堆疊式的直接連接方式來實現。
  4. 根據請求項3所述的封裝結構，其中，低互連電阻的金屬連接結構被配置為片狀的金屬夾結構或者重佈線金屬結構。
  5. 根據請求項1所述的封裝結構，其中，該第二功率電晶體的第一功率電極和該第二功率電極位於該 第二晶片的不同表面。
  6. 根據請求項5所述的封裝結構，其中，該第一晶片和第二晶片並行排列。
  7. 根據請求項6所述的封裝結構，其中，該連接裝置包括金屬夾結構，以通過焊接層與該第一功率電晶體的第二功率電極和該第二功率電晶體的第一功率電極電耦接，並連接至引線框架的相應引腳。
  8. 根據請求項6所述的封裝結構，其中，該連接裝置包括金屬重佈線結構，該第一功率電晶體的第二電極和該第二功率電晶體的第一電極，通過焊接製程，與該金屬重佈線層連接，並經由該金屬重佈線結構連接至引線框架的相應引腳。
  9. 根據請求項1所述的封裝結構，其中，該第一功率電晶體的第一功率電極和第二功率電極的電位區域位於該第一晶片的該同一表面上的相對兩側區域，該第一功率電晶體的第二功率電極的電位區域位於靠近第二晶片的一側。
  10. 根據請求項9所述的封裝結構，其中，該連接裝置包括低互連電阻的金屬連接結構，以在該封裝結構內部將該第二功率電晶體的第一功率電極和該第一功率電晶體的第二功率電極進行連接，以容納大電流和降低互連電阻。
  11. 根據請求項10所述的封裝結構，其中，該低互連電阻的金屬連接結構包括與該第一功率電晶體的 第二功率電極相連的第一部分和與該第二功率電晶體的第一功率電極相連的第二部分，該第一部分和第二部分相接觸。
  12. 根據請求項11所述的封裝結構，其中，該第一部分被配置為圖案化的重佈線金屬結構，以將該第一功率電晶體的第二功率電極引出。
  13. 根據請求項12所述的封裝結構，其中，該第二部分被配置為金屬夾結構。
  14. 根據請求項12所述的封裝結構，其中，該圖案化的重佈線金屬結構包括電氣引線和指狀結構；該指狀結構與電極引出結構相連接，該電氣引線與該指狀結構相連接，以將相應的電位引出。
  15. 根據請求項12所述的封裝結構，其中，該圖案化的重佈線金屬結構包括第一金屬層，焊接結構和第二金屬層；該第一金屬層的第一表面與相同電位的電極引出相連接，該焊接結構與該第一金屬層的第二表面相連接，並將該電極電位重新佈設於第一晶片的相應區域；該第二金屬層的第一表面與該焊接結構相連接，並通過第二表面與外部連接。
  16. 根據請求項5所述的封裝結構，其中，該第一晶片和第二晶片堆疊排列。
  17. 根據請求項16所述的封裝結構，其中，該第二晶片正裝，該第一晶片倒裝，部分堆疊於該第二晶片上方。
  18. 根據請求項17所述的封裝結構，其中，該第一功率電晶體的第二功率電極區域和該第二功率電晶體的第一功率電極區域沿該封裝結構的垂直方向重疊。
  19. 根據請求項18所述的封裝結構，其中，該連接裝置包括金屬連接結構，其第一表面通過可焊接結構與該第一功率電晶體的第二功率電極電連接，第二表面通過可焊接結構與該第二功率電晶體的第一功率電極電連接，並通過該金屬連接結構連接至引線框架的相應引腳。
  20. 根據請求項18所述的封裝結構，其中，該第一控制和驅動電路中的驅動電極通過金屬連接結構連接至該第二功率電晶體的控制電極，該控制電極與該第一功率電極位於同一表面。
  21. 根據請求項20所述的封裝結構，其中，該金屬連接結構配置為金屬凸塊或者金屬重佈線結構。
  22. 根據請求項18所述的封裝結構，其中，該第一功率電晶體的第一功率電極通過金屬凸塊或者金屬重佈線結構連接至引線框架的相應引腳。
  23. 根據請求項1所述的封裝結構，其中，該第二功率電晶體的第一功率電極和該第二功率電極位於該第二晶片的同一表面。
  24. 根據請求項23所述的封裝結構，其中，該第一功率電晶體與該高電平引腳之間的連接，該第二功率電晶體與該低電平引腳之間的連接，以及該第二功率電晶體的第一功率電極和該第二功率電極之間的連接通過低 互連電阻的金屬連接結構或者通過堆疊式的直接連接方式來實現。
  25. 根據請求項1所述的封裝結構，其中，該第二功率電晶體的控制電極與第一功率電極位於不同表面，該第一控制和驅動電路中的驅動電極和該第一功率電極通過金屬連接結構連接至該引線框架的同一引腳。
  26. 根據請求項1所述的封裝結構，其中，還包括塑封體，以包覆該第一晶片，第二晶片，該連接裝置和引線框架，並將該引腳部分裸露於該塑封體外。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160260697A1 (en) * 2011-01-14 2016-09-08 Infineon Technologies Americas Corp. Stacked Half-Bridge Package
US20190035745A1 (en) * 2016-12-28 2019-01-31 Renesas Electronics Corporation Semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102083254B (zh) 2009-11-30 2013-09-18 成都芯源系统有限公司 适用于三端可控硅调光器的wled驱动电路及驱动方法
CN103646942B (zh) * 2010-02-25 2016-01-13 万国半导体有限公司 一种应用于功率切换器电路的半导体封装结构
CN101835314B (zh) 2010-05-19 2013-12-04 成都芯源系统有限公司 一种具有调光功能的led驱动电路及灯具
JP5787784B2 (ja) * 2012-02-15 2015-09-30 ルネサスエレクトロニクス株式会社 半導体装置
DE102016101433A1 (de) * 2016-01-27 2017-07-27 Infineon Technologies Ag Multi-Chip-Halbleiterleistungsgehäuse
CN107046010B (zh) * 2016-02-05 2019-08-02 万国半导体股份有限公司 功率器件及制备方法
CN106341923B (zh) 2016-04-29 2018-03-23 矽力杰半导体技术(杭州)有限公司 控制电路、控制方法和应用其的线性led驱动电路
CN106912144B (zh) * 2017-04-06 2018-01-23 矽力杰半导体技术(杭州)有限公司 具有可控硅调光器的led驱动电路、电路模块及控制方法
CN106793352B (zh) 2017-04-06 2018-11-13 矽力杰半导体技术(杭州)有限公司 具有可控硅调光器的led驱动电路、电路模块及控制方法
CN106888524B (zh) 2017-04-21 2018-01-16 矽力杰半导体技术(杭州)有限公司 具有可控硅调光器的led驱动电路、电路模块及控制方法
CN108463030A (zh) * 2018-04-18 2018-08-28 矽力杰半导体技术(杭州)有限公司 具有可控硅调光器的led驱动电路、电路模块及控制方法
CN211828761U (zh) * 2020-05-03 2020-10-30 矽力杰半导体技术(杭州)有限公司 应用于功率转换器的封装结构

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160260697A1 (en) * 2011-01-14 2016-09-08 Infineon Technologies Americas Corp. Stacked Half-Bridge Package
US20190035745A1 (en) * 2016-12-28 2019-01-31 Renesas Electronics Corporation Semiconductor device

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