TWI776166B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI776166B
TWI776166B TW109119115A TW109119115A TWI776166B TW I776166 B TWI776166 B TW I776166B TW 109119115 A TW109119115 A TW 109119115A TW 109119115 A TW109119115 A TW 109119115A TW I776166 B TWI776166 B TW I776166B
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Taiwan
Prior art keywords
insulating layer
redistribution
lower electrode
pattern
electrode pad
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TW109119115A
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English (en)
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TW202105627A (zh
Inventor
金鍾潤
朴正鎬
李錫賢
張延鎬
張在權
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南韓商三星電子股份有限公司
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Publication of TW202105627A publication Critical patent/TW202105627A/zh
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Publication of TWI776166B publication Critical patent/TWI776166B/zh

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Abstract

一種半導體封裝包括：重佈線結構，包括重佈線絕緣層及重佈線圖案；半導體晶片，設置於重佈線絕緣層的第一表面上且電性連接至重佈線圖案；以及下電極接墊，設置於重佈線絕緣層的與第一表面相對的第二表面上，下電極接墊包括嵌置於重佈線絕緣層中的第一部分及自重佈線絕緣層的第二表面突出的第二部分，其中下電極接墊的第一部分的厚度大於下電極接墊的第二部分的厚度。

Description

半導體封裝
[相關申請案的交叉參考]
本申請案主張於2019年6月28日在韓國智慧財產局提出申請的韓國專利申請案第10-2019-0078341號的優先權權益，所述韓國專利申請案的揭露內容全文併入本案供參考。
本發明概念是有關於一種半導體封裝及一種製造所述半導體封裝的方法，且更具體而言，是有關於一種扇出型半導體封裝及一種製造所述扇出型半導體封裝的方法。舉例而言，本揭露是有關於扇出型晶圓級封裝(fan-out wafer level packaging，FOWLP)的一種方法及一種裝置。
近來，隨著電子產品市場中對可攜式裝置的需求的快速增長，安裝於該些電子產品中的電子組件一直被要求微型化且輕量化。為了使電子組件微型化且輕量化，使安裝於電子組件上的半導體封裝在能夠處理大量資料的同時具有較小的體積是有益的。具體而言，在具有增加數目的輸入/輸出(input/output，I/O)端子的高度積體化的半導體晶片中，輸入端子與輸出端子之間的間距可減小，且因此，輸入端子與輸出端子之間可能發生干擾。 為了消除輸入端子與輸出端子之間的此種干擾，具有增加的輸入端子與輸出端子之間的間距的扇出型半導體封裝是有益的。
本發明概念提供一種具有改善的可靠性的半導體封裝以及一種製造所述半導體封裝的方法。
根據本發明概念的態樣，提供一種半導體封裝，所述半導體封裝包括：重佈線結構，包括重佈線絕緣層及重佈線圖案；半導體晶片，設置於所述重佈線絕緣層的第一表面上且電性連接至所述重佈線圖案；以及下電極接墊，設置於所述重佈線絕緣層的與所述第一表面相對的第二表面上，所述下電極接墊包括嵌置於重佈線絕緣層中的第一部分及自所述重佈線絕緣層的所述第二表面突出的第二部分，其中所述下電極接墊的所述第一部分的厚度大於所述下電極接墊的所述第二部分的厚度。
根據本發明概念的態樣，提供一種半導體封裝，所述半導體封裝包括：重佈線絕緣層，包括彼此相對的第一表面與第二表面；第一導電線圖案，位於所述重佈線絕緣層中；第二導電線圖案，位於所述重佈線絕緣層的所述第一表面上；下電極接墊，包括嵌置於所述重佈線絕緣層中的第一部分及自所述重佈線絕緣層的所述第二表面突出的第二部分；第一導電通孔圖案，在所述第一導電線圖案與所述下電極接墊之間延伸且接觸所述下電極接墊；第二導電通孔圖案，在所述第二導電線圖案與所述第一導電線圖案之間延伸；以及半導體晶片，設置於所述重佈線絕緣層上 且電性連接至所述第二導電線圖案。
根據本發明概念的態樣，提供一種半導體封裝，所述半導體封裝包括重佈線結構、半導體晶片、晶片連接端子、底部填充材料層、模製層、下電極接墊以及外部連接端子，所述重佈線結構包括：多個絕緣層；多個導電線圖案，設置於所述多個絕緣層中的每一者的上表面上；以及多個導電通孔圖案，穿透所述多個絕緣層中的至少一者且連接至所述多個導電線圖案中的至少一者，所述半導體晶片位於所述重佈線結構的上表面上，所述晶片連接端子插置於所述半導體晶片與所述多個導電線圖案的最上層的導電線圖案之間，所述底部填充材料層在所述半導體晶片與所述重佈線結構之間環繞所述晶片連接端子，所述模製層覆蓋所述半導體晶片的至少一部分，所述下電極接墊位於所述重佈線結構的底表面上，所述外部連接端子位於所述下電極接墊上，其中所述下電極接墊包括嵌置於所述多個絕緣層中的最下絕緣層中的第一部分及自所述最下絕緣層突出的第二部分，且所述下電極接墊的所述第二部分的厚度小於所述下電極接墊的所述第一部分的厚度。
根據本發明概念的態樣，提供一種製造半導體封裝的方法，所述方法包括在載體基板上形成覆蓋絕緣層、在所述覆蓋絕緣層上形成下電極接墊、形成包括覆蓋所述下電極接墊的重佈線絕緣層及電性連接至所述下電極接墊的重佈線圖案的重佈線結構、在所述重佈線結構上放置半導體晶片、移除所述載體基板、 以及移除所述覆蓋絕緣層且移除所述重佈線絕緣層的一部分以暴露出所述下電極接墊的側壁的一部分。
10、10a、10b:半導體封裝
11L:下封裝
11U:上封裝
100:重佈線結構
100L:第一重佈線結構
100U:第二重佈線結構
110、110L:重佈線絕緣層
110U:第二重佈線絕緣層
111:第一絕緣層/絕緣層
111a:第一絕緣層
113:第二絕緣層/絕緣層
115:第三絕緣層/絕緣層
118:第一表面
119:第二表面
120:第一重佈線圖案/重佈線圖案
120L、130L:重佈線圖案
120U、140U:第二重佈線圖案
121:第一導電線圖案/導電線圖案
121L、121U、131L、141L、141U:導電線圖案
123:第一導電通孔圖案/導電通孔圖案
123L、123U、133L、143L、143U:導電通孔圖案
125:第一晶種層/晶種層
125a:第一初步晶種層
130:第二重佈線圖案/重佈線圖案
131:第二導電線圖案/導電線圖案
133:第二導電通孔圖案/導電通孔圖案
135:第二晶種層/晶種層
140、140L:第三重佈線圖案/重佈線圖案
141:第三導電線圖案/導電線圖案
143:第三導電通孔圖案/導電通孔圖案
145:第三晶種層/晶種層
150:下電極接墊/電極接墊
150L:第一下電極接墊
150U:第二下電極接墊
151:第一部分
151t、153t:厚度
153:第二部分
160:第一導電柱
200、200a:半導體晶片
200L、201:第一半導體晶片
200U、203:第二半導體晶片
210、211、213:半導體基板
220、221、223:晶片接墊
230:晶片連接端子
230L:第一晶片連接端子
230U:第二晶片連接端子
240:底部填充材料層
240L:第一底部填充材料層
240U:第二底部填充材料層
300:模製層
300L:第一模製層
300U:第二模製層
310:載體基板
311:釋放膜
320:覆蓋絕緣層
400:外部連接端子
410:封裝間連接端子
II:區域
MP:罩幕圖案
OP:開口
SL:切割道
S110:第一步驟/製程步驟
S120:第二步驟/製程步驟
S130:第三步驟/製程步驟
S140:第四步驟/製程步驟
S150:第五步驟/製程步驟
S160:第六步驟/製程步驟
S170:第七步驟/製程步驟
S180:第八步驟/製程步驟
VO1:第一通孔開口
VO2:第二通孔開口
VO3:第三通孔開口
結合附圖，根據以下詳細說明，將更清楚地理解本發明概念的實施例，在附圖中：圖1是示出根據本發明概念的示例性實施例的半導體封裝的剖視圖。
圖2是根據本發明概念的示例性實施例的圖1中的區域「II」的放大剖視圖。
圖3是示出根據本發明概念的示例性實施例的製造半導體封裝的方法的流程圖。
圖4A至圖4L是根據本發明概念的示例性實施例的依序示出製造半導體封裝的方法的剖視圖。
圖5A至圖5E是根據本發明概念的示例性實施例依序示出形成第一重佈線圖案的方法的剖視圖。
圖6是示出根據本發明概念的示例性實施例的半導體封裝的剖視圖。
圖7是示出根據本發明概念的示例性實施例的半導體封裝的剖視圖。
在下文中，將參照附圖詳細闡述本發明概念的示例性實施例。在圖式中，相同的參考編號用於相同的元件且將省略其冗 餘說明。
圖1是示出根據本發明概念的示例性實施例的半導體封裝10的剖視圖。圖2是根據本發明概念的示例性實施例的圖1的區域「II」的放大剖視圖。
參照圖1及圖2，半導體封裝10可包括重佈線結構100、設置於重佈線結構100的上側上的半導體晶片200以及設置於重佈線結構100的下側上的下電極接墊150。
重佈線結構100可包括重佈線絕緣層110及多個重佈線圖案120、130及140。
重佈線絕緣層110可包括多個絕緣層111、113及115。所述多個絕緣層111、113及115中的每一者可包括例如包含有機化合物的材料膜。在示例性實施例中，所述多個絕緣層111、113及115中的每一者可包括包含有機聚合物材料的材料膜。在示例性實施例中，所述多個絕緣層111、113及115中的每一者可包含絕緣材料，其中絕緣材料可包含能夠用於微影製程的光可成像介電(photo-imageable dielectric，PID)材料。舉例而言，所述多個絕緣層111、113及115中的每一者可包含感光性聚醯亞胺(photosensitive polyimide，PSPI)。在示例性實施例中，所述多個絕緣層111、113及115中的每一者可包含氧化物或氮化物。
所述多個重佈線圖案120、130及140可包括多個導電線圖案121、131及141，以及多個導電通孔圖案123、133及143。所述多個導電線圖案121、131及141可設置於所述多個絕緣層 111、113及115中的每一者的上表面及下表面中的至少一個表面上。所述多個導電通孔圖案123、133及143可穿透所述多個絕緣層111、113及115中的至少一者。所述多個導電通孔圖案123、133及143可連接至所述多個導電線圖案121、131及141中的至少一者及/或可連接至下電極接墊150。
多個晶種層125、135及145可分別插置於所述多個絕緣層111、113及115與所述多個導電線圖案121、131及141之間，且可分別插置於所述多個絕緣層111、113及115與所述多個導電通孔圖案123、133及143之間。在示例性實施例中，所述多個晶種層125、135及145可藉由執行物理氣相沈積來形成，且所述多個導電線圖案121、131及141以及所述多個導電通孔圖案123、133及143可利用無電鍍覆製程(例如化學鍍覆製程或自動催化鍍覆製程(auto-catalytic plating process))來形成。
舉例而言，所述多個晶種層125、135及145可選自包括銅(Cu)、鈦(Ti)、鈦鎢(TiW)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、鉻(Cr)、鋁(Al)等的群組。然而，所述多個晶種層125、135及145並非僅限於該些材料。在示例性實施例中，所述多個晶種層125、135及145可包含使銅堆疊於鈦上的Cu/Ti，或者使銅堆疊於鈦鎢上的Cu/TiW。
所述多個導電線圖案121、131及141以及所述多個導電通孔圖案123、133及143可包含金屬，例如銅(Cu)、鋁(Al)、鎢(W)、鈦(Ti)、及鉭(Ta)、銦(In)、鉬(Mo)、錳(Mn)、 鈷(Co)、錫(Sn)、鎳(Ni)、鎂(Mg)、錸(Re)、鈹(Be)、鎵(Ga)、或釕(Ru)、或其合金，但並非僅限於此。在示例性實施例中，當所述多個導電線圖案121、131及141以及所述多個導電通孔圖案123、133及143包含銅(Cu)時，所述多個晶種層125、135及145的至少一部分可充當擴散障壁層。舉例而言，擴散障壁層可防止/減少導電線圖案121、131及141及/或導電通孔圖案123、133及143的材料擴散至絕緣層111、113及115中。
所述多個導電線圖案121、131及141的一部分可與所述多個導電通孔圖案123、133及143的一部分一起形成，以形成單一體。舉例而言，所述多個導電線圖案121、131及141的所述部分可與所述多個導電通孔圖案123、133及143的和所述多個導電線圖案121、131及141的所述部分的下側接觸的部分形成單一體。作為另一種選擇，所述多個導電線圖案121、131及141的所述部分可與所述多個導電通孔圖案123、133及143的和所述多個導電線圖案121、131及141的所述部分的上側接觸的部分形成單一體。在一些實施例中，導電通孔圖案123、133及143中的每一者可與設置於上方的導電線圖案121、131及141中的對應一者整合，以形成如圖1中所示的連續體。在某些實施例中，與圖1不同，導電通孔圖案123、133及143中的每一者可與設置於下方的對應的導電線圖案121、131或141整合，以形成連續體。
應理解，當元件被稱為「連接」另一元件、「耦合至」另一元件或位於另一元件「上」時，它可直接連接另一元件/耦合至 另一元件/位於另一元件上，或者可存在中間元件。相反，當元件被稱為「直接連接」至另一元件或「直接耦合」至另一元件，或者被稱為「接觸」另一元件或與另一元件「接觸」時，不存在中間元件。
以下將更詳細地闡述重佈線結構100的配置。
重佈線絕緣層110可包括依序堆疊的第一絕緣層111、第二絕緣層113及第三絕緣層115。第一重佈線圖案120可包括第一導電線圖案121、第一導電通孔圖案123及第一晶種層125。第二重佈線圖案130可包括第二導電線圖案131、第二導電通孔圖案133及第二晶種層135。第三重佈線圖案140可包括第三導電線圖案141、第三導電通孔圖案143及第三晶種層145。
第一絕緣層111可包括暴露出下電極接墊150的一部分的第一通孔開口VO1。第一晶種層125可設置於第一絕緣層111的上表面的一部分、第一通孔開口VO1的側壁、以及下電極接墊150的上表面的經由第一通孔開口VO1暴露出的一部分上。第一晶種層125的一部分可插置於第一導電線圖案121與第一絕緣層111的上表面之間，第一晶種層125的另一部分可被形成為環繞第一導電通孔圖案123的側壁，且第一晶種層125的其他部分可插置於第一導電通孔圖案123與下電極接墊150之間。
除非上下文另外指明，否則將用語第一、第二、第三等用作標籤，以將一個元件、組件、區、層或部分與另一元件、組件、區、層或部分(可能相似或者可能不相似)區分開來。因此， 在說明書(或申請專利範圍)的一個部分中在以下論述的第一元件、組件、區、層或部分可被稱為說明書(或另一申請專利範圍)的另一部分中的第二元件、組件、區、層或部分。
第一導電線圖案121及第一導電通孔圖案123可設置於第一晶種層125上。第一導電線圖案121與第一導電通孔圖案123可經由鍍覆製程一起形成，且可彼此整合為單一體。第一導電線圖案121可設置於第一晶種層125的形成於第一絕緣層111的上表面上的一部分上，且第一導電線圖案121亦可設置於第一導電通孔圖案123上。第一導電通孔圖案123可覆蓋第一晶種層125的位於第一通孔開口VO1中的一部分且可填充第一通孔開口VO1。舉例而言，第一導電通孔圖案123的頂部可具有與第一絕緣層111的上表面相同的水平高度(例如，處於相同的垂直水平高度處)。舉例而言，第一導電通孔圖案123及第一晶種層125的一部分可自第一通孔開口VO1的底部至第一通孔開口VO1的頂部填充第一通孔開口VO1。第一導電通孔圖案123可穿透第一絕緣層111，以將第一導電線圖案121連接至下電極接墊150。舉例而言，第一導電通孔圖案123可將第一導電線圖案121電性連接至下電極接墊150。
本文中可用理想化的視圖(儘管為了清楚起見，可能會誇大相對大小)來示出實施例。應理解，端視製造技術及/或公差而定，實際實施方式可不同於該些示例性視圖。因此，對於在指明定向、佈局、位置、形狀、大小、數量或其他量測時使用如本 文中所使用的例如「相同」、「相等」等用語、以及例如「平行」、「均勻」、「平坦的」、「共面」、「圓柱形」、「正方形」等幾何說明的某些特徵的說明囊括基於精確同一性的可接受的變化，所述變化包括幾乎相同的佈局、位置、形狀、大小、數量或處於可接受的變化(例如，由於製造製程而可能發生的變化)內的其他量測。除非上下文或其他陳述另外指明，否則用語「實質上」在本文中可用來強調此含義。
在示例性實施例中，第一導電通孔圖案123可具有在自重佈線絕緣層110的第一表面118至重佈線絕緣層110的第二表面119的方向上逐漸減小的形狀。舉例而言，第一導電通孔圖案123的平行於第一絕緣層111的上表面的橫截面積可自第一絕緣層111的上表面至第一絕緣層111的下表面逐漸減小。舉例而言，如圖1及圖2中所示，第一導電通孔圖案123在剖視圖中的寬度可自第一導電通孔圖案123的頂部至第一導電通孔圖案123的底部逐漸減小。
在第一絕緣層111上可堆疊有第二絕緣層113，第二絕緣層113覆蓋第一導電線圖案121的一部分且具有暴露出第一導電線圖案121的其餘部分的第二通孔開口VO2。舉例而言，第一導電線圖案121的一部分可被第二絕緣層113覆蓋且第一導電線圖案121的一部分可經由形成於第二絕緣層113中的第二通孔開口VO2暴露出。
第二晶種層135可設置於第二絕緣層113的上表面的一 部分、第二通孔開口VO2的側壁以及第一導電線圖案121的上表面的經由第二通孔開口VO2暴露出的一部分上。第二晶種層135的一部分可插置於第二導電線圖案131與第二絕緣層113的上表面之間，第二晶種層135的另一部分可被形成為環繞第二導電通孔圖案133的側壁，且第二晶種層135的其他部分可插置於第二導電通孔圖案133與第一導電線圖案121之間。
第二導電通孔圖案133及第二導電線圖案131可設置於第二晶種層135上。第二導電通孔圖案133及第二導電線圖案131可經由鍍覆製程形成，且可彼此整合為單一體。第二導電線圖案131可設置於第二晶種層135的位於第二絕緣層113的上表面上的一部分上，且第二導電線圖案131亦可設置於第二導電通孔圖案133上。第二導電通孔圖案133可覆蓋第二晶種層135的位於第二通孔開口VO2中的一部分且可填充第二通孔開口VO2。舉例而言，第二導電通孔圖案133的頂部可具有與第二絕緣層113的上表面相同的水平高度(例如，處於相同的垂直水平高度處)。舉例而言，第二導電通孔圖案133及第二晶種層135的一部分可自第二通孔開口VO2的底部至第二通孔開口VO2的頂部填充第二通孔開口VO2。第二導電通孔圖案133可穿透第二絕緣層113，以將第二導電線圖案131連接至第一導電線圖案121。舉例而言，第二導電通孔圖案133可將第二導電線圖案131電性連接至第一導電線圖案121。
在示例性實施例中，第二導電通孔圖案133可具有在自 重佈線絕緣層110的第一表面118至重佈線絕緣層110的第二表面119的方向上逐漸減小的形狀。舉例而言，第二導電通孔圖案133的平行於第二絕緣層113的上表面的橫截面積可自第二絕緣層113的上表面至第二絕緣層113的下表面逐漸減小。舉例而言，如圖1及圖2中所示，第二導電通孔圖案133在剖視圖中的寬度可自第二導電通孔圖案133的頂部至第二導電通孔圖案133的底部逐漸減小。
在第二絕緣層113上可堆疊有第三絕緣層115，第三絕緣層115覆蓋第二導電線圖案131的一部分且具有暴露出第二導電線圖案131的其餘部分的第三通孔開口VO3。舉例而言，第二導電線圖案131的一部分可被第三絕緣層115覆蓋且第二導電線圖案131的一部分可經由形成於第三絕緣層115中的第三通孔開口VO3暴露出。
第三晶種層145可設置於第三絕緣層115的上表面的一部分、第三通孔開口VO3的側壁以及第二導電線圖案131的上表面的經由第三通孔開口VO3暴露出的一部分上。第三晶種層145的一部分可插置於第三導電線圖案141與第三絕緣層115的上表面之間，第三晶種層145的另一部分可被形成為環繞第三導電通孔圖案143的側壁，且第三晶種層145的其他部分可插置於第三導電通孔圖案143與第二導電線圖案131之間。
第三導電通孔圖案143及第三導電線圖案141可設置於第三晶種層145上。第三導電通孔圖案143及第三導電線圖案141 可經由鍍覆製程形成，且可彼此整合為單一體。第三導電線圖案141可設置於第三晶種層145的位於第三絕緣層115的上表面上的一部分上，且第三導電線圖案141亦可設置於第三導電通孔圖案143上。第三導電通孔圖案143可覆蓋第三晶種層145的位於第三通孔開口VO3中的一部分且可填充第三通孔開口VO3。舉例而言，第三導電通孔圖案143的頂部可具有與第三絕緣層115的上表面相同的水平高度(例如，處於相同的垂直水平高度處)。舉例而言，第三導電通孔圖案143及第三晶種層145的一部分可自第三通孔開口VO3的底部至第三通孔開口VO3的頂部填充第三通孔開口VO3。第三導電通孔圖案143可穿透第三絕緣層115，以將第三導電線圖案141連接至第二導電線圖案131。舉例而言，第三導電通孔圖案143可將第三導電線圖案141電性連接至第二導電線圖案131。
在示例性實施例中，第三導電通孔圖案143可具有在自重佈線絕緣層110的第一表面118至重佈線絕緣層110的第二表面119的方向上逐漸減小的形狀。舉例而言，第三導電通孔圖案143的平行於第三絕緣層115的上表面的橫截面積可自第三絕緣層115的上表面至第三絕緣層115的下表面逐漸減小。舉例而言，如圖1及圖2中所示，第三導電通孔圖案143在剖視圖中的寬度可自第三導電通孔圖案143的頂部至第三導電通孔圖案143的底部逐漸減小。
在示例性實施例中，第三導電線圖案141可設置於重佈 線絕緣層110的第一表面118上且可用作可附接有半導體晶片200的上電極接墊。
在圖1中，重佈線結構100被示出為包括三個絕緣層111、113及115、三個導電線圖案121、131及141以及三個導電通孔圖案123、133及143，但並非僅限於此。可根據重佈線結構100中的電路內連線的設計對絕緣層的數目、導電線圖案的數目及導電通孔圖案的數目進行各種修改。
半導體晶片200可附接於重佈線結構100上。舉例而言，半導體晶片200可以倒裝晶片方式安裝於重佈線結構100上。舉例而言，可將半導體晶片200倒置以將晶片接墊220向下帶至晶片連接端子230上及/或向下帶向第三導電線圖案141。
半導體晶片200可包括例如中央處理單元(central processing unit，CPU)晶片、圖形處理單元(graphic processing unit，GPU)晶片或應用處理器(application processor，AP)晶片。半導體晶片200可包括例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶片或靜態隨機存取記憶體(static random access memory，SRAM)晶片、快閃記憶體晶片(flash memory chip)、電性可抹除及可程式化唯讀記憶體(electrically erasable and programmable read-only memory，EPROM)晶片、相變隨機存取記憶體(phase-change random access memory，PRAM)晶片、磁性隨機存取記憶體(magnetic random access memory，MRAM)晶片或電阻式隨機存取記憶體(resistive random access memory， RRAM)晶片。
半導體晶片200可包括半導體基板210以及設置於半導體基板210的一個表面上的晶片接墊220。
半導體基板210可包含例如矽(Si)。作為另一種選擇，半導體基板210可包含例如鍺(Ge)等半導體元素、或例如碳化矽(SiC)、砷化鎵(GaAs)、砷化銦(InAs)及磷化銦(InP)等化合物半導體。半導體基板210可具有主動面及與主動面相對的非主動面。在示例性實施例中，半導體基板210的主動面可面對重佈線結構100。
半導體晶片200可包括位於半導體基板210的主動面上的多個不同種類的單個裝置。
在半導體晶片200的晶片接墊220與用作重佈線結構100的上電極接墊的第三導電線圖案141之間可設置有晶片連接端子230。晶片連接端子230可電性連接半導體晶片200的晶片接墊220與第三導電線圖案141。晶片連接端子230可包括例如柱結構、焊料凸塊、焊料球及焊料層中的至少一者。
經由晶片連接端子230、重佈線結構100的第一重佈線圖案120、第二重佈線圖案130及第三重佈線圖案140、下電極接墊150及外部連接端子400的路徑，半導體晶片200可自外部接收用於半導體晶片200的運作的控制訊號、電源訊號及接地訊號中的至少一者，且亦可自外部接收待儲存於半導體晶片200中的資料訊號，或者可向外部提供儲存於半導體晶片200中的資料訊號。
可在半導體晶片200與重佈線結構100之間填充環繞晶片連接端子230的底部填充材料層240。底部填充材料層240可包含例如藉由毛細底部填充方法形成的環氧樹脂。在示例性實施例中，底部填充材料層240可包含非導電膜(non-conductive film，NCF)，例如絕緣體。
下電極接墊150可設置於重佈線結構100的下側上。外部連接端子400可設置於下電極接墊150上。半導體封裝10可經由外部連接端子400電性連接至且安裝於電子產品/裝置的模組基板或系統板上。下電極接墊150可用作其中設置有外部連接端子400的凸塊下金屬(under bump metallurgy，UBM)。
舉例而言，下電極接墊150及本文中闡述的其他接墊可完全具有均勻的厚度。上面設置有外部連接端子400的下電極接墊150的底表面可包括平的表面。下電極接墊150的頂表面亦可具有平的表面，所述平的表面可平行於底表面。舉例而言，下電極接墊150可包含金屬，例如銅(Cu)、鋁(Al)、鎢(W)、鈦(Ti)、鉭(Ta)、銦(In)、鉬(Mo)、錳(Mn)、鈷(Co)、錫(Sn)、鎳(Ni)、鎂(Mg)、錸(Re)、鈹(Be)、鎵(Ga)、或釕(Ru)、或其合金，但並非僅限於此。
在示例性實施例中，下電極接墊150的一部分可嵌置於重佈線絕緣層110中，且下電極接墊150的另一部分可自重佈線絕緣層110突出。舉例而言，下電極接墊150的嵌置部分可為相對於重佈線絕緣層110的表面水平高度凹陷至重佈線絕緣層110 中的部分。舉例而言，重佈線絕緣層110可覆蓋下電極接墊150的側壁的一部分，但可不覆蓋下電極接墊150的側壁的另一部分。在某些實施例中，如圖1及圖2中所示，下電極接墊150的一部分可嵌置於重佈線絕緣層110中且下電極接墊150的另一部分可自重佈線絕緣層110突出。舉例而言，如圖1及圖2中所示，下電極接墊150的頂表面的水平高度可高於重佈線絕緣層110的第二表面119的水平高度。舉例而言，下電極接墊150的頂表面可接觸重佈線絕緣層110。
根據本發明概念的示例性實施例，下電極接墊150的另一部分可自重佈線絕緣層110的第二表面119突出，且因此，沿重佈線絕緣層110的第二表面119的應力可在下電極接墊150的側壁處減小。因此，可防止由於半導體封裝10上的應力而對下電極接墊150及其周圍的重佈線結構100造成損壞，且最終可改善半導體封裝10的可靠性。
舉例而言，下電極接墊150的嵌置於重佈線絕緣層110中(或被重佈線絕緣層110環繞)的部分可被界定成下電極接墊150的第一部分151，且下電極接墊150的自重佈線絕緣層110的第二表面119突出的另一部分可被界定成下電極接墊150的第二部分153。在此種情形中，下電極接墊150的第一部分151的側壁可被重佈線絕緣層110覆蓋，且下電極接墊150的第二部分153的側壁可不被重佈線絕緣層110覆蓋。下電極接墊150的第二部分153的側壁可暴露至外部。舉例而言，下電極接墊150的第二 部分153可暴露至重佈線絕緣層110的外部。舉例而言，當半導體封裝10安裝於另一裝置/結構上/連接至另一裝置/結構時，第二部分153可被另一結構(例如被外部連接端子400及/或另一結構)覆蓋。
在示例性實施例中，下電極接墊150的第一部分151的厚度151t可大於下電極接墊150的第二部分153的厚度153t。舉例而言，下電極接墊150的第一部分151的側壁的高度可大於下電極接墊150的第二部分153的側壁的高度。當下電極接墊150的自重佈線絕緣層110突出的第二部分153的厚度153t太小時，可降低下電極接墊150的側壁處的應力鬆弛效應。當下電極接墊150的自重佈線絕緣層110突出的第二部分153的厚度153t太大時，下電極接墊150的嵌置於重佈線絕緣層110中的第一部分151的厚度151t與下電極接墊150的總厚度相比可能太小，使得重佈線絕緣層110與下電極接墊150之間的黏合性可能降低。
在示例性實施例中，下電極接墊150的第二部分153的厚度153t可介於下電極接墊150的總厚度的約10%與約30%之間。舉例而言，當下電極接墊150的厚度為10微米時，下電極接墊150的自重佈線絕緣層110的第二表面119突出的第二部分153的厚度153t可介於約1微米與約3微米之間。舉例而言，當下電極接墊150的厚度為10微米時，下電極接墊150的嵌置於重佈線絕緣層110中的第一部分151的厚度151t可介於約7微米與約9微米之間。第一部分151的側壁的高度方向及第二部分153的側 壁的高度方向以及包括第一部分151及第二部分153的下電極接墊150的厚度方向可垂直於重佈線絕緣層110的第一表面118及/或第二表面119。
例如「約」或「近似」等用語可反映僅以相對小的方式，及/或以不顯著改變某些元件的運作、功能或結構的方式變化的數量、大小、定向或佈局。舉例而言，自「約0.1至約10」的範圍可囊括例如圍繞0.1的0%至5%偏差與圍繞10的0%至5%偏差的範圍，特別是若此種偏差保持與所列範圍相同的效果。
半導體封裝10可更包括覆蓋重佈線結構100上的半導體晶片200的至少一部分的模製層300。模製層300可包含例如環氧模製化合物(epoxy molding compound，EMC)。模製層300可覆蓋重佈線絕緣層110的第一表面118的一部分且可覆蓋半導體晶片200的側表面。在此種情形中，半導體晶片200的上表面可暴露至外部，例如，暴露至模製層300的外部或半導體封裝10的外部。在其他示例性實施例中，模製層300可進一步覆蓋半導體晶片200的上表面。
儘管圖式中未示出，但散熱構件可附接至半導體晶片200的上表面。散熱構件可包括例如散熱板(heat slug)或熱匯。在示例性實施例中，導熱介面材料(thermal conductive interface material，TIM)可設置於散熱構件與半導體晶片200的上表面之間。導熱介面材料可包括例如礦物油、油脂、間隙填充油灰、相變凝膠、相變材料接墊、顆粒填充環氧樹脂。
半導體晶片200的覆蓋區域(footprint)可小於重佈線結構100的覆蓋區域。舉例而言，在平面圖中，半導體晶片200的面積可小於重佈線結構100的面積。舉例而言，半導體晶片200的水平寬度可小於重佈線結構100的水平寬度。在示例性實施例中，所述多個導電線圖案121、131及141的一部分可延伸以在水平方向上自半導體晶片200的側表面進一步突出。舉例而言，第一導電線圖案121的一部分及第二導電線圖案131的一部分可延伸以在水平方向上自半導體晶片200的側表面進一步突出。舉例而言，在平面圖中，第一導電線圖案121的一部分及/或第二導電線圖案131的一部分可自半導體晶片200的側表面突出。在某些實施例中，例如在平面圖中，所述多個下電極接墊150中的至少一者可設置於例如與半導體晶片200的側表面間隔開(例如向外)的位置處。
圖3是示出根據本發明概念的示例性實施例的製造半導體封裝的方法的流程圖。
參照圖3，製造半導體封裝的方法可包括在載體基板上形成覆蓋絕緣層的第一步驟S110、在覆蓋絕緣層上形成下電極接墊的第二步驟S120、形成重佈線結構的第三步驟S130、在重佈線結構上附接半導體晶片且形成模製層的第四步驟S140、移除載體基板的第五步驟S150、移除覆蓋絕緣層以暴露出下電極接墊的第六步驟S160、移除重佈線絕緣層的一部分以暴露出下電極接墊的側壁的一部分的第七步驟S170、以及在下電極接墊上形成外部連接 端子的第八步驟S180。
製造半導體封裝的方法可包括以上製程步驟S110至S180。在其他實施例中，某些製程步驟可以不同於以上次序的次序執行。舉例而言，連續闡述的製程的兩個步驟可實質上同時執行或者以相反的次序執行。稍後將參照圖4A至圖4L更詳細地闡述第一步驟S110至第八步驟S180中的每一者的技術特徵。
圖4A至圖4L是根據本發明概念的示例性實施例的依序示出製造半導體封裝10的方法的剖視圖。
參照圖4A，可在附接有釋放膜311的載體基板310上形成覆蓋絕緣層320。覆蓋絕緣層320可包含與圖1的重佈線絕緣層110相同的絕緣材料，或者可包含不同於重佈線絕緣層110的絕緣材料。舉例而言，覆蓋絕緣層320可包括包含有機化合物的材料膜。在示例性實施例中，覆蓋絕緣層320可包含感光性聚醯亞胺。作為另一種選擇，例如，覆蓋絕緣層320可包含氧化物或氮化物。
載體基板310可支撐覆蓋絕緣層320，且可包括在烘烤製程及蝕刻製程中具有製程穩定性的任何材料。舉例而言，可在隨後的製程中藉由加熱及/或雷射移除載體基板310。當隨後藉由雷射燒蝕分離及移除載體基板310時，載體基板310可包括透明基板。當隨後藉由加熱分離及移除載體基板310時，載體基板310可為耐熱基板。在示例性實施例中，載體基板310可包括玻璃基板。作為另一種選擇，在其他示例性實施例中，載體基板310可包含耐熱有機聚合物材料，例如聚醯亞胺(polyimide，PI)、聚醚 醚酮(polyetheretherketone，PEEK)、聚醚碸(polyethersulfone，PES)、聚苯硫醚(polyphenylene sulfide，PPS)等，但並非僅限於此。
釋放膜311可包括例如能夠藉由因應於雷射輻照進行蒸發使得載體基板310為可分離的雷射反應層。釋放膜311可包括碳系材料層。舉例而言，釋放膜311可包括非晶碳層(amorphous carbon layer，ACL)。舉例而言，釋放膜311可包括包含具有基於總重量具有約85重量百分比至約99重量百分比的相對高的碳含量的烴化合物、或包含烴化合物衍生物的旋塗硬罩幕(spin-on hardmask，SOH)。
參照圖4B，可在覆蓋絕緣層320上形成下電極接墊150。為了形成下電極接墊150，可在覆蓋絕緣層320上形成導電材料膜，且然後可將導電材料膜圖案化。下電極接墊150可被形成為在覆蓋絕緣層320的上表面上具有完全均勻的厚度，且下電極接墊150的與覆蓋絕緣層320的上表面接觸的下表面可具有平的形狀。
在示例性實施例中，下電極接墊150可包括單一金屬材料。作為另一種選擇，下電極接墊150可具有多層結構，其中每層包含與其他層的金屬材料不同的金屬材料。
參照圖4C，在形成下電極接墊150之後，可形成包括第一通孔開口VO1的第一絕緣層111a，其中第一通孔開口VO1暴露出下電極接墊150的一部分。舉例而言，為了形成第一絕緣層 111a，可形成覆蓋下電極接墊150及覆蓋絕緣層320的絕緣材料膜，且然後可藉由經由曝光製程及顯影製程移除絕緣材料膜的一部分來形成第一通孔開口VO1。第一通孔開口VO1可暴露出下電極接墊150的一部分。
參照圖4D，可在圖4C的所得結構上形成第一晶種層125、第一導電線圖案121及第一導電通孔圖案123。舉例而言，第一晶種層125可被形成為覆蓋第一絕緣層111a的上表面、第一絕緣層111a的藉由第一通孔開口VO1(例如，第一通孔開口VO1的側壁)提供的內側壁、以及經由第一通孔開口VO1暴露出的下電極接墊150。第一絕緣層111a的內側壁可為第一絕緣層111a的藉由第一通孔開口VO1形成的表面，例如內側表面。第一導電線圖案121可沿第一絕緣層111a的上表面延伸，且第一導電通孔圖案123可例如連同第一晶種層125的一部分填充第一通孔開口VO1。第一晶種層125、第一導電線圖案121及第一導電通孔圖案123可構成第一重佈線圖案120。稍後將參照圖5A至圖5E更詳細地闡述形成第一重佈線圖案120的方法。
參照圖4E，在圖4D的所得結構上，經由與參照圖4C及圖4D闡述的製程實質上相同的製程或相似的製程，可依序形成包括第二通孔開口VO2的第二絕緣層113、第二重佈線圖案130、包括第三通孔開口VO3的第三絕緣層115及第三重佈線圖案140。第一絕緣層111、第二絕緣層113及第三絕緣層115以及第一重佈線圖案120、第二重佈線圖案130及第三重佈線圖案140 可構成重佈線結構100。
舉例而言，第二晶種層135可被形成為覆蓋第二絕緣層113的上表面、第二絕緣層113的由第二通孔開口VO2(例如，第二通孔開口VO2的側壁)提供的內側壁、以及第一導電線圖案121的經由第二通孔開口VO2暴露出的一部分。第二導電線圖案131可沿第二絕緣層113的上表面延伸，且第二導電通孔圖案133可例如連同第二晶種層135的一部分填充第二通孔開口VO2。第二晶種層135、第二導電線圖案131及第二導電通孔圖案133可構成第二重佈線圖案130。
第三晶種層145可被形成為覆蓋第三絕緣層115的上表面、第三絕緣層115的由第三通孔開口VO3(例如，第三通孔開口VO3的側壁)提供的內側壁、以及第二導電線圖案131的經由第三通孔開口VO3暴露出的一部分。第三導電線圖案141可沿第三絕緣層115的上表面延伸，且第三導電通孔圖案143可例如連同第三晶種層145的一部分填充第三通孔開口VO3。第三晶種層145、第三導電線圖案141及第三導電通孔圖案143可構成第三重佈線圖案140。
參照圖4F，可將半導體晶片200附接至重佈線結構100。可將半導體晶片200附接於重佈線結構100上，使得晶片接墊220面對重佈線結構100。半導體晶片200的晶片接墊220可經由晶片連接端子230電性連接至重佈線結構100的第三導電線圖案141。在此種情形中，第三導電線圖案141可用作其中安置有晶片連接 端子230的重佈線結構100的上電極接墊。
在將半導體晶片200附接至重佈線結構100之後，可形成底部填充材料層240以填充半導體晶片200與重佈線結構100之間的空間。底部填充材料層240可環繞晶片連接端子230。舉例而言，在將半導體晶片200附接至重佈線結構100之後，可藉由毛細底部填充方法形成底部填充材料層240。在某些示例性實施例中，可藉由在半導體晶片200的晶片接墊220上附接非導電膜，且然後在重佈線結構100上附接半導體晶片200來形成底部填充材料層240。
參照圖4G，在形成底部填充材料層240之後，可形成用於模製半導體晶片200的模製層300。模製層300可覆蓋半導體晶片200的側表面且暴露出半導體晶片200的上表面。模製層300可覆蓋重佈線絕緣層110的第一表面118的一部分。在其他示例性實施例中，模製層300可被形成為進一步覆蓋半導體晶片200的上表面。
參照圖4H以及圖4G，在形成模製層300之後，可移除載體基板310。舉例而言，在圖4G的所得結構中，附接有釋放膜311的載體基板310可與其他結構分離。舉例而言，為了分離載體基板310，可使用雷射輻照或加熱釋放膜311。由於載體基板310的分離，因此可暴露出覆蓋絕緣層320。
參照圖4I，在將圖4H的所得產物倒置之後，可移除覆蓋絕緣層320以暴露出下電極接墊150。舉例而言，可執行蝕刻製程 來移除覆蓋絕緣層320。由於覆蓋絕緣層320被移除，因此可暴露出下電極接墊150的下表面。
參照圖4J及圖4I，在移除覆蓋絕緣層320之後，可移除圖4I的第一絕緣層111a的一部分，以暴露出下電極接墊150的側壁的一部分。舉例而言，可執行乾式蝕刻製程來移除圖4I的第一絕緣層111a的一部分。由於移除圖4I的第一絕緣層111a的一部分，因此圖2的第一部分151可嵌置於第一絕緣層111中，且圖2的下電極接墊150的第二部分153可自第一絕緣層111突出。
在此種情形中，藉由控制蝕刻速度及蝕刻時間，可調整自第一絕緣層111突出的下電極接墊150的厚度。在示例性實施例中，由於對第一絕緣層111進行的蝕刻製程，因此下電極接墊150的自第一絕緣層111突出的第二部分153的厚度可小於下電極接墊150的嵌置於第一絕緣層111中的第一部分151的厚度。
在示例性實施例中，可在相同的蝕刻製程中移除圖4I的第一絕緣層111a的一部分及覆蓋絕緣層320。舉例而言，可藉由執行一個蝕刻製程來移除圖4I的第一絕緣層111a的一部分及覆蓋絕緣層320。在此種情形中，覆蓋絕緣層320可包含與圖4I的第一絕緣層111a相同的材料。
作為另一種選擇，在其他示例性實施例中，可經由分開的蝕刻製程移除圖4I的第一絕緣層111a的一部分及覆蓋絕緣層320。
參照圖4K，可將外部連接端子400附接於下電極接墊150 上。外部連接端子400可包括例如焊料球或凸塊。
參照圖4L，在形成外部連接端子400之後，可經由沿切割道SL切分圖4K的所得產物的單體化製程來完成如圖1中所示的經單體化的半導體封裝10。
通常，在以後晶片(chip last)方式製造半導體封裝的方法中，可依次執行重佈線結構形成、晶片附接、UBM形成及焊料球附接。然而，根據製造根據本發明概念的示例性實施例的半導體封裝的方法，由於可在形成重佈線結構100之前首先形成用作UBM的下電極接墊150，因此可簡化製程且可降低生產成本。
圖5A至圖5E是根據本發明概念的示例性實施例的依序示出形成第一重佈線圖案120的方法的剖視圖。
參照圖5A，可在覆蓋絕緣層320上形成絕緣材料層，且可對絕緣材料層執行蝕刻製程以形成包括第一通孔開口VO1的第一絕緣層111a。舉例而言，為了形成第一通孔開口VO1，可執行使用電漿、雷射鑽孔等的反應性離子蝕刻(reactive ion etching，RIE)製程。
在示例性實施例中，例如在如圖5A中所示的剖視圖中，第一通孔開口VO1可具有其中第一通孔開口VO1的寬度逐漸向下(或更靠近下電極接墊150)變窄的形狀。第一絕緣層111a的由第一通孔開口VO1(例如，第一通孔開口VO1的側壁)提供的內側壁可具有傾斜的側壁部分。舉例而言，可藉由在蝕刻製程中控制蝕刻氣體、氣體供應量及蝕刻速率等的組合來調整由第一絕緣 層111a的傾斜側壁部分與第一絕緣層111a的下表面形成的角度。舉例而言，例如在類似於圖5A中所述一者的剖視圖中，由第一絕緣層111a的傾斜側壁部分與第一絕緣層111a的下表面形成的角度可處於約75度與約85度之間。
參照圖5B，可形成第一初步晶種層125a以覆蓋第一絕緣層111a的上表面、第一絕緣層111a的由第一通孔開口VO1(例如，第一通孔開口VO1的側壁)提供的內側壁、以及下電極接墊150的經由第一通孔開口VO1暴露出的一部分。第一初步晶種層125a可在第一絕緣層111a的上表面、第一絕緣層111a的由第一通孔開口VO1提供的內側壁、以及下電極接墊150的經由第一通孔開口VO1暴露出的一部分上共形地延伸。
參照圖5C，可在第一初步晶種層125a上形成包括開口OP的罩幕圖案MP。罩幕圖案MP的開口OP可暴露出第一初步晶種層125a的一部分，且界定在後續製程中形成第一導電線圖案121及第一導電通孔圖案123的區。
參照圖5D，可在第一初步晶種層125a的由罩幕圖案MP的開口OP暴露出的一部分上形成第一導電線圖案121及第一導電通孔圖案123。第一導電線圖案121可在第一絕緣層111a的上表面之上延伸，且第一導電通孔圖案123可例如連同第一初步晶種層125a的一部分填充第一通孔開口VO1。舉例而言，可經由使用第一初步晶種層125a作為晶種的鍍覆製程一起形成第一導電線圖案121及第一導電通孔圖案123。第一導電線圖案121與第一導電 通孔圖案123可整體地形成為單一體。
在此種情形中，由於第一導電通孔圖案123可被形成為填充第一絕緣層111a中的第一通孔開口VO1，因此第一導電通孔圖案123可具有與第一通孔開口VO1的形狀對應的形狀。舉例而言，第一導電通孔圖案123可形成於其中共形地形成有第一初步晶種層125a的第一通孔開口VO1中。舉例而言，例如在如圖5D中所示的剖視圖中，第一導電通孔圖案123可具有寬度向下(或更靠近下電極接墊150)逐漸減小的形狀。
參照圖5E及圖5D，在形成第一導電線圖案121及第一導電通孔圖案123之後，可移除罩幕圖案MP，且然後可移除第一初步晶種層125a的藉由移除罩幕圖案MP暴露出的一部分。由於移除第一初步晶種層125a的藉由移除罩幕圖案MP暴露出的一部分，因此可形成第一晶種層125。第一晶種層125可插置於第一導電線圖案121與第一絕緣層111a之間、第一導電通孔圖案123與第一絕緣層111a的內側壁之間、以及導電通孔圖案123與下電極接墊150之間。
可使用與參照圖5A至圖5E示出的形成第一重佈線圖案120的方法相同的方法或相似的方法來形成圖4E中的第二重佈線圖案130及圖4E中的第三重佈線圖案140中的每一者。
圖6是示出根據本發明概念的一些實施例的半導體封裝10a的剖視圖。除了半導體封裝10a包括多個半導體晶片200a之外，圖6中所示的半導體封裝10a可與參照圖1及圖2闡述的半 導體封裝10實質上相同或相似。
參照圖6，半導體封裝10a可包括重佈線結構100及位於重佈線結構100上的所述多個半導體晶片200a。所述多個半導體晶片200a可包括彼此間隔開的第一半導體晶片201與第二半導體晶片203。第一半導體晶片201可包括半導體基板211及晶片接墊221，且第一半導體晶片201的晶片接墊221可經由晶片連接端子230電性連接至第三重佈線圖案140。第二半導體晶片203可包括半導體基板213及晶片接墊223，且第二半導體晶片203的晶片接墊223可經由晶片連接端子230電性連接至第三重佈線圖案140。
在示例性實施例中，第一半導體晶片201及第二半導體晶片203可包括不同類型的半導體晶片。舉例而言，當第一半導體晶片201是非記憶體晶片時，第二半導體晶片203可為記憶體晶片。舉例而言，第一半導體晶片201可包括邏輯晶片。第一半導體晶片201可包括中央處理單元(CPU)晶片、圖形處理單元(GPU)晶片或應用處理器(AP)晶片。在一些實施例中，第二半導體晶片203可包括例如動態隨機存取記憶體(DRAM)晶片、靜態隨機存取記憶體(SRAM)晶片、快閃記憶體晶片、電性可抹除及可程式化唯讀記憶體(EPROM)晶片、相變隨機存取記憶體(PRAM)晶片、磁性隨機存取記憶體(MRAM)晶片或電阻式隨機存取記憶體(RRAM)晶片。在一些實施例中，第二半導體晶片203可包括高頻寬記憶體(high bandwidth memory，HBM)DRAM半導體晶片。作為另一種選擇，在其他示例性實施例中，第一半 導體晶片201與第二半導體晶片203可包括相同類型的半導體晶片。在示例性實施例中，半導體封裝10a可包括系統級封裝(system in package，SIP)，其中不同種類的半導體晶片彼此電性連接以作為一個系統運作。
在此種情形中，由所述多個半導體晶片200a佔據的覆蓋區域可小於重佈線結構100的水平面積。由所述多個半導體晶片200a佔據的覆蓋區域可在垂直方向上與重佈線結構100完全交疊。舉例而言，在平面圖中，所述多個半導體晶片200a的面積可小於重佈線結構100的面積。在某些實施例中，所述多個半導體晶片200a可垂直地堆疊形成堆疊晶片。
圖7是示出根據本發明概念的實施例的半導體封裝10b的剖視圖。
參照圖7，半導體封裝10b可包括下封裝11L及位於下封裝11L上的上封裝11U。半導體封裝10b可包括其中上封裝11U附接至下封裝11L的層疊封裝(package-on-package，POP)形式的半導體封裝。
下封裝11L可包括：第一重佈線結構100L，包括重佈線絕緣層110L及重佈線圖案120L、130L及140L；第一半導體晶片200L；第一下電極接墊150L；第一晶片連接端子230L；第一底部填充材料層240L；第一模製層300L及第一導電柱160。下封裝11L的第一重佈線結構100L、第一半導體晶片200L、第一下電極接墊150L、第一晶片連接端子230L、第一底部填充材料層240L 及第一模製層300L可分別與以上參照圖1及圖2闡述的半導體封裝10的重佈線結構100、半導體晶片200、下電極接墊150、晶片連接端子230、底部填充材料層240及模製層300實質上相同或相似。
第一導電柱160可穿透第一模製層300L。第一重佈線結構100L的第三重佈線圖案140L的一部分可連接至第一模製層300L的下端部。第一模製層300L的上端部可連接至封裝間連接端子410。第一重佈線結構100L的第三重佈線圖案140L可接觸及/或電性連接至第一導電柱160的下端部。第一導電柱160的上端部可接觸及/或電性連接至封裝間連接端子410。
上封裝11U可包括：第二重佈線結構100U，包括第二重佈線絕緣層110U及第二重佈線圖案120U及140U；第二半導體晶片200U；第二下電極接墊150U；第二晶片連接端子230U；第二底部填充材料層240U；及第二模製層300U。上封裝11U的第二重佈線結構100U、第二半導體晶片200U、第二下電極接墊150U、第二晶片連接端子230U、第二底部填充材料層240U及第二模製層300U可分別與以上參照圖1及圖2闡述的半導體封裝10的重佈線結構100、半導體晶片200、下電極接墊150、晶片連接端子230、底部填充材料層240及模製層300實質上相同或相似。
上封裝11U可藉由插置於上封裝11U與下封裝11L之間的封裝間連接端子410電性連接及實體連接至下封裝11L。封裝間連接端子410可接觸上封裝11U的第二下電極接墊150U的底表 面且可接觸下封裝11L的第一導電柱160。
在示例性實施例中，類似於參照圖1及圖2闡述的下電極接墊150，上封裝11U的第二下電極接墊150U的一部分可自第二重佈線絕緣層110U突出。舉例而言，第二下電極接墊150U的嵌置於第二重佈線絕緣層110U中的一部分的厚度可大於第二下電極接墊150U的自第二重佈線絕緣層110U突出的另一部分的厚度。
在示例性實施例中，第一半導體晶片200L與第二半導體晶片200U可包括不同類型的半導體晶片。作為另一種選擇，在其他示例性實施例中，第一半導體晶片200L與第二半導體晶片200U可包括相同類型的半導體晶片。
第二半導體晶片200U可經由包括在第二重佈線結構100U中的所述多個導電線圖案121U及141U和多個導電通孔圖案123U及143U、第二下電極接墊150U、封裝間連接端子410、第一導電柱160、以及包括在第一重佈線結構100L中的所述多個導電線圖案121L、131L及141L及所述多個導電通孔圖案123L、133L及143L電性連接至第一半導體晶片200L及/或外部。
儘管已參照本發明概念的實施例具體示出及闡述了本發明概念，但是應理解，在不背離以下申請專利範圍的精神及範圍的情況下，可在本文中進行形式及細節上的各種改變。
10:半導體封裝
100:重佈線結構
110:重佈線絕緣層
111:第一絕緣層/絕緣層
113:第二絕緣層/絕緣層
115:第三絕緣層/絕緣層
118:第一表面
119:第二表面
120:第一重佈線圖案/重佈線圖案
121:第一導電線圖案/導電線圖案
123:第一導電通孔圖案/導電通孔圖案
125:第一晶種層/晶種層
130:第二重佈線圖案/重佈線圖案
131:第二導電線圖案/導電線圖案
133:第二導電通孔圖案/導電通孔圖案
135:第二晶種層/晶種層
140:第三重佈線圖案/重佈線圖案
141:第三導電線圖案/導電線圖案
143:第三導電通孔圖案/導電通孔圖案
145:第三晶種層/晶種層
150:下電極接墊/電極接墊
200:半導體晶片
210:半導體基板
220:晶片接墊
230:晶片連接端子
240:底部填充材料層
300:模製層
400:外部連接端子
II:區域

Claims (19)

  1. 一種半導體封裝，包括：重佈線結構，包括重佈線絕緣層及重佈線圖案，所述重佈線絕緣層包括第一絕緣層；第一半導體晶片，設置於所述重佈線絕緣層的第一表面上且電性連接至所述重佈線圖案；以及下電極接墊，設置於所述重佈線絕緣層的與所述第一表面相對的第二表面上，所述下電極接墊包括嵌置於所述重佈線絕緣層中的第一部分及自所述重佈線絕緣層的所述第二表面突出的第二部分，其中所述下電極接墊的所述第一部分的厚度大於所述下電極接墊的所述第二部分的厚度，其中所述重佈線圖案形成在所述第一絕緣層的頂表面上，且所述下電極接墊形成在所述第一絕緣層的底表面上，且其中所述重佈線圖案包括晶種層，所述晶種層接觸所述第一絕緣層的所述頂表面及所述下電極接墊的頂表面。
  2. 如請求項1所述的半導體封裝，其中所述下電極接墊的所述第二部分的所述厚度介於所述下電極接墊的總厚度的約10%與約30%之間。
  3. 如請求項1所述的半導體封裝，其中所述下電極接墊的所述第二部分的側壁暴露至所述重佈線絕緣層的外部。
  4. 如請求項1所述的半導體封裝，其中所述重佈線結構更包括導電通孔圖案，所述導電通孔圖案穿過所述重佈線絕緣層的一部分而電性連接至所述下電極接墊。
  5. 如請求項4所述的半導體封裝，其中所述導電通孔圖案的寬度在第一方向上逐漸變窄，其中所述第一方向自所述重佈線絕緣層的所述第一表面指向所述重佈線絕緣層的所述第二表面。
  6. 如請求項4所述的半導體封裝，其中所述晶種層環繞所述導電通孔圖案的側壁。
  7. 如請求項1所述的半導體封裝，其中所述第一半導體晶片包括設置於面對所述重佈線絕緣層的所述第一表面的表面上的晶片接墊，且所述半導體封裝更包括設置於所述重佈線圖案的位於所述重佈線絕緣層的所述第一表面上的一部分與所述第一半導體晶片的所述晶片接墊之間的晶片連接端子。
  8. 如請求項7所述的半導體封裝，更包括設置於所述第一半導體晶片與所述重佈線絕緣層的所述第一表面之間且環繞所述晶片連接端子的底部填充材料層。
  9. 如請求項1所述的半導體封裝，更包括位於所述下電極接墊的底表面上的外部連接端子。
  10. 如請求項9所述的半導體封裝， 其中所述下電極接墊的所述底表面是平的。
  11. 如請求項1所述的半導體封裝，更包括：模製層，覆蓋所述第一半導體晶片的側表面；以及導電柱，穿透所述模製層且電性連接至所述重佈線圖案。
  12. 如請求項1所述的半導體封裝，更包括：第二半導體晶片，與所述第一半導體晶片間隔開，其中所述第一半導體晶片是邏輯晶片且所述第二半導體晶片是記憶體晶片。
  13. 一種半導體封裝，包括：重佈線絕緣層，包括第一重佈線絕緣層及第二重佈線絕緣層，所述第一重佈線絕緣層的上表面對應於所述重佈線絕緣層的第一表面，所述第二重佈線絕緣層的下表面對應於所述重佈線絕緣層的第二表面，所述第一表面與所述第二表面彼此相對；第一導電線圖案，位於所述第二重佈線絕緣層的上表面上方且接觸所述第二重佈線絕緣層的所述上表面；第二導電線圖案，位於所述重佈線絕緣層的所述第一表面上；下電極接墊，位於所述重佈線絕緣層的所述第二表面上且包括嵌置於所述重佈線絕緣層中的第一部分及自所述重佈線絕緣層的所述第二表面突出的第二部分；第一導電通孔圖案，在所述第一導電線圖案與所述下電極接墊之間延伸且接觸所述下電極接墊；第二導電通孔圖案，在所述第二導電線圖案與所述第一導電 線圖案之間延伸；以及半導體晶片，設置於所述重佈線絕緣層上且電性連接至所述第二導電線圖案，其中所述第一導電通孔圖案的寬度及所述第二導電通孔圖案的寬度各自在第一方向上逐漸變窄，其中所述第一方向是自所述重佈線絕緣層的所述第一表面朝向所述重佈線絕緣層的所述第二表面。
  14. 如請求項13所述的半導體封裝，其中所述下電極接墊的所述第二部分的厚度介於約1微米與約3微米之間。
  15. 如請求項13所述的半導體封裝，其中所述下電極接墊的所述第二部分的側壁暴露至所述重佈線絕緣層的外部；且所述下電極接墊的所述第一部分的側壁的高度大於所述下電極接墊的所述第二部分的所述側壁的高度。
  16. 如請求項13所述的半導體封裝，更包括：第一晶種層，環繞所述第一導電通孔圖案的側壁且設置於所述第一導電通孔圖案與所述下電極接墊之間；以及第二晶種層，環繞所述第二導電通孔圖案的側壁且設置於所述第二導電通孔圖案與所述第一導電通孔圖案之間。
  17. 如請求項13所述的半導體封裝，更包括：晶片連接端子，設置於所述第二導電線圖案與所述 半導體晶片之間；以及底部填充材料層，設置於所述半導體晶片與所述重佈線絕緣層的所述第一表面之間且環繞所述晶片連接端子。
  18. 如請求項13所述的半導體封裝，更包括：外部連接端子，位於所述下電極接墊的所述第二部分的底表面上，其中所述下電極接墊的所述第二部分的所述底表面是平的。
  19. 一種半導體封裝，包括：重佈線結構，包括：多個絕緣層；多個導電線圖案，設置於所述多個絕緣層中的每一者的上表面上方且接觸所述多個絕緣層中的每一者的上表面；以及多個導電通孔圖案，穿透所述多個絕緣層中的至少一者且連接至所述多個導電線圖案中的至少一者；半導體晶片，位於所述重佈線結構的上表面上；晶片連接端子，設置於所述半導體晶片與所述多個導電線圖案的最上層的導電線圖案之間；底部填充材料層，在所述半導體晶片與所述重佈線結構之間環繞所述晶片連接端子；模製層，覆蓋所述半導體晶片的至少一部分；下電極接墊，位於所述重佈線結構的底表面上；以及外部連接端子，位於所述下電極接墊上，其中所述下電極接墊包括嵌置於所述多個絕緣層中的最下絕緣層中的第一部分及自所述最下絕緣層突出的第二部分，且所述 下電極接墊的所述第二部分的厚度小於所述下電極接墊的所述第一部分的厚度，且其中所述下電極接墊在剖視圖中具有矩形形狀。
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