CN112151461A - 半导体封装及其制造方法 - Google Patents
半导体封装及其制造方法 Download PDFInfo
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- CN112151461A CN112151461A CN202010272728.5A CN202010272728A CN112151461A CN 112151461 A CN112151461 A CN 112151461A CN 202010272728 A CN202010272728 A CN 202010272728A CN 112151461 A CN112151461 A CN 112151461A
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- lower electrode
- redistribution
- electrode pad
- semiconductor package
- insulating layer
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Abstract
公开了一种半导体封装包括:重新分布结构,包括重新分布绝缘层和重新分布图案;第一半导体芯片,设置在重新分布绝缘层的第一表面上并电连接到重新分布图案;以及下电极焊盘,设置在重新分布绝缘层的与第一表面相对的第二表面上,下电极焊盘包括嵌入在重新分布绝缘层中的第一部分和从重新分布绝缘层的第二表面突出的第二部分,其中,下电极焊盘的第一部分的厚度大于下电极焊盘的第二部分的厚度。
Description
相关申请的交叉引用
本申请要求于2019年6月28日在韩国知识产权局提交的韩国专利申请10-2019-0078341的优先权的权益,其公开内容通过引用全部合并于此。
技术领域
本发明构思涉及一种半导体封装和一种制造该半导体封装的方法,并且更具体地,涉及一种扇出半导体封装和一种制造扇出半导体封装的方法。例如,本公开涉及扇出晶片级封装(FOWLP)的方法和器件。
背景技术
近来,由于在电子产品市场中对便携式设备的需求迅速增长,因此一直需要安装在这些电子产品中的电子部件的小型化和轻量化。对于电子部件的小型化和轻量化,有利的是,安装在其上的半导体封装具有较小的体积,同时能够处理大量数据。特别地,在具有增加数量的输入和输出(I/O)端子的高度集成的半导体芯片中,可以减小输入和输出端子之间的间隔,因此可能在输入和输出端子之间发生干扰。为了消除输入和输出端子之间的这种干扰,在输入和输出端子之间具有增大的间隔的扇出半导体封装是有益的。
发明内容
本发明构思提供了具有提高的可靠性的半导体封装以及制造该半导体封装的方法。
根据本发明构思的一个方面,提出了一种半导体封装,包括:重新分布结构,包括重新分布绝缘层和重新分布图案;第一半导体芯片,设置在重新分布绝缘层的第一表面上并电连接到重新分布图案;以及下电极焊盘,设置在重新分布绝缘层的与第一表面相对的第二表面上,下电极焊盘包括嵌入在重新分布绝缘层中的第一部分和从重新分布绝缘层的第二表面突出的第二部分,其中,下电极焊盘的第一部分的厚度大于下电极焊盘的第二部分的厚度。
根据本发明构思的一个方面,提出了一种半导体封装,包括:重新分布绝缘层,包括彼此相对的第一表面和第二表面;第一导电线图案,在重新分布绝缘层中;第二导电线图案,在重新分布绝缘层的第一表面上;下电极焊盘,包括嵌入在重新分布绝缘层中的第一部分、和从重新分布绝缘层的第二表面突出的第二部分;第一导电通孔图案,在第一导电线图案与下电极焊盘之间延伸,并且与下电极焊盘接触;第二导电通孔图案,在第二导电线图案与第一导电线图案之间延伸;以及半导体芯片,设置在重新分布绝缘层上,并且电连接到第二导电线图案。
根据本发明构思的一个方面,提出了一种半导体封装,包括:重新分布结构,包括多个绝缘层、没置在多个绝缘层中的每一个绝缘层的上表面上的多个导电线图案、以及多个导电通孔图案,多个导电通孔图案穿透多个绝缘层中的至少一个并连接到多个导电线图案中的至少一个;半导体芯片,在重新分布结构的上表面上;芯片连接端子,介于半导体芯片与多个导电线图案中的最上层的导电线图案之间;底部填充材料层,围绕半导体芯片与重新分布结构之间的芯片连接端子;模制层,覆盖半导体芯片的至少一部分;下电极焊盘,在重新分布结构的底表面上;以及外部连接端子,在下电极焊盘上,其中,下电极焊盘包括嵌入多个绝缘层中的最下绝缘层中的第一部分、和从最下绝缘层突出的第二部分,并且下电极焊盘的第二部分的厚度小于下电极焊盘的第一部分的厚度。
根据本发明构思的一个方面,提供了一种制造半导体封装的方法,该方法包括:在载体衬底上形成覆盖绝缘层;在覆盖绝缘层上形成下电极焊盘;形成重新分布结构,该重新分布结构包括覆盖下电极焊盘的重新分布绝缘层和电连接到下电极焊盘的重新分布图案;将半导体芯片布置在重新分布结构上;去除载体衬底,并且去除覆盖绝缘层盘;以及去除重新分布绝缘层的一部分,以暴露下电极焊盘的侧壁的一部分。
附图说明
根据以下结合附图进行的详细描述,将更清楚地理解本发明构思的实施例,在附图中:
图1是示出根据本发明构思的示例实施例的半导体封装的截面图;
图2是根据本发明构思的示例实施例的图1中的区域“II”的放大截面图;
图3是示出根据本发明构思的示例实施例的制造半导体封装的方法的流程图;
图4A至图4L是顺序地示出根据本发明构思的示例实施例的制造半导体封装的方法的截面图;
图5A至图5E是顺序示出根据本发明构思的示例实施例的形成第一重新分布图案的方法的截面图;
图6是示出根据本发明构思的示例实施例的半导体封装的截面图;以及
图7是示出根据本发明构思的示例实施例的半导体封装的截面图。
具体实施方式
在下文中,将参考附图详细描述本发明构思的示例实施例。在附图中,相同的附图标记用于相同的元件,并且将省略其多余描述。
图1是示出根据本发明构思的示例实施例的半导体封装10的截面图。图2是根据本发明构思的示例实施例的图1的区域“II”的放大截面图。
参照图1和图2,半导体封装10可以包括重新分布结构100、设置在重新分布结构100的上侧上的半导体芯片200、以及设置在重新分布结构100的下侧上的下电极焊盘150。
重新分布结构100可以包括重新分布绝缘层110和多个重新分布图案120、130和140。
重新分布绝缘层110可以包括多个绝缘层111、113和115。多个绝缘层111、113和115中的每一个可以包括例如包含有机化合物的材料膜。在示例实施例中,多个绝缘层111、113和115中的每一个可以包括包含有机聚合物材料的材料膜。在示例实施例中,多个绝缘层111、113和115中的每一个可以包括绝缘材料,其中,绝缘材料可以包括能够在光刻工艺中使用的可光成像介电(PID)材料。例如,多个绝缘层111、113和115中的每一个可以包括光敏聚酰亚胺(PSPI)。在示例实施例中,多个绝缘层111、113和115中的每一个可以包括氧化物或氮化物。
多个重新分布图案120、130和140可以包括多个导电线图案121、131和141以及多个导电通孔图案123、133和143。多个导电线图案121、131和141可以设置在多个绝缘层111、113和115中的每一个的上表面和下表面中的至少一个表面上。多个导电通孔图案123、133和143可以穿透多个绝缘层111、113和115中的至少一个。多个导电通孔图案123、133和143可以连接到多个导电线图案121、131和141中的至少一个,和/或可以连接到下电极焊盘150。
多个种子层125、135和145可以分别介于多个绝缘层111、113和115与多个导电线图案121、131和141之间,并且可以分别介于在多个绝缘层111、113和115与多个导电通孔图案123、133和143之间。在示例实施例中,可以通过执行物理气相沉积来形成多个种子层125、135和145,并且多个导电线图案121、131和141以及多个导电通孔图案123、133和143可以用无电镀覆工艺例如化学镀覆工艺或自动催化镀覆工艺来形成。
例如,多个种子层125、135和145可以选自包括由铜(Cu)、钛(Ti)、钨化钛(TiW)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、铬(Cr)、铝(Al)等组成的组。然而,多个种子层125、135和145不限于这些材料。在示例实施例中,多个种子层125、135和145可以包括具有铜堆叠在钛上的Cu/Ti、或具有铜堆叠在钨化钛上的Cu/TiW。
多个导电线图案121、131和141以及多个导电通孔图案123、133和143可以包括诸如铜(Cu)、铝(Al)、钨(W)、钛(Ti)和钽(Ta)、铟(In)、钼(Mo)、锰(Mn)、钴(Co)、锡(Sn)、镍(Ni)、镁(Mg)、铼(Re)、铍(Be)、镓(Ga)或钌(Ru)的金属或其合金,但不限于此。在示例实施例中,当多个导电线图案121、131和141以及多个导电通孔图案123、133和143包括铜(Cu)时,多个种子层125、135和145的至少一部分可以用作扩散阻挡层。例如,扩散阻挡层可以防止/减少导电线图案121、131和141和/或导电通孔图案123、133和143的材料扩散到绝缘层111、113和115中。
多个导电线图案121、131和141的一部分可以与多个导电通孔图案123、133和143的一部分一起形成单体。例如,多个导电线图案121、131和141的一部分可以与多个导电通孔图案123、133和143的一部分形成为单体,多个导电通孔图案123、133和143的一部分与多个导电线图案1121、131和141的一部分的下侧接触。备选地,多个导电线图案121、131和141的一部分可以与多个导电通孔图案123、133和143的一部分形成为单体,多个导电通孔图案123、133和143的一部分与多个导电线图案121、131和141的一部分的上侧接触。在一些实施例中,每个导电通孔图案123、133和143可以与设置在上方的导电线图案121、131和141中的相应一个集成以形成如图1所示的连续体。在某些实施例中,每个导电通孔图案123、133和143可以与设置在下方的对应导电线图案121、131或141集成以形成连续体,这不同于图1。
将理解,当提及元件“连接”或“耦接”“到”另一元件或在另一元件“上”时,该元件可以直接连接或耦接到该另一元件或直接在该另一元件上,或者可以存在介于中间的元件。相比之下,当提及元件“直接连接”或“直接耦接”到另一元件或“接触”另一元件或与另一元件“接触”时,不存在介于中间的元件。
下面将更详细地描述重新分布结构100的配置。
重新分布绝缘层110可以包括顺序堆叠的第一绝缘层111、第二绝缘层113和第三绝缘层115。第一重新分布图案120可以包括第一导电线图案121、第一导电通孔图案123和第一种子层125。第二重新分布图案130可以包括第二导电线图案131、第二导电通孔图案133和第二种子层135。第三重新分布图案140可以包括第三导电线图案141、第三导电通孔图案143和第三种子层145。
第一绝缘层111可以包括第一通孔开口VO1,该第一通孔开口VO1暴露出150的一部分。第一种子层125可以设置在第一绝缘层111的上表面的一部分、第一通孔开口VO1的侧壁以及通过第一通孔开口VO1暴露的下电极焊盘150的上表面的一部分上。第一种子层125的一部分可以介于第一导电线图案121与第一绝缘层111的上表面之间,第一种子层125的另一部分可以形成为围绕第一导电通孔图案123的侧壁,并且第一种子层125的另一部分可以介于第一导电通孔图案123与下电极焊盘150之间。
除非上下文另有说明,否则术语第一、第二、第三等用作标签,以将一个元件、组件、区域、层或部分与另一元件、组件、区域、层或部分(其可以或可以不相似)。因此,在说明书的一部分(或权利要求)中下面讨论的第元件、组件、区域、层或部分可以在说明书的另一部分(或另一权利要求)中称为第二元件、组件、区域、层或部分。
第一导电线图案121和第一导电通孔图案123可以设置在第一种子层125上。第一导电线图案121和第一导电通孔图案123可以通过镀覆工艺一起形成,并且可以彼此集成为单体。第一导电线图案121可以设置在第一种子层125的形成在第一绝缘层111的上表面上的部分上,并且第一导电线图案121也可以设置在第一导电通孔图案123上。第一导电通孔图案123可以覆盖第一通孔开口VO1中的第一种子层125的一部分,并且可以填充第一通孔开口VO1。例如,第一导电通孔图案123的顶部可以具有与第一绝缘层111的上表面相同的水平(例如,在相同的竖直水平处)。例如,第一导电通孔图案123和第一种子层125的一部分可以从第一通孔开口VO1的底部到顶部填充第一通孔开口VO1。第一导电通孔图案123可以穿透第一绝缘层111以将第一导电线图案121连接到下电极焊盘150。例如,第一导电通孔图案123可以将第一导电线图案121电连接到下电极焊盘150。
这里的实施例可以用理想化的视图示出(尽管为了清楚起见,可能夸大了相对尺寸)。应当理解,取决于制造技术和/或公差,实际的实施方式可以与这些示例性视图不同。因此,当指代取向、布局、位置、形状、尺寸、数量或其他度量时,使用如本文所使用的诸如“相同”、“相等”之类的术语以及诸如“平行”、“均匀”、“平面”、“共面”、“圆柱形”、“正方形”等几何描述对某些特征的描述包括来自完全相同的可接受的变化,该变化包括几乎相同的布局、位置、形状、尺寸、数量或例如由于制造过程而发生的在可接受的变化内的其他度量。除非上下文或其他陈述另有说明,否则术语“基本上”在本文中可以用于强调该含义。
在示例实施例中,第一导电通孔图案123可以具有在从重新分布绝缘层110的第一表面118到第二表面119的方向上逐渐减小的形状。例如,与第一绝缘层111的上表面平行的第一导电通孔图案123的截面积可以从第一绝缘层111的上表面到第一绝缘层111的下表面逐渐减小。例如,如图1和图2所示,在截面图中第一导电通孔图案123的宽度可以从第一导电通孔图案123的顶部到底部逐渐减小。
第二绝缘层113可以堆叠在第一绝缘层111上,该第二绝缘层113覆盖第一导电线图案121的一部分并且具有第二通孔开口VO2,该第二通孔开口VO2暴露出第一导电线图案121的其余部分。例如,第一导电线图案121的一部分可以被第二绝缘层113覆盖,并且第一导电线图案121的一部分可以通过形成在第二绝缘层113中的第二通孔开口VO2而被暴露。
第二种子层135可以设置在第二绝缘层113的上表面的一部分、第二通孔开口VO2的侧壁、以及通过第二导电通孔开口VO2暴露的第一导电线图案121的上表面的一部分上。第二种子层135的一部分可以介于第二导电线图案131与第二绝缘层113的上表面之间,第二种子层135的另一部分可以形成为围绕第二导电通孔图案133的侧壁,并且第二种子层135的另一部分可以介于第二导电通孔图案133与第一导电线图案121之间。
第二导电通孔图案133和第二导电线图案131可以设置在第二种子层135上。第二导电通孔图案133和第二导电线图案131可以通过镀覆工艺形成,并且可以彼此集成为单体。第二导电线图案131可以设置在第二绝缘层113的上表面上的第二种子层135的一部分上,并且第二导电线图案131也可以设置在第二导电通孔图案133上。第二导电通孔图案133可以覆盖第二通孔开口VO2中的第二种子层135的一部分,并且可以填充第二通孔开口VO2。例如,第二导电通孔图案133的顶部可以具有与第二绝缘层113的上表面相同的水平(例如,在相同的竖直水平处)。例如,第二导电通孔图案133和第二种子层135的一部分可以从第二通孔开口VO1的底部到顶部填充第二通孔开口VO2。第二导电通孔图案133可以穿透第二绝缘层113以将第二导电线图案131连接到第一导电线图案121。例如,第二导电通孔图案133可以将第二导电线图案131电连接到第一导电线图案121。
在示例实施例中,第二导电通孔图案133可以具有在从重新分布绝缘层110的第一表面118到第二表面119的方向上逐渐减小的形状。例如,与第二绝缘层113的上表面平行的第二导电通孔图案133的截面积可以从第二绝缘层113的上表面到第二绝缘层113的下表面逐渐减小。例如,如图1和图2所示,在截面图中第二导电通孔图案133的宽度可以从第二导电通孔图案133的顶部到底部逐渐减小。
第三绝缘层115可以堆叠在第二绝缘层113上,该第二绝缘层115覆盖第二导电线图案131的一部分并且具有第三通孔开口VO3,该第三通孔开口VO3暴露出第二导电线图案131的其余部分。例如,第二导电线图案131的一部分可以被第三绝缘层115覆盖,并且第二导电线图案131的一部分可以通过形成在第三绝缘层115中的第三通孔开口VO3而暴露。
第三种子层145可以设置在第三绝缘层115的上表面的一部分、第三通孔开口VO3的侧壁、以及通过第三导电通孔开口VO3暴露的第二导电线图案131的上表面的一部分上。第三种子层145的一部分可以介于第三导电线图案141与第三绝缘层115的上表面之间,第三种子层145的另一部分可以形成为围绕第三导电通孔图案143的侧壁,并且第三种子层145的另一部分可以介于第三导电通孔图案143和第二导电线图案131之间。
第三导电通孔图案143和第三导电线图案141可以设置在第三种子层145上。第三导电通孔图案143和第三导电线图案141可以通过镀覆工艺形成,并且可以彼此集成为单体。第三导电线图案141可以设置在第三绝缘层115的上表面上的第三种子层145的一部分上,并且第三导电线图案141也可以设置在第三导电通孔图案143上。第三导电通孔图案143可以覆盖第三通孔开口VO2中的第三种子层145的一部分,并且可以填充第三通孔开口VO3。例如,第三导电通孔图案143的顶部可以具有与第三绝缘层115的上表面相同的水平(例如,在相同的竖直水平处)。例如,第三导电通孔图案143、和第二种子层145的一部分可以从第二通孔开口VO1的底部到顶部填充第二通孔开口VO2。第三导电通孔图案143可以穿透第三绝缘层115以将第三导电线图案141连接到第二导电线图案131。例如,第三导电通孔图案143可以将第三导电线图案141电连接到第二导电线图案131。
在示例实施例中,第三导电通孔图案143可以具有在从重新分布绝缘层110的第一表面118到第二表面119的方向上逐渐减小的形状。例如,与第三绝缘层115的上表面平行的第三导电通孔图案143的截面积可以从第三绝缘层115的上表面到第三绝缘层115的下表面逐渐减小。例如,如图1和图2所示,在截面图中第三导电通孔图案143的宽度可以从第三导电通孔图案143的顶部到底部逐渐减小。
在示例实施例中,第三导电线图案141可以设置在重新分布绝缘层110的第一表面118上,并且可以用作可以附接到半导体芯片200的上电极焊盘。
在图1中,重新分布结构100被示出为包括三个绝缘层111、113和115、三个导电线图案121、131和141以及三个导电通孔图案123、133和143,但是不限于此。绝缘层的数量、导电线图案的数量和导电通孔图案的数量可以根据重新分布结构100中的电路互连的设计进行各种修改。
半导体芯片200可以被附接到重新分布结构100上。例如,半导体芯片200可以以倒装芯片的方式安装在重新分布结构100上。例如,半导体芯片200可以被倒置以使芯片焊盘220下降到芯片连接端子230上和/或朝向第三导线图案141下降。
半导体芯片200可以包括例如中央处理单元(CPU)芯片、图形处理单元(GPU)芯片或应用处理器(AP)芯片。半导体芯片200可以包括例如动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、闪存芯片、电可擦除可编程只读存储器(EPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片或者电阻性随机存取存储器(RRAM)芯片。
半导体芯片200可以包括半导体衬底210和设置在半导体衬底210的一个表面上的芯片焊盘220。
半导体衬底210可以包括例如硅(Si)。备选地,半导体衬底210可以包括诸如锗(Ge)之类的半导体元素或者诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)和/或磷化铟(InP)之类的化合物半导体。半导体衬底210可以具有有源表面和与有源表面相对的无源表面。在示例实施例中,半导体衬底210的有源表面可以面对重新分布结构100。
半导体芯片200可以在半导体衬底210的有源表面上包括多个各种单独器件。
芯片连接端子230可以设置在半导体芯片200的芯片焊盘220与用作重新分布结构100的上电极焊盘的第三导电线图案141之间。芯片连接端子230可以将半导体芯片200的芯片焊盘220与第三导电线图案141电连接。芯片连接端子230可以包括例如柱状结构、焊料凸块、焊料球和焊料层中的至少一种。
通过芯片连接端子230、重新分布结构100的第一重新分布图案至第三重新分布图案120、130和140、下电极焊盘150和外部连接端子400的路径,半导体芯片200可以从外部接收控制信号、电源信号和接地信号中的至少一个用于半导体芯片200的操作,并且半导体芯片200还可以从外部接收要存储在半导体芯片200中的数据信号,或者可以将存储在半导体芯片200中的数据信号提供给外部。
围绕芯片连接端子230的底部填充材料层240可以被填充在半导体芯片200与重新分布结构100之间。底部填充材料层240可以包括例如通过毛细管底部填充方法形成的环氧树脂。在示例实施例中,底部填充材料层240可以包括非导电膜(NCF),例如绝缘体。
下电极焊盘150可以设置在重新分布结构100的下侧。外部连接端子400可以设置在下电极焊盘150上。半导体封装10可以通过外部连接端子400电连接到并且安装在电子产品/设备的模块衬底或系统板上。下电极焊盘150可以用作设置有外部连接端子400的凸块下金属(UBM)。
例如,下电极焊盘150和本文描述的其他焊盘可以完全具有均匀的厚度。下电极焊盘150的设置有外部连接端子400的底表面可以包括平坦表面。下电极焊盘150的顶表面还可以具有平坦表面,该平坦表面可以平行于底表面。例如,下电极焊盘150可以包括诸如铜(Cu)、铝(Al)、钨(W)、钛(Ti)、钽(Ta)、铟(In)、钼(Mo)、锰(Mn)、钴(Co)、锡(Sn)、镍(Ni)、镁(Mg)、铼(Re)、铍(Be)、镓(Ga)或钌(Ru)的金属或其合金,但是不限于此。
在示例实施例中,下电极焊盘150的一部分可以被嵌入在重新分布绝缘层110中,并且下电极焊盘150的另一部分可以从重新分布绝缘层110突出。例如,下电极焊盘150的嵌入部分可以是相对于重新分布绝缘层110的表面水平凹入到重新分布绝缘层110中的部分。例如,重新分布绝缘层110可以覆盖下电极焊盘150的侧壁的一部分,但是可以不覆盖下电极焊盘150的侧壁的另一部分。在某些实施例中,下电极焊盘150的一部分可以被嵌入在重新分布绝缘层110中,并且下电极焊盘150的其他部分可以从重新分布绝缘层110突出,如图1和图2所示。例如,下电极焊盘150的顶表面的水平可以高于重新分布绝缘层110的第二表面119的水平,如图1和图2所示。例如,下电极焊盘150的顶表面可以接触重新分布绝缘层110。
根据本发明构思的示例实施例,下电极焊盘150的另一部分可以从重新分布绝缘层110的第二表面119突出,并且因此沿着重新分布绝缘层110的第二表面119的应力可以在下电极焊盘150的侧壁处减小。因此,可以防止由于在半导体封装10上的应力而对下电极焊盘150和电极焊盘150周围的重新分布结构100造成损坏,并且最终可以提高半导体封装10的可靠性。
例如,下电极焊盘150嵌入在重新分布绝缘层110中(或由重新分布绝缘层110包围)的部分可以被定义为下电极焊盘150的第一部分151,并且下电极焊盘150的从重新分布绝缘层110的第二表面119突出的另一部分可以被定义为下电极焊盘150的第二部分153。在这种情况下,下电极焊盘150的第一部分151的侧壁可以被重新分布绝缘层110覆盖,并且下电极焊盘150的第二部分153的侧壁可以不被重新分布绝缘层110覆盖。下电极焊盘150的第二部分153的侧壁可以暴露于外部。例如,电极焊盘150的第二部分153可以暴露于重新分布绝缘层110的外部。例如,当将半导体封装10安装在/连接到另一器件/结构时,第二部分153可以被另一结构(例如由外部连接端子400和/或另一结构)覆盖。
在示例实施例中,下电极焊盘150的第一部分151的厚度151t可以大于下电极焊盘150的第二部分153的厚度153t。例如,下电极焊盘150的第一部分151的侧壁的高度可以大于下电极焊盘150的第二部分153的侧壁的高度。当下电极焊盘150的从重新分布绝缘层110突出的第二部分153的厚度153t太小时,下电极焊盘150的侧壁处的应力松弛效应可降低。与下电极焊盘150的总厚度相比,当下电极焊盘150的从重新分布绝缘层110突出的第二部分153的厚度153t太大时,下电极焊盘150的嵌入在重新分布绝缘层110中的第一部分151的厚度151t可能太小,使得重新分布绝缘层110与下电极焊盘150之间的粘附性可能降低。
在示例实施例中,下电极焊盘150的第二部分153的厚度153t可以在下电极焊盘150的总厚度的约10%和约30%之间。例如,当下电极焊盘150的厚度是10μm时,下电极焊盘150的从重新分布绝缘层110的第二表面119突出的第二部分153的厚度153t可以在约1μm和约3μm之间。例如,当下电极焊盘150的厚度是10μm时,下电极焊盘150的嵌入在重新分布绝缘层110中的第一部分151的厚度151t可以在约7μm和约9μm之间。第一部分151和第二部分153的侧壁的高度方向以及包括第一部分151和第二部分153在内的下电极焊盘150的厚度方向可以垂直于重新分布绝缘层110的第一表面118和/或第二表面119。
诸如“约”或“近似”之类的术语可以反映仅以较小的相对方式和/或以不显著改变某些元件的操作、功能或结构的方式变化的数量、大小、取向或布局。例如,从“约0.1到约10”的范围可以包含以下范围,如0.1左右的0%至5%偏差和10左右的0%至5%偏差,特别是这种偏差保持与所列的范围相同效果的情况。
半导体封装10还可以包括模制层300,该模制层300覆盖重新分布结构100上半导体芯片200的至少一部分。模制层300可以包括例如环氧模制复合物(EMC)。模制层300可以覆盖重新分布绝缘层110的第一表面118的一部分,并且可以覆盖半导体芯片200的侧表面。在这种情况下,半导体芯片200的上表面可以暴露于外部,例如暴露于模制层300的外部或暴露于半导体封装10的外部。在其他示例实施例中,模制层300还可以覆盖半导体芯片200的上表面。
尽管在附图中未示出,但是散热构件可以附接到半导体芯片200的上表面。散热构件可以包括例如散热块或散热器。在示例实施例中,导热界面材料(TIM)可以设置在散热构件与半导体芯片200的上表面之间。导热界面材料可以包括例如矿物油、油脂、间隙填充腻子、相变凝胶、相变材料焊盘、颗粒填充的环氧树脂。
半导体芯片200的占地面积可以小于重新分布结构100的占地面积。例如,在平面图中,半导体芯片200的面积可以小于重新分布结构100的面积。例如,半导体芯片200的水平宽度可以小于重新分布结构100的水平宽度。在示例实施例中,多个导电线图案121、131和141的一部分可以延伸以从半导体芯片200的侧表面沿水平方向进一步突出。例如,第一导电线图案121的一部分和第二导电线图案131的一部分可以从半导体芯片200的侧表面沿水平方向进一步突出。例如,在平面图中,第一导电图案121的一部分和/或第二导电图案131的一部分可以从半导体芯片200的侧表面突出。在某些实施例中,在平面图中,多个下电极焊盘150中的至少一个可以例如设置在从半导体芯片200的侧表面间隔开(例如向外)的位置处。
图3是示出根据本发明构思的示例实施例的制造半导体封装的方法的流程图。
参照图3,制造半导体封装的方法可以包括:第一步骤S110,在载体衬底上形成覆盖绝缘层;第二步骤S120,在覆盖绝缘层上形成下电极焊盘;第三步骤S130,形成重新分布结构;第四步骤S140,将半导体芯片附接在重新分布结构上,并形成模制层;第五步骤S150,去除载体衬底;第六步骤S160,去除覆盖绝缘层以暴露下电极焊盘;第七步骤S170,去除重新分布绝缘层的一部分,以暴露下电极焊盘的侧壁的一部分;以及第八步骤S180,在下电极焊盘上形成外部连接端子。
制造半导体封装的方法可以包括上述工艺步骤S110至S180。在其他实施例中,可以以与上述顺序不同的顺序来执行某些工艺步骤。例如,可以基本上同时地或以相反的顺序执行连续描述的工艺的两个步骤。稍后将参照图4A至图4L更详细地描述第一步骤S110至第八步骤S180中的每一个的技术特征。
图4A至图4L是顺序地示出根据本发明构思的示例实施例的制造半导体封装10的方法的截面图。
参照图4A,覆盖绝缘层320可以形成在附接有离型膜311的载体衬底310上。覆盖绝缘层320可以包括与图1的重新分布绝缘层110相同的绝缘材料,或者可以包括与重新分布结构绝缘层110不同的绝缘材料。例如,覆盖绝缘层320可以包括包含有机化合物的材料膜。在示例实施例中,覆盖绝缘层320可以包括光敏聚酰亚胺。备选地,例如,覆盖绝缘层320可以包括氧化物或氮化物。
载体衬底310可以支撑覆盖绝缘层320,并且可以包括在烘烤工艺和蚀刻工艺中具有工艺稳定性的任何材料。例如,可以在随后的过程中通过加热和/或激光去除载体衬底310。当随后通过激光烧蚀分离并去除载体衬底310时,载体衬底310可以包括透明衬底。当载体衬底310被分离并随后通过加热去除时,载体衬底310可以是耐热衬底。在示例实施例中,载体衬底310可以包括玻璃衬底。备选地,在其他示例实施例中,载体衬底310可以包括耐热有机聚合物材料,例如聚酰亚胺(PI)、聚醚醚酮(PEEK)、聚醚砜(PES)、聚苯硫醚(PPS)等,但不限于此。
离型膜311可以包括例如激光反应层,该激光反应层能够通过响应于激光照射而汽化来使载体衬底310可分离。离型膜311可以包括碳基材料层。例如,离型膜311可以包括非晶碳层(ACL)。例如,离型膜311可以包括具有烃化合物或其衍生物的旋涂硬掩模(SOH),该烃化合物具有基于总重量的约85重量%至约99重量%的相对高的碳含量。
参照图4B,下电极焊盘150可以形成在覆盖绝缘层320上。为了形成下电极焊盘150,导电材料膜可以形成在覆盖绝缘层320上,然后可以对导电材料膜进行图案化。下电极焊盘150可以形成为在覆盖绝缘层320的上表面上整体上具有均匀的厚度,并且下电极焊盘150的与覆盖绝缘层320的上表面接触的下表面可以具有平坦形状。
在示例实施例中,下电极焊盘150可以包括单一金属材料。备选地,下电极焊盘150可以具有多层结构,其中每一层包括与其他层不同的金属材料。
参照图4C,在形成下电极焊盘150之后,可以形成包括第一通孔开口VO1的第一绝缘层111a,其中第一通孔开口VO1暴露下电极焊盘150的一部分。例如,为了形成第一绝缘层111a,可以形成将下电极焊盘150和覆盖绝缘层320覆盖的绝缘材料膜,然后可以通过经由曝光和显影工艺去除绝缘材料膜的一部分来形成第一通孔开口VO1。下电极焊盘150的一部分可以被第一通孔开口VO1暴露。
参照图4D,可以在图4C的所得结构上形成第一种子层125、第一导电线图案121和第一导电通孔图案123。例如,第一种子层125可以形成为覆盖第一绝缘层111a的上表面、由第一通孔开口VO1提供的第一绝缘层111a的内侧壁(例如,第一通孔开口VO1的侧壁)和通过第一通孔开口VO1暴露出的下电极焊盘150。第一绝缘层111a的内侧壁可以是由第一通孔开口VO1形成的第一绝缘层111a的表面,例如内侧表面。第一导电线图案121可以沿着第一绝缘层111a的上表面延伸,并且第一导电通孔图案123可以例如与第一种子层125的一部分一起填充第一通孔开口VO1。第一种子层125、第一导电线图案121和第一导电通孔图案123可以构成第一重新分布图案120。稍后将参考图5A至图5E更详细地描述形成第一重新分布图案120的方法。
参照图4E,在图4D的所得结构上,通过与参照图4C和图4D所述的工艺基本相同或相似的工艺,可以顺序地形成包括第二通孔开口VO2的第二绝缘层113、第二重新分布图案130,包括第三通孔开口VO3的第三绝缘层115和第三重新分布图案140。第一绝缘层至第三绝缘层111、113和115以及第一重新分布图案至第三重新分布图案120、130和140可以构成重新分布结构100。
例如,第二种子层135可以形成为覆盖第二绝缘层113的上表面、由第二通孔开口VO2提供的第二绝缘层113的内侧壁(例如,第二通孔开口VO2的侧壁)、和第一导电线图案121的通过第二通孔开口VO2暴露出的部分。第二导电线图案131可以沿着第二绝缘层113的上表面延伸,并且第二导电通孔图案133可以例如与第二种子层135的一部分一起填充第二通孔开口VO2。第二种子层135、第二导电线图案131和第二导电通孔图案133可以构成第二重新分布图案130。
第三种子层145可以形成为覆盖第三绝缘层115的上表面、由第三通孔开口VO3提供的第三绝缘层115的内侧壁(例如,第三通孔开口VO3的侧壁)、和第二导电线图案131的通过第三通孔开口VO3暴露出的部分。第三导电线图案141可以沿着第三绝缘层115的上表面延伸,并且第三导电通孔图案143可以例如与第三种子层145的一部分一起填充第三通孔开口VO3。第三种子层145、第三导电线图案141和第三导电通孔图案143可以构成第三重新分布图案140。
参照图4F,半导体芯片200可以附接到重新分布结构100。半导体芯片200可以附接到重新分布结构100上,使得芯片焊盘220面对重新分布结构100。半导体芯片200的芯片焊盘220可以通过芯片连接端子230电连接到重新分布结构100的第三导电线图案141。在这种情况下,第三导电线图案141可以用作其中安置有芯片连接端子230的重新分布结构100的上电极焊盘。
在将半导体芯片200附接到重新分布结构100之后,可以形成底部填充材料层240以填充半导体芯片200与重新分布结构100之间的空间。底部填充材料层240可以围绕芯片连接端子230。例如,在将半导体芯片200附接到重新分布结构100之后,可以通过毛细管底部填充方法形成底部填充材料层240。在某些示例实施例中,可以通过在半导体芯片200的芯片焊盘220上附接非导电膜,然后在重新分布结构100上附接半导体芯片200,来形成底部填充材料层240。
参照图4G,在形成底部填充材料层240之后,可以形成用于模制半导体芯片200的模制层300。模制层300可以覆盖半导体芯片200的侧表面并且暴露半导体芯片200的上表面。模制层300可以覆盖重新分布绝缘层110的第一表面118的一部分。在其他示例实施例中,模制层300可以形成为进一步覆盖半导体芯片200的上表面。
将图4H与图4G一起参照,在形成模制层300之后,可以去除载体衬底310。例如,在图4G的所得结构中,可以将附接有离型膜311的载体衬底310与其他结构分离。例如,为了分离载体衬底310,可以用激光照射或加热离型膜311。由于载体衬底310的分离,覆盖绝缘层320可以被暴露。
参照图4I,在反转图4H的所得产物之后,可以去除覆盖绝缘层320以暴露下电极焊盘150。例如,可以执行蚀刻工艺以去除覆盖绝缘层320。随着覆盖绝缘层320的去除,下电极焊盘150的下表面可以被暴露。
参照图4J和图4I,在去除覆盖绝缘层320之后,可以去除图4I的第一绝缘层111a的一部分以暴露下电极焊盘150的侧壁的一部分。例如,可以执行干法蚀刻工艺以去除图4I的第一绝缘层111a的一部分。作为去除图4I的第一绝缘层111a的一部分的结果,图2的第一部分151可以被嵌入在第一绝缘层111中,并且下电极焊盘150的图2的第二部分153可以从第一绝缘层111突出。
在这种情况下,通过控制蚀刻速度和蚀刻时间,可以调节下电极焊盘150的从第一绝缘层111突出的厚度。在示例实施例中,作为在第一绝缘层111上的蚀刻工艺的结果,下电极焊盘150的从第一绝缘层111突出的第二部分153的厚度可以小于下电极焊盘150的嵌入第一绝缘层111中的第一部分151的厚度。
在示例实施例中,图4I的第一绝缘层111a的一部分和覆盖绝缘层320可以在同一蚀刻工艺中被去除。例如,可以通过执行一个蚀刻工艺来去除图4I的第一绝缘层111a的一部分和覆盖绝缘层320。在这种情况下,覆盖绝缘层320可以包括与图4I的第一绝缘层111a相同的材料。
备选地,在其他示例实施例中,可以通过单独的蚀刻工艺去除图4I的第一绝缘层111a的一部分和覆盖绝缘层320。
参照图4K,外部连接端子400可以附接到下电极焊盘150上。外部连接端子400可以包括例如焊球或凸块。
参照图4L,在形成外部连接端子400之后,可以通过沿着划线道SL切割图4K的所得产品的锯切工艺来完成如图1所示的锯切半导体封装10。
通常,在以芯片最后方式制造半导体封装的方法中,可以依次执行重新分布结构形成、芯片附接、UBM形成和焊球附接。然而,依据本发明构思的示例实施例的制造半导体封装的方法,由于可以在形成重新分布结构100之前首先形成用作UBM的下电极焊盘150,因此可以简化工艺并可以降低生产成本。
图5A至图5E是顺序示出根据本发明构思的示例实施例的形成第一重新分布图案120的方法的截面图。
参照图5A,可以在覆盖绝缘层320上形成绝缘材料层,并且可以对绝缘材料层执行蚀刻工艺以形成包括第一通孔开口VO1的第一绝缘层111a。例如,为了形成第一通孔开口VO1,可以执行使用等离子体的反应离子蚀刻(RIE)工艺、激光钻孔等。
在示例实施例中,第一通孔开口VO1可以具有这样的形状,其中第一通孔开口VO1的宽度向下逐渐变窄(或更靠近下电极焊盘150),例如在如图5A所示的截面图中。由第一通孔开口VO1提供的第一绝缘层111a的内侧壁(例如,第一通孔开口Vo1的侧壁)可以具有倾斜的侧壁部分。例如,可以通过控制蚀刻工艺中的蚀刻气体、气体供应量和蚀刻速率等的组合来调节由第一绝缘层111a的下表面与倾斜的侧壁部分形成的角度。例如,由第一绝缘层111a的下表面与倾斜的侧壁部分形成的角度可以在约75度和约85度之间,例如在类似于图5A中的截面图中。
参照图5B,第一初步种子层125a可以形成为覆盖第一绝缘层111a的上表面、由第一通孔开口VO1提供的第一绝缘层111a的内侧壁(例如,第一通孔开口VO1的侧壁)、和下电极焊盘150的通过第一通孔开口VO1暴露的部分。第一初步种子层125a可以在第一绝缘层111a的上表面、由第一通孔开口VO1提供的第一绝缘层111a的内侧壁、和下电极焊盘150的通过第一通孔开口VO1暴露的部分上共形地延伸。
参照图5C,可以在第一初步种子层125a上形成包括开口OP的掩模图案MP。掩模图案MP的开口0P可以暴露第一初步种子层125a的一部分,并且限定在后续工艺中形成第一导电线图案121和第一导电通孔图案123的区域。
参照图5D,第一导电线图案121和第一导电通孔图案123可以形成在第一初步种子层125a的通过掩模图案MP的开口OP暴露的部分上。第一导电线图案121可以在第一绝缘层111a的上表面上延伸,并且第一导电通孔图案123可以例如与第一初步种子层125的一部分一起填充第一通孔开口VO1。例如,第一导电线图案121和第一导电通孔图案123可以使用第一初步种子层125a作为种子通过镀覆工艺一起形成。第一导电线图案121和第一导电通孔图案123可以整体地形成为单体。
在这种情况下,由于第一导电通孔图案123可以形成为填充第一绝缘层111a中的第一通孔开口VO1,因此第一导电通孔图案123可以具有与第一通孔开口VO1的形状相对应的形状。例如,第一导电通孔图案123可以形成在第一通孔开口VO1中,在第一通孔开口VO1中共形地形成有第一初步种子层125a。例如,第一导电通孔图案123可以具有例如在如图5D所示的截面图中向下的宽度逐渐减小(或更靠近下电极焊盘150)的形状。
参照图5E和图5D,在形成第一导电线图案121和第一导电通孔图案123之后,可以去除掩模图案MP,然后去除第一初步种子层125a的通过去除掩模图案MP所暴露的部分。作为去除第一初步种子层125a的通过去除掩模图案MP所暴露的部分的结果,可以形成第一种子层125。第一种子层125可以介于第一导电线图案121与第一绝缘层111a之间,介于第一导电通孔图案123与和第一绝缘层111a的内侧壁之间,以及介于导电通孔图案123与下电极焊盘150之间。
与形成参照图5A至图5E示出的第一重新分布图案120的方法相同或相似的方法可以用于形成图4E中的第二重新分布图案130和图4E中的第三重新分布图案140中的每一个。
图6是示出根据本发明构思的一些实施例的半导体封装10a的截面图。除了半导体封装10a包括多个半导体芯片200a之外,图6所示的半导体封装10a可以与参考图1和图2描述的半导体封装10基本相同或相似。
参照图6,半导体封装10a可以包括重新分布结构100和在重新分布结构100上的多个半导体芯片200a。多个半导体芯片200a可以包括彼此间隔开的第一半导体芯片201和第二半导体芯片203。第一半导体芯片201可以包括半导体衬底211和芯片焊盘221,并且第一半导体芯片201的芯片焊盘221可以通过芯片连接端子230电连接到第三重新分布图案140。第二半导体芯片203可以包括半导体衬底213和芯片焊盘223,并且第二半导体芯片203的芯片焊盘223可以通过芯片连接端子230电连接到第三重新分布图案140。
在示例实施例中,第一半导体芯片201和第二半导体芯片203可以包括不同类型的半导体芯片。例如,当第一半导体芯片201是非存储器芯片时,第二半导体芯片203可以是存储器芯片。例如,第一半导体芯片201可以包括逻辑芯片。第一半导体芯片201可以包括例如中央处理单元(CPU)芯片、图形处理单元(GPU)芯片或应用处理器(AP)芯片。在一些实施例中,第二半导体芯片203可以包括例如动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、闪存芯片、电可擦除可编程只读存储器(EPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片或者电阻性随机存取存储器(RRAM)芯片。在一些实施例中,第二半导体芯片203可以包括高带宽存储器(HBM)DRAM半导体芯片。替代地,在示例实施例中,第一半导体芯片201和第二半导体芯片203可以包括相同类型的半导体芯片。在示例实施例中,半导体封装10a可以包括系统级封装(SIP),其中不同种类的半导体芯片彼此电连接以作为一个系统操作。
在这种情况下,由多个半导体芯片200a占据的占地面积可以小于重新分布结构100的水平区域。多个半导体芯片200a占据的占地面积可以在竖直方向上与重新分布结构100完全重叠。例如,在平面图中,多个半导体芯片200a的面积可以小于重新分布结构100的面积。在某些实施例中,多个半导体芯片200a可以竖直堆叠从而形成堆叠芯片。
图7是示出根据本发明构思的实施例的半导体封装10b的截面图。
参照图7,半导体封装10b可以包括下部封装11L和在下部封装11L上的上部封装11U。半导体封装10b可以包括封装上封装(POP)形式的半导体封装,其中上封装11U附接到下封装11L。
下封装11L可以包括第一重新分布结构100L、第一半导体芯片200L、第一下电极焊盘150L、第一芯片连接端子230L、第一底部填充材料层240L、第一模制层300L和第一导电柱160,该第一重新分布结构100L包括重新分布绝缘层110L、和重新分布图案120L、130L和140L。下封装11L的第一重新分布结构100L、第一半导体芯片200L、第一下电极焊盘150L、第一芯片连接端子230L、第一底部填充材料层240L和第一模制层300L可以分别与以上参考图1和图2描述的半导体封装10的重新分布结构100、半导体芯片200、下电极焊盘150、芯片连接端子230、底部填充材料层240和模制层300基本相同或相似。
第一导电柱160可以穿透第一模制层300L。第一重新分布结构100L的第三导电线图案140L的一部分可以连接到第一模制层300L的下端。第一模制层300L的上端可以连接到封装间连接端子410。第一重新分布结构100L的第三导电线图案140L可以接触和/或电连接到第一导电柱160的下端。第一导电柱160的上端可以接触和/或电连接到封装间连接端子410。
上封装11U可以包括第二重新分布结构100U、第二半导体芯片200U、第二下电极焊盘150U、第二芯片连接端子230U、第二底部填充材料层240U和第二模制层300U,该第二重新分布结构100U包括第二重新分布绝缘层110U和第二重新分布图案120U和140U。上封装11U的第二重新分布结构100U、第二半导体芯片200U、第二下电极焊盘150U、第二芯片连接端子230U、第二底部填充材料层240U和第二模制层300U可以分别与以上参考图1和图2描述的半导体封装10的重新分布结构100、半导体芯片200、下电极焊盘150、芯片连接端子230、底部填充材料层240和模制层300基本相同或相似。
通过介于上封装11U和下封装11L之间的封装间连接端子410,上封装11U可以电连接并物理连接到下封装11L。封装间连接端子410可以接触上封装11U的第二下电极焊盘150U的底表面,并且可以接触下封装11L的第一导电柱160。
在示例实施例中,类似于参考图1和图2描述的下电极焊盘150,上封装11U的第二下电极焊盘150U的一部分可以从第二重新分布绝缘层110U突出。例如,第二下电极焊盘150U的嵌入第二重新分布绝缘层110U中的部分的厚度可以大于第二下电极焊盘150U的从第二重新分布绝缘层110U突出的另一部分的厚度。
在示例实施例中,第一半导体芯片200L和第二半导体芯片200U可以包括不同类型的半导体芯片。备选地,在其他示例实施例中,第一半导体芯片200L和第二半导体芯片200U可以包括相同类型的半导体芯片。
第二半导体芯片200U可以经由以下组件电连接到第一半导体芯片200L和/或外部:包括在第二重新分布结构100U中的多个导电线图案121U和141U和多个导电通孔图案123U和143U;第二下电极焊盘150U;封装间连接端子410;第一导电柱160;以及第一重新分布结构100L中包括的多个导电线图案121L、131L和141L和多个导电通孔图案123L、133L和143L。
尽管已经参照本发明构思的实施例具体示出并描述了本发明构思,但是将会理解,在不脱离所附权利要求书的精神和范围的情况下,可以在其中进行形式和细节上的各种变化。
Claims (25)
1.一种半导体封装,包括:
重新分布结构,包括重新分布绝缘层和重新分布图案;
第一半导体芯片,设置在所述重新分布绝缘层的第一表面上并电连接到所述重新分布图案;以及
下电极焊盘,设置在所述重新分布绝缘层的与所述第一表面相对的第二表面上,所述下电极焊盘包括嵌入在所述重新分布绝缘层中的第一部分和从所述重新分布绝缘层的第二表面突出的第二部分,
其中,所述下电极焊盘的第一部分的厚度大于所述下电极焊盘的第二部分的厚度。
2.根据权利要求1所述的半导体封装,
其中,所述下电极焊盘的第二部分的厚度在所述下电极焊盘的总厚度的约10%和约30%之间。
3.根据权利要求1所述的半导体封装,
其中,所述下电极焊盘的第二部分的侧壁暴露于所述重新分布绝缘层的外部。
4.根据权利要求1所述的半导体封装,
其中,所述重新分布结构还包括:导电通孔图案,通过所述重新分布绝缘层的一部分电连接到所述下电极焊盘。
5.根据权利要求4所述的半导体封装,
其中,所述导电通孔图案的宽度在第一方向上逐渐变窄,其中所述第一方向从所述重新分布绝缘层的第一表面指向第二表面。
6.根据权利要求4所述的半导体封装,
其中,所述重新分布结构还包括:种子层,围绕所述导电通孔图案的侧壁,并且设置在所述导电通孔图案与所述下电极焊盘之间。
7.根据权利要求1所述的半导体封装,
其中,所述第一半导体芯片包括:芯片焊盘,设置在与所述重新分布绝缘层的第一表面面对的表面上,并且
所述半导体封装还包括:芯片连接端子,设置在所述重新分布绝缘层的第一表面上的所述重新分布图案的一部分与所述第一半导体芯片的芯片焊盘之间。
8.根据权利要求7所述的半导体封装,
还包括:底部填充材料层,设置在所述第一半导体芯片与所述重新分布绝缘层的第一表面之间,并且围绕所述芯片连接端子。
9.根据权利要求1所述的半导体封装,
还包括在所述下电极焊盘的底表面上的外部连接端子。
10.根据权利要求9所述的半导体封装,
其中,所述下电极焊盘的底表面是平坦的。
11.根据权利要求1所述的半导体封装,还包括:
模制层,覆盖所述第一半导体芯片的侧表面;以及
导电柱,穿透所述模制层并电连接到所述重新分布图案。
12.根据权利要求1所述的半导体封装,还包括:
第二半导体芯片,与所述第一半导体芯片间隔开,
其中,所述第一半导体芯片是逻辑芯片,并且所述第二半导体芯片是存储器芯片。
13.一种半导体封装,包括:
重新分布绝缘层,包括彼此相对的第一表面和第二表面;
第一导电线图案,在所述重新分布绝缘层中;
第二导电线图案,在所述重新分布绝缘层的第一表面上;
下电极焊盘,包括嵌入在所述重新分布绝缘层中的第一部分、和从所述重新分布绝缘层的第二表面突出的第二部分;
第一导电通孔图案,在所述第一导电线图案与所述下电极焊盘之间延伸,并且与所述下电极焊盘接触;
第二导电通孔图案,在所述第二导电线图案与所述第一导电线图案之间延伸;以及
半导体芯片,设置在所述重新分布绝缘层上,并且电连接到所述第二导电线图案。
14.根据权利要求13所述的半导体封装,
其中,所述下电极焊盘的第二部分的厚度在约1μm和约3μm之间。
15.根据权利要求13所述的半导体封装,
其中,所述第一导电通孔图案和所述第二导电通孔图案的宽度各自在第一方向上逐渐变窄,其中,所述第一方向从所述重新分布绝缘层的第一表面朝向所述重新分布绝缘层的第二表面。
16.根据权利要求13所述的半导体封装,
其中,所述下电极焊盘的第二部分的侧壁暴露于所述重新分布绝缘层的外部,并且
所述下电极焊盘的第一部分的侧壁的高度大于所述下电极焊盘的第二部分的侧壁的高度。
17.根据权利要求13所述的半导体封装,还包括:
第一种子层,围绕所述第一导电通孔图案的侧壁,并且设置在所述第一导电通孔图案与所述下电极焊盘之间;以及
第二种子层,围绕所述第二导电通孔图案的侧壁,并且设置在所述第二导电通孔图案与所述第一导电通孔图案之间。
18.根据权利要求13所述的半导体封装,还包括:
芯片连接端子,设置在所述第二导电线图案与所述半导体芯片之间;以及
底部填充材料层,设置在所述半导体芯片与所述重新分布绝缘层的第一表面之间,并且围绕所述芯片连接端子。
19.根据权利要求13所述的半导体封装,还包括:
外部连接端子,在所述下电极焊盘的第二部分的底表面上,
其中,所述下电极焊盘的第二部分的底表面是平坦的。
20.一种半导体封装,包括:
重新分布结构,包括多个绝缘层、设置在所述多个绝缘层中的每一个绝缘层的上表面上的多个导电线图案、以及多个导电通孔图案,所述多个导电通孔图案穿透所述多个绝缘层中的至少一个并连接到所述多个导电线图案中的至少一个;
半导体芯片,在所述重新分布结构的上表面上;
芯片连接端子,介于所述半导体芯片与所述多个导电线图案中的最上层的导电线图案之间;
底部填充材料层,在所述半导体芯片与所述重新分布结构之间围绕芯片连接端子;
模制层,覆盖所述半导体芯片的至少一部分;
下电极焊盘,在所述重新分布结构的底表面上;以及
外部连接端子,在所述下电极焊盘上,
其中,所述下电极焊盘包括嵌入在所述多个绝缘层中的最下绝缘层中的第一部分、和从所述最下绝缘层突出的第二部分,并且所述下电极焊盘的第二部分的厚度小于所述下电极焊盘的第一部分的厚度。
21.根据权利要求20所述的半导体封装,
其中,所述多个导电通孔图案各自具有以下形状:在从所述重新分布结构的上表面朝向所述重新分布结构的下表面的方向上逐渐变窄。
22.根据权利要求20所述的半导体封装,
其中,所述多个导电通孔图案的一部分与所述下电极焊盘接触。
23.根据权利要求20所述的半导体封装,
其中,所述重新分布结构包括:
多个种子层,设置在所述多个绝缘层中的每一个的上表面与所述多个导电线图案之间,并且在所述多个绝缘层中的每一个与所述多个导电通孔图案之间。
24.根据权利要求20所述的半导体封装,
其中,所述下电极焊盘具有均匀的厚度,并且所述下电极焊盘的第二部分的侧壁暴露于最下绝缘层的外部。
25.根据权利要求20所述的半导体封装,还包括:多个下电极焊盘,
其中,在平面图中,所述多个下电极焊盘中的至少一个与所述半导体芯片的侧表面向外间隔开。
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