TWI759413B - Semiconductor device, wafer-like semiconductor element, electronic apparatus including semiconductor device, and manufacturing method of semiconductor device - Google Patents

Semiconductor device, wafer-like semiconductor element, electronic apparatus including semiconductor device, and manufacturing method of semiconductor device Download PDF

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Publication number
TWI759413B
TWI759413B TW107103153A TW107103153A TWI759413B TW I759413 B TWI759413 B TW I759413B TW 107103153 A TW107103153 A TW 107103153A TW 107103153 A TW107103153 A TW 107103153A TW I759413 B TWI759413 B TW I759413B
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Taiwan
Prior art keywords
wafer
protrusions
semiconductor element
wiring board
semiconductor device
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TW107103153A
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Chinese (zh)
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TW201832335A (en
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梅澤讓
恆見大樹
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日商索尼半導體解決方案公司
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Publication of TW201832335A publication Critical patent/TW201832335A/en
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract

本發明之半導體裝置包含配線基板、及覆晶安裝於配線基板上之晶片狀半導體元件，在與配線基板對向之側之晶片狀半導體元件之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物，晶片狀半導體元件藉由在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料塗佈於配線基板上之狀態下，在配置為經由底部填充材料與配線基板對向後實施回焊處理，而覆晶安裝於配線基板上。The semiconductor device of the present invention includes a wiring board and a chip-like semiconductor element flip-chip mounted on the wiring board, a plurality of solder bumps are provided on the surface of the chip-like semiconductor element on the side facing the wiring board, and insulating A plurality of protrusions of the material, the wafer-like semiconductor element is arranged so as to be aligned with the wiring substrate through the underfill material in a state where the underfill material having the property of decreasing the viscosity as the temperature rises is applied on the wiring substrate. A reflow process is performed backward, and the flip chip is mounted on the wiring board.

Description

半導體裝置、晶片狀半導體元件、包含半導體裝置之電子機器、及半導體裝置之製造方法Semiconductor device, wafer-like semiconductor element, electronic apparatus including semiconductor device, and manufacturing method of semiconductor device

本發明係關於一種半導體裝置、晶片狀半導體元件、包含半導體裝置之電子機器、及半導體裝置之製造方法。The present invention relates to a semiconductor device, a wafer-like semiconductor element, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device.

伴隨著電子機器之小型化及薄型化，針對包含晶片狀半導體元件之封裝體亦要求小型薄型化及多端子化。因而，業界提出使用焊料凸塊等將晶片狀半導體元件(以下有簡單地稱為晶片之情形)接合於中介層基板等之配線基板的覆晶安裝方式。 針對使用所謂之毛細管底部填充方式之安裝方式進行說明，該毛細管底部填充方式首先將晶片與配線基板設為電性接合之狀態，其次在晶片之周邊部塗佈液狀之底部填充材料並利用毛細管現象使底部填充材料滲透配線基板與晶片之間隙。在圖28A中顯示該安裝方式之基本的步驟。 當在晶片與配線基板之間進行焊接時，為了去除金屬表面之氧化膜而而必須實施助銲劑處理。然而，若殘存助銲劑，則成為在底部填充密封步驟中可靠性降低之原因。因而，在將晶片與配線基板接合後，實施用於去除殘留助銲劑之洗淨處理。其次，在晶片之周邊部塗佈液狀之底部填充材料，利用毛細管現象使底部填充材料滲透配線基板與晶片之間隙。而且，之後，對底部填充材料實施固化處理使其固化而進行密封。例如在日本特開2007-324418號公報與日本特開2008-270257號公報中揭示有以防止電極間之短路、及提高毛細管底部填充方式之底部填充材料之流動性等為目的，而在晶片形成與電極與不同之突起物。 在毛細管底部填充方式中，利用毛細管現象使底部填充材料滲透配線基板與晶片之間隙。因而，當縮小間隙，或使配線基板與晶片之接合部之窄節距化時，因助銲劑等之殘渣而底部填充材料之潤濕性惡化，而妨礙底部填充材料之滲透。因而，在使用毛細管底部填充方式之密封之情形下，窄節距化有其界限。又，因毛細管底部填充方式之密封步驟需要較長時間且亦需要助銲劑之洗淨之步驟等，故在使用毛細管底部填充方式之安裝方式中有難以謀求藉由縮短生產步驟之節拍時間帶來之生產效率之提高的課題。 因而，例如在日本特開2002-203874號公報中揭示有先塗佈底部填充材料方式之安裝方式，該先塗佈底部填充材料方式之安裝方式先塗佈底部填充材料，其次將晶片與配線基板設為電性接合之狀態。在圖28B中顯示該安裝方式之基本的步驟。 先塗佈底部填充材料方式具備以下優點，即：無須殘留助銲劑之洗淨步驟，即便縮小配線基板與晶片之間隙或謀求配線基板與晶片之接合部之窄節距化仍能夠進行密封。 [先前技術文獻] [專利文獻] [專利文獻1]日本特開2007-324418號公報 [專利文獻2]日本特開2008-270257號公報 [專利文獻3]日本特開2002-203874號公報Along with the miniaturization and thinning of electronic equipment, the package including chip-shaped semiconductor elements is also required to be reduced in size and thickness and multi-terminal. Therefore, the industry has proposed a flip-chip mounting method in which a wafer-shaped semiconductor element (hereinafter referred to simply as a wafer) is bonded to a wiring substrate such as an interposer substrate using solder bumps or the like. A description will be given of a mounting method using a so-called capillary underfill method. First, the chip and the wiring board are electrically connected to each other, and then a liquid underfill material is applied to the periphery of the wafer and the capillary is used. The phenomenon causes the underfill material to penetrate the gap between the wiring substrate and the chip. The basic steps of this installation are shown in FIG. 28A. When soldering between a chip and a wiring board, it is necessary to perform a flux treatment in order to remove the oxide film on the metal surface. However, if the flux remains, it becomes a cause of a decrease in reliability in the underfill sealing step. Therefore, after bonding the wafer and the wiring board, a cleaning process for removing the residual flux is performed. Next, a liquid underfill material is applied to the peripheral portion of the wafer, and the underfill material penetrates the gap between the wiring board and the wafer by utilizing the capillary phenomenon. Then, the underfill material is subjected to curing treatment to be cured and sealed. For example, Japanese Patent Laid-Open No. 2007-324418 and Japanese Patent Laid-Open No. 2008-270257 disclose that, for the purpose of preventing a short circuit between electrodes and improving the fluidity of an underfill material of a capillary underfill method, the formation of Different protrusions from electrodes. In the capillary underfill method, the capillary phenomenon is used to make the underfill material penetrate the gap between the wiring substrate and the wafer. Therefore, when the gap is narrowed or the pitch of the bonding portion between the wiring board and the chip is narrowed, the wettability of the underfill material is deteriorated by the residues of flux or the like, and the penetration of the underfill material is hindered. Therefore, in the case of sealing using the capillary underfill method, the narrowing of the pitch has its limits. In addition, since the sealing step of the capillary underfill method takes a long time and also requires the step of cleaning the flux, etc., it is difficult to achieve the result of shortening the takt time of the production step in the installation method using the capillary underfill method. The subject of improving production efficiency. Therefore, for example, Japanese Patent Laid-Open No. 2002-203874 discloses a mounting method in which the underfill material is applied first, and the underfill material is applied first in the mounting method. Set to the state of electrical connection. The basic steps of this installation are shown in FIG. 28B. The method of applying the underfill material first has the following advantages, that is, without the cleaning step of residual flux, sealing can be performed even if the gap between the wiring board and the chip is narrowed or the pitch between the wiring board and the chip is narrowed. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open No. 2007-324418 [Patent Document 2] Japanese Patent Laid-Open No. 2008-270257 [Patent Document 3] Japanese Patent Laid-Open No. 2002-203874

[發明所欲解決之問題] 在上述之專利文獻3所揭示之技術中必須在成為進行完底部填充材料之選擇性塗佈、及在配線基板與晶片之間實現高精度之定位之狀態後，在加熱下加壓而安裝晶片。然而，基於生產效率提高之觀點，較佳的是，能夠在無須底部填充材料之選擇性塗佈及高精度之定位下進行晶片安裝。 又，在先塗佈底部填充材料方式中，在晶片安裝步驟中，因助銲劑功能之還原作用等所致之空隙容易殘留在底部填充材料中。然而，在上述之專利文獻3所揭示之技術中，除因底部填充材料之黏度之降低引起之效果外，未言及在晶片安裝時如何使殘留於底部填充材料中之空隙釋放至外部。 因而，本發明之目的在於提供一種能夠在無須底部填充材料之選擇性塗佈及高精度之定位下，進一步較小晶片安裝時之底部填充材料之空隙的半導體裝置、包含上述半導體裝置之電子機器、用於上述半導體裝置之晶片狀半導體元件、及上述半導體裝置之製造方法。 [解決問題之技術手段] 為了達成上述之目的，本發明之第1態樣之半導體裝置具備： 配線基板； 晶片狀半導體元件，其覆晶安裝於配線基板上；且 在與配線基板對向之側之晶片狀半導體元件之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物； 晶片狀半導體元件藉由在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料塗佈於配線基板上之狀態下在配置為經由底部填充材料與配線基板對向後實施回流處理，而覆晶安裝於配線基板上。 用於達成上述之目的之本發明之第1態樣之晶片狀半導體元件係覆晶安裝於塗佈有底部填充材料之配線基板上者，且 在與配線基板對向之側之晶片狀半導體元件之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物。 用於達成上述之目的之本發明之第1態樣之電子機器係包含含有配線基板、及覆晶安裝於配線基板上之晶片狀半導體元件的半導體裝置者；且 在與配線基板對向之側之晶片狀半導體元件之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物； 晶片狀半導體元件藉由在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料塗佈於配線基板上之狀態下在配置為經由底部填充材料與配線基板對向後實施回流處理，而覆晶安裝於配線基板上。 用於達成上述之目的之本發明之第1態樣之半導體裝置之製造方法包含以下步驟： 藉由將在與配線基板對向之側之面設置有複數個焊料凸塊及包含絕緣性材料之複數個突起物之晶片狀半導體元件在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料塗佈於配線基板上之狀態下在配置為經由底部填充材料與配線基板後實施回流處理，而將前述晶片狀半導體元件覆晶安裝於配線基板上。 [發明之效果] 用於本發明之半導體裝置之晶片狀半導體元件在與配線基板對向之側之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物。而且，晶片狀半導體元件藉由在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料塗佈於配線基板上之狀態下在配置為經由底部填充材料與配線基板對向後實施回流處理，而被安裝。由於可在無須對各個晶片之加熱加壓製程下進行自對準之位置修正，故能夠在無須底部填充材料之選擇性塗佈及高精度之定位下進行晶片安裝。又，由於在回流處理時，晶片狀半導體元件之突起物間之間隙成為氣體之流路，故能夠減小晶片安裝時之底部填充材料之空隙。[Problems to be Solved by the Invention] In the technique disclosed in the above-mentioned Patent Document 3, it is necessary to achieve a state in which the selective coating of the underfill material and the high-precision positioning between the wiring board and the wafer are completed. The wafer is mounted under heat and pressure. However, from the viewpoint of improving the production efficiency, it is preferable that the wafer mounting can be performed without selective coating of the underfill material and high-precision positioning. In addition, in the method of applying the underfill material first, in the chip mounting step, voids due to the reduction action of the flux function and the like tend to remain in the underfill material. However, in the technique disclosed in the above-mentioned Patent Document 3, other than the effect due to the reduction in the viscosity of the underfill material, there is no mention of how to release the voids remaining in the underfill material to the outside at the time of chip mounting. Therefore, the object of the present invention is to provide a semiconductor device that can further reduce the gap of the underfill material during chip mounting without the need for selective coating of the underfill material and high-precision positioning, and an electronic apparatus including the above-mentioned semiconductor device. , A wafer-like semiconductor element used in the above-mentioned semiconductor device, and a method of manufacturing the above-mentioned semiconductor device. [Technical Means for Solving the Problem] In order to achieve the above-mentioned object, the semiconductor device according to the first aspect of the present invention includes: a wiring board; a wafer-like semiconductor element flip-chip mounted on the wiring board; A plurality of solder bumps and a plurality of protrusions including insulating materials are arranged on the surface of the chip-shaped semiconductor element on the side; the wafer-shaped semiconductor element is coated with an underfill material having the property of decreasing the viscosity as the temperature rises. In the state of being arranged on the wiring board, the reflow process is performed so as to be opposed to the wiring board via the underfill material, and the flip chip is mounted on the wiring board. The chip-like semiconductor element of the first aspect of the present invention for achieving the above-mentioned object is flip-chip mounted on a wiring substrate coated with an underfill material, and the chip-like semiconductor element on the side opposite to the wiring substrate The surface is provided with a plurality of solder bumps and a plurality of protrusions including insulating materials. The electronic apparatus of the first aspect of the present invention for achieving the above-mentioned object includes a semiconductor device including a wiring board and a chip-like semiconductor element flip-chip mounted on the wiring board; and on the side facing the wiring board The surface of the chip-shaped semiconductor element is provided with a plurality of solder bumps and a plurality of protrusions including an insulating material; the wafer-shaped semiconductor element is coated with an underfill material having the property of decreasing the viscosity as the temperature rises In the state on the wiring board, a reflow process is performed after being disposed so as to be opposed to the wiring board through the underfill material, and the flip chip is mounted on the wiring board. The manufacturing method of the semiconductor device of the first aspect of the present invention for achieving the above-mentioned object includes the following steps. The wafer-like semiconductor element with a plurality of protrusions is arranged to pass through the underfill material and the wiring board and then subjected to reflow treatment in a state where an underfill material having a property of decreasing the viscosity as the temperature rises is applied on the wiring board. The wafer-like semiconductor element is flip-chip mounted on a wiring board. [Effect of the Invention] The wafer-like semiconductor element used in the semiconductor device of the present invention is provided with a plurality of solder bumps and a plurality of protrusions including an insulating material on the surface facing the wiring board. In addition, the wafer-like semiconductor element is arranged to face the wiring substrate via the underfill material and then subjected to reflow treatment in a state where the underfill material having the property of decreasing the viscosity as the temperature rises is applied on the wiring substrate. is installed. Since the self-aligned position correction can be performed without the heating and pressing process of each wafer, the chip mounting can be performed without the selective coating of the underfill material and the high-precision positioning. In addition, during the reflow process, the gaps between the protrusions of the wafer-like semiconductor element serve as gas flow paths, so that the gaps of the underfill material at the time of wafer mounting can be reduced.

以下，參照圖式，基於實施形態說明本發明。本發明並不限定於實施形態，實施形態之各種數值及材料係例示。在以下之說明中，對於相同要件或具有相同功能之要件使用相同符號，且省略重複之說明。此外，說明係按照以下之順序進行。 1.關於本發明之半導體裝置、晶片狀半導體元件、包含半導體裝置之電子機器、及半導體裝置之製造方法之總體之說明 2.第1實施形態 3.第2實施形態 4.第3實施形態 5.第4實施形態 6.第5實施形態 7.第6實施形態 8.第7實施形態 9.第8實施形態 10.第9實施形態 11.第10實施形態 12.第11實施形態 13.第12實施形態 14.其他 ［關於本發明之半導體裝置、晶片狀半導體元件、包含半導體裝置之電子機器、及半導體裝置之製造方法之總體之說明］ 在本發明之半導體裝置、用於本發明之電子機器之半導體裝置、及利用本發明之半導體裝置之製造方法製造之半導體裝置(以下有將其等簡單地稱為本發明之半導體裝置之情形)中，晶片狀半導體元件可採用具有突起物之構成，該突起物形成為在晶片狀半導體元件被覆晶安裝之狀態下前端不到達配線基板。 在包含上述之較佳之構成之本發明之半導體裝置中可採用以下構成，即：晶片狀半導體元件藉由設置於配線基板之焊料凸塊與設置於晶片狀半導體元件之焊料凸塊利用回流處理融合，而在相對於配線基板已定位之狀態下被安裝。 在包含上述之各種較佳之構成之本發明之半導體裝置中，底部填充材料可被選擇性地塗佈於配線基板上，亦可批量塗佈。基於提高生產效率之觀點，較佳的是採用批量塗佈於配線基板上之構成。 在包含上述之各種較佳之構成之本發明之半導體裝置中，較佳的是，底部填充材料係具有助銲劑功能者。根據該構成，由於去除與底部填充材料相接之金屬表面之酸化物，故能夠良好地進行回流處理之焊料凸塊之融合。 如上述般，本發明之晶片狀半導體元件係覆晶安裝於塗佈有底部填充材料之配線基板上之晶片狀半導體元件。在與配線基板對向之側之晶片狀半導體元件之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物。而且，可採用具有突起物之構成，該突起物形成為在晶片狀半導體元件被覆晶安裝之狀態下前端不到達配線基板。 本發明之晶片狀半導體元件、及用於本發明之半導體晶片之晶片狀半導體元件(以下有將其等簡單地稱為本發明之晶片狀半導體元件之情形)可為具有較設置於晶片狀半導體元件之焊料凸塊形成為更高之突起物之構成，亦可為具有與焊料凸塊形成為相同高度之突起物之構成，還可為具有較焊料凸塊形成為更低之突起物之構成。 在包含上述之各種較佳之構成之本發明之晶片狀半導體元件中， 可採用在晶片狀半導體元件之面之供配置突起物之區域以一定之密度設置有突起物之構成。 或，還可採用在晶片狀半導體元件之面之供配置突起物之區域以相應於區域內之位置而不同之密度設置有突起物之構成。 在此情形下，可採用相鄰之突起物間之間隙設置為橫穿供配置突起物之區域之構成。或，還可採用晶片狀半導體元件之面之中央區域之突起物之密度高於包圍中央區域之周邊區域之突起物之密度之構成。 在包含上述之各種較佳之構成之本發明之晶片狀半導體元件中，可採用在晶片狀半導體元件之面設置有相同形狀之突起物之構成。 或，還可採用在晶片狀半導體元件之面設置有形狀不同之複數種突起物之構成。在此情形下，可採用設置有高度不同之複數種突起物之構成。 在包含上述之各種較佳之構成之本發明之晶片狀半導體元件中，突起物可採用形成為越遠離晶片狀半導體元件之面則形狀越變小之構成。例如，突起物可設為以晶片狀半導體元件之面側為底面，越遠離晶片狀半導體元件之面則剖面形狀越變小之截頭錐之形狀。在包含上述之各種較佳之構成之本發明之晶片狀半導體元件中，突起物可為對稱形狀，亦可為非對稱形狀。 包含上述之各種較佳之構成之本發明之半導體裝置、晶片狀半導體元件、包含半導體裝置之電子機器、及半導體裝置之製造方法(以下有將其等簡單地稱為本發明之情形)所使用之配線基板之形狀及構成只要不對本發明之實施產生障礙則無特別限定。例如，可為在1個配線基板上安裝1個晶片狀半導體元件之構成，亦可為在1個配線基板上安裝複數個晶片狀半導體元件之構成。又，可為配置有晶片狀半導體元件及表面安裝零件之構成。 設置於本發明之晶片狀半導體元件之突起物可使用例如PI系、酚系、PBO系、BCB系、及丙烯酸系等之感光性樹脂，利用曝光等之光微影術而形成。或，還可使用聚醯胺系、及ABS系等之樹脂，利用3D打印技術而形成。再者，還可使用玻璃系之材料，利用蝕刻技術而形成。 在配線基板上塗佈底部填充材料之方法只要不對本發明之實施產生障礙則無特別限定。例如，可以旋轉塗佈法、噴塗法、及印刷法等之各種印刷法塗佈。 構成本發明所使用之底部填充材料之材料只要不對本發明之實施產生障礙則無特別限定。具體而言，只要係在回流處理時黏度降低至不有損自對準之程度且在回流處理後能夠進行固化處理之材料即可。可例示例如環氧系之材料來作為構成底部填充材料之材料。例如，熱固化性之底部填充材料藉由固化劑因長時間之加熱發生反應而固化。回流時之加熱時間短，而固化反應輕微，且溫度上升，而黏度降低。 除嚴密地成立之情形外，在實質上成立之情形下亦滿足本說明書之各種之條件。容許存在設計上或製造上產生之各種偏差。且，以下之說明中使用之各圖式係示意性圖式，不表示實際之寸法及其比例。 ［第1實施形態］ 第1實施形態關於本發明之第1態樣之半導體裝置、晶片狀半導體元件、及半導體裝置之製造方法。 圖1係用於說明本發明之第1態樣之半導體裝置之示意性分解立體圖。 此外，為了方便圖示及說明，在圖1中將晶片狀半導體元件10及設置於配線基板20等之電極及突起物等誇張性表示。又，雖然為了方便說明，而說明在1個配線基板上安裝有1個晶片狀半導體元件，但本發明並不限定於此。 半導體裝置1具備：配線基板20、及覆晶安裝於配線基板20上之晶片狀半導體元件10。在與配線基板20對向之側之晶片狀半導體元件10之面，設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物。 晶片狀半導體元件10藉由在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料22塗佈於配線基板20上之狀態下，在配置為經由底部填充材料22與配線基板20對向後實施回焊處理，而覆晶安裝於配線基板20上。 晶片狀半導體元件10具有突起物，該突起物形成為在晶片狀半導體元件10被覆晶安裝之狀態下前端不到達配線基板20。而且，晶片狀半導體元件10藉由將設置於配線基板20之焊料凸塊、與設置於晶片狀半導體元件10之焊料凸塊，利用回焊處理融合，而在相對於配線基板20已定位之狀態下被安裝。 就半導體裝置1之基本的製造步驟進行說明。 圖2係用於說明本發明之第1態樣之半導體裝置之基本的製造步驟之步驟圖。 如圖2所示，底部填充材料22被批量塗佈於配線基板20上(例如參照後述之圖5)。晶片狀半導體元件10配置為經由底部填充材料22與配線基板20對向。此外，此時，晶片狀半導體元件10只要以自對準有效之程度之精度配置即足夠。亦即，無須以配線基板20之電極與晶片狀半導體元件10之電極正確地對向之方式高精度地定位。其次，進行批量回流處理。參照後述之圖6及圖7於後文詳細地說明，在回流處理時產生焊接之自對準，晶片狀半導體元件10在相對於配線基板20已定位之狀態下被安裝。之後，對底部填充材料22進行固化處理，而半導體裝置1完成。 如上述般，在與配線基板20對向之側之晶片狀半導體元件10之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物。針對覆晶安裝前之晶片狀半導體元件10詳細地說明。 圖3A及圖3B係用於說明晶片狀半導體元件10之電極與突起物之配置之示意性立體圖。圖3A顯示突起物形成前之狀態，圖3B顯示突起物形成後之狀態。 在圖所示之例中，沿矩形狀之晶片狀半導體元件10之各邊以特定之間隔設置有焊料凸塊11(參照圖3A)。相對於該狀態之晶片狀半導體元件10，使用例如光微影術，在焊料凸塊11所包圍之區域之內側形成包含絕緣性材料之複數個突起物12(參照圖3B)。 在圖所示之例中，突起物12形成為越遠離晶片狀半導體元件10之面則形狀越變小，且係對稱形狀。突起物12具有利用毛細管現象將先塗佈於配線基板20之底部填充材料22抽吸並填充至晶片狀半導體元件側之功能。突起物12較焊料凸塊11形成為更高。 其次，針對覆晶安裝前之配線基板20進行說明。 圖4係用於說明配線基板之電極配置之示意性立體圖。圖5係用於說明配線基板之電極與先塗佈底部填充材料層之配置之示意性立體圖。 以符號20A表示在配線基板20中與晶片狀半導體元件10對向之部分。此外，在以下之說明中，有將以符號20A表示之部分簡單地稱為對向部20A之情形。對向部20A係大致矩形，沿各邊以與晶片狀半導體元件10對應之方式形成有焊料凸塊21(參照圖4)。相對於該狀態之配線基板20批量塗佈有底部填充材料22(參照圖5)。 以上，針對半導體裝置1之概要進行了說明。接著，參照圖，針對半導體裝置1之製造方法詳細地說明。 本發明之半導體裝置之製造方法包含以下步驟： 藉由將在與配線基板20對向之側之面設置有複數個焊料凸塊11及包含絕緣性材料之複數個突起物12之晶片狀半導體元件10在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料22塗佈於配線基板20上之狀態下在配置為經由底部填充材料22與配線基板20對向後實施回流處理，而將前述晶片狀半導體元件10覆晶安裝於配線基板20上。 圖6A至圖6E係用於說明半導體裝置之製造步驟之示意性部分剖視圖。圖7A至圖7C係接續圖6E用於說明半導體裝置之製造步驟之示意性部分剖視圖。為了方便圖示，而在該等圖中配線基板僅圖示對向部20A之部分。又，各構成要件之形狀等簡略化地顯示。 ［步驟-100］(參照圖6A及圖6B) 準備晶片狀半導體元件10，在其上形成成為電極之焊料凸塊11(參照圖6A)。其次，使用例如光微影術，在焊料凸塊11所包圍之區域之內側形成包含絕緣性材料之複數個突起物12(參照圖6B)。 ［步驟-110］(參照圖6C及圖6D) 準備配線基板20，在對向部20A上形成成為電極之焊料凸塊21(參照圖6C)。其次，在包含對向部20A上之整面上批量地塗佈底部填充材料22(參照圖6D)。 如上述般，底部填充材料22被批量塗佈於配線基板20上。無須相對於對向部20A選擇性地塗佈。又，在塗佈時使用具有助銲劑功能之底部填充材料22。 ［步驟-120］(參照圖6E) 之後，將晶片狀半導體元件10配置為經由底部填充材料22與配線基板20對向。 ［步驟-130］(參照圖7A及圖7B) 其次，進行回流處理。 若伴隨著溫度上升而底部填充材料22之黏度降低，則晶片狀半導體元件10之突起物12利用毛細管現象抽吸底部填充材料22(參照圖7A)。以符號22A表示流動狀態之底部填充材料。 繼而，晶片狀半導體元件10與配線基板20之焊料凸塊11、21融合並吸引彼此(參照圖7B)。藉此產生自對準，晶片狀半導體元件10成為相對於配線基板20已定位之狀態。因而，即便在［步驟-120］中在晶片狀半導體元件10之配置中殘留稍許之偏移，仍不對定位產生障礙。 又，由於因焊料凸塊11、21之融合而晶片狀半導體元件10進一步下沉，故促進晶片狀半導體元件10與配線基板20間之底部填充材料22A之填充。晶片狀半導體元件10之突起物間之間隙在底部填充材料22A之填充過程中成為氣體之流路。因而，能夠減小晶片安裝時之底部填充材料22之空隙。能夠利用突起物12之設計控制回流處理時之底部填充材料22A之抽吸量及到達高度。 若在底部填充材料22A之填充過程中突起物12之前端到達配線基板20，則有損因焊料凸塊11、21融合帶來之自對準效果。因而，突起物12形成為在晶片狀半導體元件10被覆晶安裝之狀態下前端不到達配線基板20。此外，在某些情況下，在不有損自對準效果之範圍內，可更包含前端到達配線基板20之間隙間隔設定用途等之突起物。 ［步驟-140］(參照圖7C) 其次，進行底部填充材料22A之固化處理。固化處理只要相應於底部填充材料之種類適宜地選擇較佳之方法即可。以符號22B表示固化後之底部填充材料。藉此，能夠獲得在配線基板20安裝有晶片狀半導體元件10而成之半導體裝置1。 本發明之製造方法係先塗佈底部填充材料之方法，與毛細管底部填充方式相比密封所需要之節拍時間為短。再者，在本發明之製造方法中，在晶片安裝時無須晶片個別之加壓加熱。而且，由於發揮焊接之自對準，故緩和配置晶片狀半導體元件時之定位之精度。因而，根據本發明之製造方法能夠將步驟簡單化，而能夠大幅地縮短節拍時間及前置時間。 此外，雖然在以上之說明中，突起物12較焊料凸塊11形成為更高，但並不限定於此。例如，可為突起物12與焊料凸塊11為相同高度、或突起物12低於焊料凸塊11的構成。在圖8中顯示使突起物12低於焊料凸塊11之情形之步驟圖。 圖8A係與圖6E對應之圖。由於突起物12低於焊料凸塊11，故焊料凸塊11較突起物12先與底部填充材料22接觸。 圖8B係與圖7A對應之圖，圖8C係與圖7B對應之圖。若因回流處理而底部填充材料22之黏度降低，則首先，通過焊料凸塊11抽吸樹脂(參照圖8B)，其次，亦利用突起部12抽吸樹脂(參照圖8C)。 圖8D係與圖7C對應之圖。藉由在回流處理後進行固化處理，而能夠獲得在配線基板20上安裝有晶片狀半導體元件10而成之半導體裝置1。 ［第2實施形態］ 第2實施形態關於本發明之第1態樣之晶片狀半導體元件。 圖9係用於說明第2實施形態之晶片狀半導體元件之構造之示意性平面圖。 第2實施形態之晶片狀半導體元件10之焊料凸塊11沿晶片狀半導體元件10之外周部之各邊連續地配置。而且，在晶片狀半導體元件10之面之供配置突起物之區域(更具體而言，由焊料凸塊包圍之區域)以一定之密度設置有突起物12。 在該構成中，在晶片狀半導體元件10之面，相同形狀之突起物12係相同地以同一節距配置。突起物12可使用光微影術而形成，前述光微影術例如在塗佈感光性之絕緣樹脂材料後使用描繪有所需圖案之光罩進行曝光，之後進行顯影處理。 ［第3實施形態］ 第3實施形態亦關於本發明之第1態樣之晶片狀半導體元件。在第2實施形態中，在供配置突起物之區域以一定之密度設置有突起物。相對於此，在第3實施形態中，以相應於區域內之位置而不同之密度設置有突起物。 圖10係用於說明第3實施形態之晶片狀半導體元件之構造之示意性平面圖。 在第3實施形態中亦然，焊料凸塊11係沿晶片狀半導體元件10之外周部之各邊連續地配置，在晶片狀半導體元件10之面之供配置突起物之區域設置有突起物12。 惟，在第3實施形態中，由焊料凸塊11包圍之區域被分割為複數個區塊。而且，在區塊與區塊之間設置有間隙13。在各區塊內，相同形狀之突起物12係相同地以相同節距配置。間隙13設定為寬於區塊內之突起物間之間隔。在該構造中，相鄰之突起物間之間隙13配置為橫穿供配置突起物之區域。由於該等間隙13成為晶片狀半導體元件10之安裝時之氣體之流路，故能夠有效地減小晶片狀半導體元件10之安裝時之底部填充材料之空隙。 ［第4實施形態］ 第4實施形態係第3實施形態之變化例。在第3實施形態中，在各區塊內，相同形狀之突起物係相同地以相同節距配置。相對於此，在第4實施形態中，設置有形狀不同之複數種突起物之點主要不同。 圖11係用於說明第4實施形態之晶片狀半導體元件之構造之示意性平面圖。 在第4實施形態亦然，焊料凸塊11係沿晶片狀半導體元件10之外周部之各邊連續地配置，在晶片狀半導體元件10之面之供配置突起物之區域設置有突起物。而且，由焊料凸塊11包圍之區域被分割為複數個區塊。而且，在區塊與區塊之間設置有間隙13。 在晶片狀半導體元件10之周邊附近之區塊配置有例如與圖10所示之突起物12相同之突起物12A。另一方面，在晶片狀半導體元件10之中央附近之區塊配置有更大徑之突起物12B。突起物12B亦形成為越遠離晶片狀半導體元件10之面則形狀越變小，且係對稱形狀。此外，突起物12A與突起物12B之高度可相同，亦可不同。 與第3實施形態相同地，間隙13設定為寬於區塊內之突起物間之間隔。與第3實施形態相同地，由於該等間隙13成為晶片狀半導體元件之安裝時之氣體之流路，故能夠有效地減小晶片狀半導體元件之安裝時之底部填充材料之空隙。 ［第5實施形態］ 第5實施形態亦關於本發明之第1態樣之晶片狀半導體元件。 圖12A及圖12B係用於說明第5實施形態之晶片狀半導體元件之構造之示意性平面圖，圖12A顯示電極之配置關係，圖12B顯示突起物之配置關係。圖13係用於說明第5實施形態之晶片狀半導體元件之構造之示意性平面圖，顯示電極與突起物之配置關係。 在第2實施形態至第4實施形態中，焊料凸塊係沿晶片狀半導體元件之外周部之各邊連續地配置。相對於此，在第5實施形態中，焊料凸塊11在晶片狀半導體元件10之面配置為矩陣狀。而且，在晶片狀半導體元件10之面之供配置突起物之區域(更具體而言，未配置有焊料凸塊之區域)，以將焊料凸塊之間填埋之方式配置有突起物。 在晶片狀半導體元件10之面之供配置突起物之區域以相應於區域內之位置而不同之密度設置有突起物。而且，在晶片狀半導體元件10之面設置有形狀不同之複數種突起物，晶片狀半導體元件10之面之中央區域之突起物之密度高於包圍中央區域之周邊區域之突起物之密度。 在圖所示之例中，晶片狀半導體元件10之面被分割為4個區塊。而且，基本上係以下之構成，即：靠近晶片狀半導體元件10之中心部之區域高密度地配置尺寸大之突起物12B，若遠離晶片狀半導體元件10之中心部則消除尺寸小之突起物12A且降低密度。 ［第6實施形態］ 第6實施形態係第5實施形態之變化例。在第5實施形態中，焊料凸塊在晶片狀半導體元件之面配置為矩陣狀。相對於此，在第6實施形態中以下之點不同，即：在一部分未配置有焊料凸塊，替代其形成有突起物。 圖14A及圖14B係用於說明第6實施形態之晶片狀半導體元件之構造之示意性平面圖，圖14A顯示電極之配置關係，圖14B顯示突起物之配置關係。圖15係用於說明第6實施形態之晶片狀半導體元件之構造之示意性平面圖，顯示電極與突起物之配置關係。 在第6實施形態中，在以符號13表示之區域中未配置有焊料凸塊11。為以填埋該區域13之方式配置有突起物12A、12B之構成。 ［第7實施形態］ 第7實施形態係第6實施形態之變化例。 圖16A及圖16B係用於說明第7實施形態之晶片狀半導體元件之構造之示意性平面圖，圖16A顯示電極之配置關係，圖16B顯示突起物之配置關係。圖17係用於說明第7實施形態之晶片狀半導體元件之構造之示意性平面圖，顯示電極與突起物之配置關係。 在第7實施形態中，在未配置有焊料凸塊11之區域13形成有以仿照平面形狀之方式形成之突起物12C。 ［第8實施形態］ 第8實施形態亦關於本發明之第1態樣之晶片狀半導體元件。 圖18A及圖18B係用於說明第8實施形態之晶片狀半導體元件之構造之示意性平面圖，圖18A顯示電極之配置關係，圖18B顯示突起物之配置關係。圖19係用於說明第8實施形態之晶片狀半導體元件之構造之示意性平面圖，顯示電極與突起物之配置關係。 在第1實施形態中參照圖8A至圖8D說明了突起物低於焊料凸塊之情形之步驟。在此情形下，由於焊料凸塊較突起物先與底部填充材料接觸，故較佳的是，以確保與晶片外相通之通路之方式配置焊料凸塊等。 在第8實施形態之晶片狀半導體元件10中，焊料凸塊11係沿晶片狀半導體元件10之外周部之各邊配置。然而，以在晶片狀半導體元件10之四個角隅及左右之邊各者之中央部確保與晶片外相通之通路之方式，在該等部分隔以間隔地配置有焊料凸塊11。 而且，在晶片狀半導體元件10之面之供配置突起物之區域(更具體而言，由焊料凸塊包圍之區域)，以確保與晶片外相通之流路之方式配置有突起物12C、12D、12E。 根據該構成，由於即便在回流時焊料凸塊11先與底部填充材料22接觸，仍確保自晶片狀半導體元件10之中央與晶片外相通之通路，故能夠有效地減小空隙。 ［第9實施形態］ 第9實施形態關於本發明之第1態樣之半導體裝置及晶片狀半導體元件。 在第1實施形態中說明了半導體裝置採用在配線基板上安裝有1個晶片狀半導體元件之構成。相對於此，第9實施形態之半導體裝置係所謂之多晶片構成。 圖20係用於說明具備一對晶片狀半導體元件之第9實施形態之半導體裝置之構造之示意性平面圖。 第9實施形態之半導體裝置1A係多晶片構成之半導體裝置，係在配線基板安裝有晶片狀半導體元件10A、10B而成。此外，在圖20中省略配線基板之記載。 圖21A及圖21B係用於說明第9實施形態之一對晶片狀半導體元件中一者之構造之示意性平面圖，圖21A顯示電極之配置關係，圖21B顯示突起物之配置關係。 在一個晶片狀半導體元件10A中，與第5實施形態相同地，焊料凸塊11在晶片狀半導體元件10A之面配置為矩陣狀。而且，在晶片狀半導體元件10A之面之配置突起物之區域(更具體而言，未配置有焊料凸塊之區域)，以將焊料凸塊之間填埋之方式配置有突起物12A、12B。 圖22A及圖22B係用於說明第9實施形態之一對晶片狀半導體元件中另一者之構造之示意性平面圖，圖22A顯示電極之配置關係，圖22B顯示突起物之配置關係。 在另一晶片狀半導體元件10B中，與第6實施形態相同地，在一部分未配置有焊料凸塊11，形成有突起物作為替代。 不論為晶片狀半導體元件10A、10B之任一者，晶片狀半導體元件之面均被分割為4個區塊。且為以下之構成：增大靠近各個晶片狀半導體元件之中心部之區域之突起物之尺寸且提高密度，隨著朝向外側而減小尺寸且降低密度。再者，為以下之構成：在晶片狀半導體元件10A、10B對向之邊側，與其他邊相比減小突起物之尺寸且降低密度。藉由降低突起物之密度，而能夠防止底部填充材料過量流入晶片狀半導體元件10A與晶片狀半導體元件10B對向之面，能夠適切地控制在晶片狀半導體元件間產生之張力。 ［第10實施形態］ 第10實施形態關於本發明之第1態樣之半導體裝置。 第10實施形態之半導體裝置係使覆晶安裝之接線與打線接合之接線混合之半導體裝置。 圖23A及圖23B係用於說明第10實施形態之半導體裝置之製造步驟之示意性部分剖視圖。 底部填充材料之統一塗佈在進行引線接合上成為障礙。因而，在配線基板20，在與覆晶安裝之晶片狀半導體元件10C對應之部分選擇性地塗佈底部填充材料22。而且，於在其上配置晶片狀半導體元件10D後，進行回流處理，其次進行固化處理。圖23A顯示回流處理中之狀況。 其次，在將例如由接著層30引線接合之晶片狀半導體元件10D搭載於被覆晶安裝之晶片狀半導體元件10C上後，藉由利用引線接合40在電極23進行配線而能夠獲得半導體裝置1B(參照圖23B)。 ［第11實施形態］ 第11實施形態關於本發明之第1態樣之晶片狀半導體元件。 在設置於晶片狀半導體元件之突起物為對稱形狀之情形下，當突起物下沉至軟化之底部填充材料時，基本上朝突起物周邊各向同性地壓出底部填充材料。 在如針對底部填充材料之填充性存在不均一之情形下，除調整晶片狀半導體元件之面之突起物之配置密度之處理外，還考量將突起物之形狀設為非對稱之處理。 圖24係用於說明第10實施形態之晶片狀半導體元件之突起部之構造之示意圖。 圖所示之突起物12係以下之非對稱形狀，即：相對於晶片狀半導體元件面，左側之斜面所成之角(以符號A1表示)與右側之斜面所成之角(以符號A2表示)不同，且在突起物12之前端之面與晶片狀半導體元件側之面上中心位置不同。 圖25A及圖25B係用於說明第11實施形態之晶片狀半導體元件之突起部之功能之示意圖。 當晶片狀半導體元件自圖25A所示之狀態進一步下沉而成為圖25B所示之狀態時，流動狀態之底部填充材料22A朝突起物12之右側被更多地壓出。藉此，能夠調整底部填充材料22之填充之程度。 將突起物12設為何種非對稱形狀，只要基於晶片狀半導體元件之規格等適宜地選擇較佳之形狀即可。非對稱形狀之突出部可利用例如3D打印技術等形成。 ［第12實施形態］ 本發明之第12實施形態係搭載由上述之各實施形態獲得之半導體裝置之電子機器。在圖26中顯示電子機器之概略構成。 電子機器1100係例如在形成為橫長之扁平之形狀之外殼1101之內外配置所需之各部而成，例如用作遊戲機器。 在外殼1101之正面、左右方向之中央部設置有顯示面板1102，在顯示面板1102之左右分別設置有在周向上隔開配置之4個操作鍵1103、及4個操作鍵1104。又，在外殼1101之正面之下端部設置有4個操作鍵1105。操作鍵1103、操作鍵1104、及操作鍵1105作為用於在顯示面板1102顯示之選單項目之選擇及遊戲之進行等之方向鍵及決定鍵而發揮功能。 在外殼1101之上表面設置有用於連接外部機器之連接端子1106、電力供給用之供給端子1107、及進行與外部機器之紅外線通訊之受光窗1108等。 接著，針對電子機器1100之電路構成進行說明。 圖27係顯示圖26所示之電子機器之電路構成之示意性方塊圖。 電子機器1100具備主CPU(Central Processing Unit，中央處理單元)1110、及系統控制器1120。例如自未圖示之電池以不同之系統將電力供給至主CPU 1110與系統控制器1120。電子機器1100更具有包含保持由保持使用者設定之各種資訊之記憶體等之設定資訊保持部1130。主CPU 1110、系統控制器1120、及設定資訊保持部1130構成為本發明之一體之半導體裝置。 主CPU 1110具有：產生用於令使用者進行各種資訊之設定及應用程式之選擇之選單畫面的選單處理部111、及執行應用程式之應用程式處理部112。所設定之資訊由主CPU 1110送出至設定資訊保持部1130，並被保持於設定資訊保持部1130中。系統控制器1120具有操作輸入受理部121、通訊處理部122及電力控制部123。由操作輸入受理部121進行操作鍵1103、操作鍵1104、及操作鍵1105之狀態檢測，由通訊處理部122進行與外部機器之間之通訊處理，由電力控制部123進行供給至各部之電力之控制。 (其他) 雖然以上針對本發明之實施形態具體地進行了說明，但本發明並不限定於上述之實施形態，可進行基於本發明之技術性思想之各種變化。例如，在上述之實施形態例舉之數值、構造、基板、原料、及製程等終極而言僅為一例，可根據需要使用與其等不同之數值、構造、基板、原料、及製程等。 此外，本發明之技術亦可採用如以下之構成。 ［A1］ 一種半導體裝置，其具備： 配線基板；及 晶片狀半導體元件，其覆晶安裝於配線基板上；且 在與配線基板對向之側之晶片狀半導體元件之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物； 晶片狀半導體元件藉由在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料塗佈於配線基板上之狀態下在配置為經由底部填充材料與配線基板對向後實施回流處理，而覆晶安裝於配線基板上。 ［A2］ 如上述［A1］之半導體裝置，其中晶片狀半導體元件具有突起物，該突起物形成為在晶片狀半導體元件被覆晶安裝之狀態下前端不到達配線基板。 ［A3］ 如上述［A1］或［A2］之半導體裝置，其中晶片狀半導體元件藉由設置於配線基板之焊料凸塊與設置於晶片狀半導體元件之焊料凸塊利用回流處理融合，而在相對於配線基板已定位之狀態下被安裝。 ［A4］ 如上述［A1］至［A3］中任一項之半導體裝置，其中底部填充材料被批量塗佈於配線基板上。 ［A5］ 如上述［A1］至［A4］中任一項之半導體裝置，其中底部填充材料具有助銲劑功能。 ［A6］ 如上述［A1］至［A5］中任一項之半導體裝置，其中在晶片狀半導體元件之面之供配置突起物之區域以一定之密度設置有突起物。 ［A7］ 如上述［A1］至［A5］中任一項之半導體裝置，其中在晶片狀半導體元件之面之供配置突起物之區域以相應於區域內之位置而不同之密度設置有突起物。 ［A8］ 如上述［A7］之半導體裝置，其中晶片狀半導體元件之面之相鄰之突起物間之間隙設置為橫穿供配置突起物之區域。 ［A9］ 如上述［A7］或［A8］之半導體裝置，其中晶片狀半導體元件之面之中央區域之突起物之密度高於包圍中央區域之周邊區域之突起物之密度。 ［A10］ 如上述［A1］至［A9］中任一項之半導體裝置，其中在晶片狀半導體元件之面設置有相同形狀之突起物。 ［A11］ 如上述［A1］至［A9］中任一項之半導體裝置，其中在晶片狀半導體元件之面設置有形狀不同之複數種突起物。 ［A12］ 如上述［A11］之半導體裝置，其中在晶片狀半導體元件之面設置有高度不同之複數種突起物。 ［A13］ 如上述［A1］至［A12］中任一項之半導體裝置，其中晶片狀半導體元件之面之突起物形成為越遠離晶片狀半導體元件之面則形狀越變小。 ［A14］ 如上述［A1］至［A13］中任一項之半導體裝置，其中晶片狀半導體元件之面之突起物係對稱形狀。 ［A15］ 如上述［A1］至［A13］中任一項之半導體裝置，其中晶片狀半導體元件之面之突起物係非對稱形狀。 ［B1］ 一種晶片狀半導體元件，其係覆晶安裝於塗佈有底部填充材料之配線基板上者，且 在與配線基板對向之側之晶片狀半導體元件之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物。 ［B2］ 如上述［B1］之晶片狀半導體元件，其中晶片狀半導體元件具有突起物，該突起物形成為在晶片狀半導體元件被覆晶安裝之狀態下前端不到達配線基板。 ［B3］ 如上述［B1］或［B2］之晶片狀半導體元件，其中在晶片狀半導體元件之面之供配置突起物之區域以一定之密度設置有突起物。 ［B4］ 如上述［B1］至［B3］中任一項之晶片狀半導體元件，其中在晶片狀半導體元件之面之供配置突起物之區域以相應於區域內之位置而不同之密度設置有突起物。 ［B5］ 如上述［B4］之晶片狀半導體元件，其中相鄰之突起物間之間隙設置為橫穿供配置突起物之區域。 ［B6］ 如上述［B4］或［B5］之晶片狀半導體元件，其中晶片狀半導體元件之面之中央區域之突起物之密度高於包圍中央區域之周邊區域之突起物之密度。 ［B7］ 如上述［B1］至［B6］中任一項之晶片狀半導體元件，其中在晶片狀半導體元件之面設置有相同形狀之突起物。 ［B8］ 如上述［B1］至［B6］中任一項之晶片狀半導體元件，其中在晶片狀半導體元件之面設置有形狀不同之複數種突起物。 ［B9］ 如上述［B8］之晶片狀半導體元件，其設置有高度不同之複數種突起物。 ［B10］ 如上述［B1］至［B9］中任一項之晶片狀半導體元件，其中突起物形成為越遠離晶片狀半導體元件之面則形狀越變小。 ［B11］ 如上述［B1］至［B10］中任一項之晶片狀半導體元件，其中突起物係對稱形狀。 ［B12］ 如上述［B1］至［B10］中任一項之晶片狀半導體元件，其中突起物係非對稱形狀。 ［C1］ 一種電子機器，其係包含含有配線基板、及覆晶安裝於配線基板上之晶片狀半導體元件的半導體裝置者；且 在與配線基板對向之側之晶片狀半導體元件之面設置有複數個焊料凸塊、及包含絕緣性材料之複數個突起物； 晶片狀半導體元件藉由在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料塗佈於配線基板上之狀態下在配置為經由底部填充材料與配線基板對向後實施回流處理，而覆晶安裝於配線基板上。 ［C2］ 如上述［C1］之電子機器，其中晶片狀半導體元件具有突起物，該突起物形成為在晶片狀半導體元件被覆晶安裝之狀態下前端不到達配線基板。 ［C3］ 如上述［C1］或［C2］之電子機器，其中晶片狀半導體元件藉由設置於配線基板之焊料凸塊與設置於晶片狀半導體元件之焊料凸塊利用回流處理融合，而在相對於配線基板已定位之狀態下被安裝。 ［C4］ 如上述［C1］至［C3］中任一項之電子機器，其中底部填充材料被批量塗佈於配線基板上。 ［C5］ 如上述［C1］至［C4］中任一項之電子機器，其中底部填充材料具有助銲劑功能。 ［C6］ 如上述［C1］至［C5］中任一項之電子機器，其中在晶片狀半導體元件之面之供配置突起物之區域以一定之密度設置有突起物。 ［C7］ 如上述［C1］至［C5］中任一項之電子機器，其中在晶片狀半導體元件之面之供配置突起物之區域以相應於區域內之位置而不同之密度設置有突起物。 ［C8］ 如上述［C7］之電子機器，其中晶片狀半導體元件之面之相鄰之突起物間之間隙設置為橫穿供配置突起物之區域。 ［C9］ 如上述［C7］或［C8］之電子機器，其中晶片狀半導體元件之面之中央區域之突起物之密度高於包圍中央區域之周邊區域之突起物之密度。 ［C10］ 如上述［C1］至［C9］中任一項之電子機器，其中在晶片狀半導體元件之面設置有相同形狀之突起物。 ［C11］ 如上述［C1］至［C9］中任一項之電子機器，其中在晶片狀半導體元件之面設置有形狀不同之複數種突起物。 ［C12］ 如上述［C11］之電子機器，其中在晶片狀半導體元件之面設置有高度不同之複數種突起物。 ［C13］ 如上述［C1］至［C12］中任一項之電子機器，其中晶片狀半導體元件之面之突起物形成為越遠離晶片狀半導體元件之面則形狀越變小。 ［C14］ 如上述［C1］至［C13］中任一項之電子機器，其中晶片狀半導體元件之面之突起物係對稱形狀。 ［C15］ 如上述［C1］至［C13］中任一項之電子機器，其中晶片狀半導體元件之面之突起物係非對稱形狀。 ［D1］ 一種半導體裝置之製造方法之製造方法，其包含以下步驟：藉由將在與配線基板對向之側之面設置有複數個焊料凸塊及包含絕緣性材料之複數個突起物之晶片狀半導體元件在將具有伴隨著溫度上升而黏度降低之特性之底部填充材料塗佈於配線基板上之狀態下在配置為經由底部填充材料與配線基板對向後實施回流處理，而將前述晶片狀半導體元件覆晶安裝於配線基板上。 ［D2］ 如上述［D1］之半導體裝置之製造方法，其中晶片狀半導體元件具有突起物，該突起物形成為在晶片狀半導體元件被覆晶安裝之狀態下前端不到達配線基板。 ［D3］ 如上述［D1］或［D2］之半導體裝置之製造方法，其中晶片狀半導體元件藉由設置於配線基板之焊料凸塊與設置於晶片狀半導體元件之焊料凸塊利用回流處理融合，而在相對於配線基板已定位之狀態下被安裝。 ［D4］ 如上述［D1］至［D3］中任一項之半導體裝置之製造方法，其中將底部填充材料批量塗佈於配線基板上。 ［D5］ 如上述［D1］至［D4］中任一項之半導體裝置之製造方法，其中底部填充材料具有助銲劑功能。 ［D6］ 如上述［D1］至［D5］中任一項之半導體裝置之製造方法，其中在晶片狀半導體元件之面之供配置突起物之區域以一定之密度設置有突起物。 ［D7］ 如上述［D1］至［D5］中任一項之半導體裝置之製造方法，其中在晶片狀半導體元件之面之供配置突起物之區域以相應於區域內之位置而不同之密度設置有突起物。 ［D8］ 如上述［D7］之半導體裝置之製造方法，其中晶片狀半導體元件之面之相鄰之突起物間之間隙設置為橫穿供配置突起物之區域。 ［D9］ 如上述［D7］或［D8］之半導體裝置之製造方法，其中晶片狀半導體元件之面之中央區域之突起物之密度高於包圍中央區域之周邊區域之突起物之密度。 ［D10］ 如上述［D1］至［D9］中任一項之半導體裝置之製造方法，其中在晶片狀半導體元件之面設置有相同形狀之突起物。 ［D11］ 如上述［D1］至［D9］中任一項之半導體裝置之製造方法，其中在晶片狀半導體元件之面設置有形狀不同之複數種突起物。 ［D12］ 如上述［D11］之半導體裝置之製造方法，其中在晶片狀半導體元件之面設置有高度不同之複數種突起物。 ［D13］ 如上述［D1］至［D12］中任一項之半導體裝置之製造方法，其中晶片狀半導體元件之面之突起物形成為越遠離晶片狀半導體元件之面則形狀越變小。 ［D14］ 如上述［D1］至［D13］中任一項之半導體裝置之製造方法，其中晶片狀半導體元件之面之突起物係對稱形狀。 ［D15］ 如上述［D1］至［D13］中任一項之半導體裝置之製造方法，其中晶片狀半導體元件之面之突起物係非對稱形狀。 Hereinafter, the present invention will be described based on embodiments with reference to the drawings. The present invention is not limited to the embodiment, and various numerical values and materials of the embodiment are exemplified. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and overlapping descriptions are omitted. In addition, the description is performed in the following order. 1. General description of a semiconductor device, a wafer-like semiconductor element, an electronic device including a semiconductor device, and a method of manufacturing a semiconductor device of the present invention 2. First Embodiment 3. Second Embodiment 4. Third Embodiment 5 . 4th embodiment 6. 5th embodiment 7. 6th embodiment 8. 7th embodiment 9. 8th embodiment 10. 9th embodiment 11. 10th embodiment 12. 11th embodiment 13. 12. Embodiment 14. Others [Description of the semiconductor device of the present invention, a wafer-like semiconductor element, an electronic apparatus including the semiconductor device, and the overall manufacturing method of the semiconductor device] In the semiconductor device of the present invention, the electronic device used in the present invention In the semiconductor device of the machine and the semiconductor device manufactured by the manufacturing method of the semiconductor device of the present invention (hereinafter, the semiconductor device of the present invention may be simply referred to as the semiconductor device of the present invention), the wafer-like semiconductor element may be constituted with protrusions , the protrusion is formed so that the tip of the protrusion does not reach the wiring board when the wafer-shaped semiconductor element is mounted on the flip chip. In the semiconductor device of the present invention including the above-mentioned preferable configuration, a configuration in which the wafer-like semiconductor element is fused by the solder bumps provided on the wiring board and the solder bumps provided on the wafer-like semiconductor element by a reflow process can be adopted , and is mounted in a state of being positioned relative to the wiring board. In the semiconductor device of the present invention including the above-mentioned various preferred configurations, the underfill material may be selectively applied on the wiring substrate, or may be applied in batches. From the viewpoint of improving the production efficiency, it is preferable to adopt the configuration of batch coating on the wiring substrate. In the semiconductor device of the present invention including the above-mentioned various preferable configurations, it is preferable that the underfill material has a flux function. According to this configuration, since the acidification of the metal surface in contact with the underfill material is removed, the fusion of the solder bumps in the reflow process can be performed favorably. As described above, the wafer-like semiconductor element of the present invention is a chip-like semiconductor element that is flip-chip mounted on a wiring substrate coated with an underfill material. A plurality of solder bumps and a plurality of protrusions made of an insulating material are provided on the surface of the wafer-like semiconductor element on the side facing the wiring board. Furthermore, it is possible to adopt a configuration having a protrusion formed so that the tip of the protrusion does not reach the wiring board in a state where the wafer-like semiconductor element is mounted on a flip chip. The wafer-like semiconductor element of the present invention, and the wafer-like semiconductor element used for the semiconductor wafer of the present invention (hereinafter, the same may be simply referred to as the wafer-like semiconductor element of the present invention) may have a higher density than that provided in the wafer-like semiconductor element. The solder bumps of the component are formed with higher protrusions, the solder bumps may be formed with protrusions of the same height, or the solder bumps may be formed with lower protrusions . In the wafer-like semiconductor element of the present invention including the above-mentioned various preferred structures, a structure in which protrusions are provided at a certain density in a region for arranging protrusions on the surface of the wafer-like semiconductor element can be employed. Alternatively, it is also possible to employ a configuration in which protrusions are provided at different densities according to the positions in the region in the area where the protrusions are arranged on the surface of the wafer-like semiconductor element. In this case, the gap between the adjacent protrusions can be set to traverse the area where the protrusions are arranged. Alternatively, the density of the protrusions in the central region of the surface of the wafer-like semiconductor element may be higher than the density of the protrusions in the peripheral region surrounding the central region. In the wafer-like semiconductor element of the present invention including the above-mentioned various preferable structures, a structure in which protrusions of the same shape are provided on the surface of the wafer-like semiconductor element can be adopted. Alternatively, it is also possible to employ a configuration in which a plurality of types of protrusions having different shapes are provided on the surface of the wafer-like semiconductor element. In this case, a configuration in which a plurality of protrusions having different heights are provided can be adopted. In the wafer-like semiconductor element of the present invention including the above-mentioned various preferable structures, the protrusions can be formed so as to be smaller in shape as the protrusions are formed farther from the surface of the wafer-like semiconductor element. For example, the protrusion may have the shape of a truncated cone whose cross-sectional shape becomes smaller as the surface side of the wafer-like semiconductor element becomes the bottom surface. In the wafer-like semiconductor device of the present invention including the above-mentioned various preferred structures, the protrusions may be symmetrical or asymmetrical. The semiconductor device, the wafer-like semiconductor element, the electronic device including the semiconductor device, and the manufacturing method of the semiconductor device of the present invention including the above-mentioned various preferable configurations (hereinafter, these and the like are simply referred to as the present invention) are used in The shape and configuration of the wiring board are not particularly limited as long as they do not hinder the implementation of the present invention. For example, a structure in which one wafer-like semiconductor element is mounted on one wiring board may be employed, or a structure in which a plurality of wafer-like semiconductor elements are mounted on one wiring board may be employed. Moreover, the structure which arrange|positions a wafer-shaped semiconductor element and a surface mount component may be sufficient. The protrusions provided in the wafer-like semiconductor element of the present invention can be formed by photolithography such as exposure using, for example, photosensitive resins such as PI-based, phenol-based, PBO-based, BCB-based, and acrylic-based. Alternatively, resins such as polyamide-based and ABS-based resins can also be used, and they can be formed by 3D printing technology. Furthermore, it can also be formed by an etching technique using a glass-based material. The method of coating the underfill material on the wiring board is not particularly limited as long as it does not hinder the implementation of the present invention. For example, various printing methods such as spin coating, spray coating, and printing can be applied. The material constituting the underfill material used in the present invention is not particularly limited as long as it does not hinder the implementation of the present invention. Specifically, as long as the viscosity is reduced to such an extent that self-alignment is not impaired during the reflow process, and the material can be cured after the reflow process. As the material constituting the underfill material, for example, an epoxy-based material can be exemplified. For example, a thermosetting underfill material is cured by a curing agent reacting with prolonged heating. The heating time during reflow is short, and the curing reaction is slight, and the temperature increases, and the viscosity decreases. In addition to the strictly established circumstances, the various conditions of this specification are also satisfied in the substantially established circumstances. Various deviations in design or manufacture are allowed. In addition, each drawing used in the following description is a schematic drawing, and does not represent an actual dimension and its ratio. [First Embodiment] The first embodiment relates to a semiconductor device, a wafer-like semiconductor element, and a method for manufacturing the semiconductor device according to the first aspect of the present invention. FIG. 1 is a schematic exploded perspective view for explaining a semiconductor device according to a first aspect of the present invention. In addition, for convenience of illustration and description, in FIG. 1, the wafer-shaped semiconductor element 10 and electrodes, protrusions, etc. provided on the wiring board 20 and the like are shown exaggeratedly. In addition, for convenience of description, it was demonstrated that one wafer-shaped semiconductor element is mounted on one wiring board, but the present invention is not limited to this. The semiconductor device 1 includes a wiring board 20 and a wafer-like semiconductor element 10 flip-chip mounted on the wiring board 20 . On the surface of the wafer-like semiconductor element 10 on the side facing the wiring board 20, a plurality of solder bumps and a plurality of protrusions made of an insulating material are provided. The wafer-like semiconductor element 10 is applied to the wiring board 20 with the underfill material 22 having the property of decreasing in viscosity as the temperature rises, and then the underfill material 22 is disposed so as to face the wiring board 20 . A reflow process is performed, and the flip chip is mounted on the wiring board 20 . The wafer-shaped semiconductor element 10 has a protrusion formed so that the tip does not reach the wiring board 20 in a state where the wafer-shaped semiconductor element 10 is mounted on a flip chip. Then, the wafer-like semiconductor element 10 is in a state of being positioned relative to the wiring board 20 by merging the solder bumps provided on the wiring board 20 and the solder bumps provided on the wafer-like semiconductor element 10 by a reflow process. installed below. The basic manufacturing steps of the semiconductor device 1 will be described. 2 is a step diagram for explaining the basic manufacturing steps of the semiconductor device according to the first aspect of the present invention. As shown in FIG. 2 , the underfill material 22 is applied on the wiring board 20 in batches (for example, refer to FIG. 5 described later). The wafer-like semiconductor element 10 is arranged to face the wiring board 20 via the underfill material 22 . In addition, in this case, it is sufficient that the wafer-like semiconductor elements 10 are arranged with an accuracy of such a degree that self-alignment is effective. That is, it is not necessary to precisely position the electrodes of the wiring board 20 and the electrodes of the wafer-like semiconductor element 10 so as to face each other accurately. Next, a batch reflow process is performed. 6 and 7 described later in detail, the self-alignment of soldering occurs during the reflow process, and the wafer-like semiconductor element 10 is mounted in a state of being positioned with respect to the wiring board 20 . After that, the underfill material 22 is cured, and the semiconductor device 1 is completed. As described above, a plurality of solder bumps and a plurality of protrusions made of an insulating material are provided on the surface of the wafer-like semiconductor element 10 on the side facing the wiring board 20 . The wafer-like semiconductor element 10 before flip chip mounting will be described in detail. 3A and 3B are schematic perspective views for explaining the arrangement of electrodes and protrusions of the wafer-like semiconductor element 10 . FIG. 3A shows the state before the protrusions are formed, and FIG. 3B shows the state after the protrusions are formed. In the example shown in the figure, solder bumps 11 are provided at predetermined intervals along each side of the rectangular chip-shaped semiconductor element 10 (see FIG. 3A ). With respect to the wafer-like semiconductor element 10 in this state, a plurality of protrusions 12 (refer to FIG. 3B ) containing an insulating material are formed on the inner side of the region surrounded by the solder bumps 11 using, for example, photolithography. In the example shown in the figure, the protrusions 12 are formed so that the shape becomes smaller and the shape becomes symmetrical as the protrusions 12 are formed farther away from the surface of the wafer-shaped semiconductor element 10 . The protrusions 12 have a function of sucking and filling the underfill material 22 previously applied to the wiring board 20 to the side of the wafer-like semiconductor element using a capillary phenomenon. The protrusions 12 are formed higher than the solder bumps 11 . Next, the wiring board 20 before flip chip mounting will be described. FIG. 4 is a schematic perspective view for explaining the electrode arrangement of the wiring board. FIG. 5 is a schematic perspective view for explaining the configuration of the electrodes of the wiring substrate and the first coating of the underfill material layer. A portion of the wiring board 20 that faces the wafer-like semiconductor element 10 is denoted by reference numeral 20A. In addition, in the following description, the part shown by the code|symbol 20A may be called simply the opposing part 20A. The opposing portion 20A is substantially rectangular, and solder bumps 21 (see FIG. 4 ) are formed along each side so as to correspond to the wafer-like semiconductor element 10 . With respect to the wiring board 20 in this state, the underfill material 22 is applied in batches (see FIG. 5 ). The outline of the semiconductor device 1 has been described above. Next, a method of manufacturing the semiconductor device 1 will be described in detail with reference to the drawings. The manufacturing method of the semiconductor device of the present invention includes the following steps: by providing a wafer-like semiconductor element having a plurality of solder bumps 11 and a plurality of protrusions 12 including an insulating material on a surface opposite to the wiring board 20 10. In a state where the underfill material 22 having the property of decreasing the viscosity as the temperature rises is applied on the wiring board 20, the wafer is disposed so as to be opposed to the wiring board 20 via the underfill material 22 and then subjected to a reflow process. The shape semiconductor element 10 is flip-chip mounted on the wiring board 20 . 6A to 6E are schematic partial cross-sectional views for explaining manufacturing steps of the semiconductor device. 7A to 7C are schematic partial cross-sectional views for explaining the manufacturing steps of the semiconductor device following FIG. 6E. For convenience of illustration, only a portion of the opposing portion 20A of the wiring board is shown in these figures. In addition, the shape etc. of each component are shown simplified. [Step-100] (see FIGS. 6A and 6B ) A wafer-like semiconductor element 10 is prepared, and solder bumps 11 serving as electrodes are formed thereon (see FIG. 6A ). Next, using, for example, photolithography, a plurality of protrusions 12 made of an insulating material are formed on the inner side of the area surrounded by the solder bumps 11 (see FIG. 6B ). [Step-110] (see FIGS. 6C and 6D ) The wiring board 20 is prepared, and solder bumps 21 serving as electrodes are formed on the opposing portion 20A (see FIG. 6C ). Next, the underfill material 22 is applied in batches on the entire surface including the opposing portion 20A (see FIG. 6D ). As described above, the underfill material 22 is applied on the wiring board 20 in batches. It is not necessary to apply selectively with respect to the opposing part 20A. In addition, the underfill material 22 having a flux function is used for coating. [Step- 120 ] (see FIG. 6E ) After that, the wafer-like semiconductor element 10 is arranged to face the wiring board 20 via the underfill material 22 . [Step-130] (see FIGS. 7A and 7B ) Next, a reflow process is performed. When the viscosity of the underfill material 22 decreases as the temperature rises, the protrusions 12 of the wafer-like semiconductor element 10 suck the underfill material 22 by capillary action (see FIG. 7A ). The underfill material in the flowing state is indicated by the symbol 22A. Then, the wafer-like semiconductor element 10 and the solder bumps 11 and 21 of the wiring board 20 are fused and attracted to each other (see FIG. 7B ). Thereby, self-alignment occurs, and the wafer-like semiconductor element 10 is in a state of being positioned with respect to the wiring board 20 . Therefore, even if a slight deviation remains in the arrangement of the wafer-like semiconductor elements 10 in [Step-120], the positioning is not hindered. Moreover, since the wafer-like semiconductor element 10 sinks further due to the fusion of the solder bumps 11 and 21 , filling of the underfill material 22A between the wafer-like semiconductor element 10 and the wiring board 20 is promoted. The gaps between the protrusions of the wafer-like semiconductor element 10 become gas flow paths during the filling process of the underfill material 22A. Therefore, the void of the underfill material 22 at the time of chip mounting can be reduced. The suction amount and reaching height of the underfill material 22A during the reflow process can be controlled by the design of the protrusions 12 . If the front ends of the protrusions 12 reach the wiring substrate 20 during the filling process of the underfill material 22A, the self-alignment effect due to the fusion of the solder bumps 11 and 21 is impaired. Therefore, the protrusion 12 is formed so that the tip of the protrusion 12 does not reach the wiring board 20 in a state where the wafer-shaped semiconductor element 10 is mounted on a flip chip. In addition, in some cases, within a range that does not impair the self-alignment effect, protrusions for the purpose of setting the gap between the front ends reaching the wiring board 20 may be further included. [Step-140] (see FIG. 7C ) Next, the curing process of the underfill material 22A is performed. As for the curing treatment, a preferred method may be appropriately selected according to the type of the underfill material. The underfill material after curing is indicated by the symbol 22B. Thereby, the semiconductor device 1 in which the wafer-like semiconductor element 10 is mounted on the wiring board 20 can be obtained. The manufacturing method of the present invention is a method of coating the underfill material first, and the cycle time required for sealing is shorter than that of the capillary underfill method. Furthermore, in the manufacturing method of the present invention, it is not necessary to press and heat the individual wafers at the time of wafer mounting. Furthermore, since the self-alignment of soldering is exerted, the positioning accuracy when arranging the wafer-like semiconductor elements is eased. Therefore, according to the manufacturing method of the present invention, the steps can be simplified, and the tact time and lead time can be greatly shortened. In addition, although the protrusion 12 is formed higher than the solder bump 11 in the above description, it is not limited to this. For example, the protrusions 12 and the solder bumps 11 may have the same height, or the protrusions 12 may be lower than the solder bumps 11 . In FIG. 8 , a step diagram of the case where the protrusions 12 are made lower than the solder bumps 11 is shown. FIG. 8A is a diagram corresponding to FIG. 6E. Since the protrusions 12 are lower than the solder bumps 11 , the solder bumps 11 come into contact with the underfill material 22 earlier than the protrusions 12 . FIG. 8B is a diagram corresponding to FIG. 7A , and FIG. 8C is a diagram corresponding to FIG. 7B . When the viscosity of the underfill material 22 decreases due to the reflow process, firstly, the resin is sucked through the solder bumps 11 (see FIG. 8B ), and secondly, the resin is also sucked by the protrusions 12 (see FIG. 8C ). FIG. 8D is a diagram corresponding to FIG. 7C. By performing the curing process after the reflow process, the semiconductor device 1 in which the wafer-like semiconductor element 10 is mounted on the wiring board 20 can be obtained. [Second Embodiment] The second embodiment relates to a wafer-like semiconductor element according to a first aspect of the present invention. FIG. 9 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the second embodiment. The solder bumps 11 of the wafer-shaped semiconductor element 10 of the second embodiment are continuously arranged along each side of the outer peripheral portion of the wafer-shaped semiconductor element 10 . In addition, the protrusions 12 are provided at a constant density in the area where the protrusions are arranged (more specifically, the area surrounded by the solder bumps) on the surface of the wafer-like semiconductor element 10 . In this configuration, on the surface of the wafer-like semiconductor element 10, the protrusions 12 of the same shape are arranged at the same pitch. The protrusions 12 can be formed using photolithography, for example, after coating a photosensitive insulating resin material, exposure is performed using a photomask having a desired pattern drawn thereon, and then a development process is performed. [Third Embodiment] The third embodiment also relates to the wafer-like semiconductor element of the first aspect of the present invention. In the second embodiment, the projections are provided at a constant density in the region where the projections are arranged. On the other hand, in the third embodiment, the protrusions are provided at different densities according to the positions in the region. 10 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the third embodiment. Also in the third embodiment, the solder bumps 11 are continuously arranged along each side of the outer peripheral portion of the wafer-like semiconductor element 10 , and the projections 12 are provided in the area of the surface of the wafer-like semiconductor element 10 where the projections are arranged. . However, in the third embodiment, the area surrounded by the solder bumps 11 is divided into a plurality of blocks. Also, gaps 13 are provided between the blocks. In each block, the protrusions 12 of the same shape are arranged at the same pitch. The gap 13 is set to be wider than the interval between the protrusions in the block. In this configuration, the gaps 13 between adjacent protrusions are arranged to traverse the area where the protrusions are arranged. Since the gaps 13 serve as gas flow paths during the mounting of the wafer-like semiconductor element 10 , the voids of the underfill material during the mounting of the wafer-like semiconductor element 10 can be effectively reduced. [Fourth Embodiment] The fourth embodiment is a modification of the third embodiment. In the third embodiment, in each block, protrusions of the same shape are arranged at the same pitch. On the other hand, in the fourth embodiment, the point of providing a plurality of projections with different shapes is mainly different. FIG. 11 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the fourth embodiment. Also in the fourth embodiment, the solder bumps 11 are continuously arranged along each side of the outer peripheral portion of the wafer-shaped semiconductor element 10 , and protrusions are provided in the area of the surface of the wafer-shaped semiconductor element 10 where the protrusions are arranged. Furthermore, the area surrounded by the solder bumps 11 is divided into a plurality of blocks. Also, gaps 13 are provided between the blocks. For example, protrusions 12A similar to the protrusions 12 shown in FIG. 10 are arranged in a block near the periphery of the wafer-like semiconductor element 10 . On the other hand, protrusions 12B with larger diameters are arranged in a block near the center of the wafer-like semiconductor element 10 . The protrusions 12B are also formed so that the shape becomes smaller and symmetrical as the protrusion 12B is further away from the surface of the wafer-like semiconductor element 10 . In addition, the heights of the protrusions 12A and the protrusions 12B may be the same or different. Like the third embodiment, the gap 13 is set to be wider than the interval between the protrusions in the block. As in the third embodiment, since the gaps 13 serve as gas flow paths during the mounting of the wafer-like semiconductor element, the voids of the underfill material during the mounting of the wafer-like semiconductor element can be effectively reduced. [Fifth Embodiment] The fifth embodiment also relates to the wafer-like semiconductor element of the first aspect of the present invention. 12A and 12B are schematic plan views for explaining the structure of the wafer-like semiconductor element according to the fifth embodiment. FIG. 12A shows the arrangement relationship of electrodes, and FIG. 12B shows the arrangement relationship of protrusions. FIG. 13 is a schematic plan view for explaining the structure of the wafer-like semiconductor element according to the fifth embodiment, and shows the arrangement relationship between electrodes and protrusions. In the second to fourth embodiments, the solder bumps are continuously arranged along each side of the outer peripheral portion of the wafer-like semiconductor element. On the other hand, in the fifth embodiment, the solder bumps 11 are arranged in a matrix on the surface of the wafer-like semiconductor element 10 . In addition, in the area where the bumps are arranged on the surface of the wafer-like semiconductor element 10 (more specifically, the area where the solder bumps are not arranged), the projections are arranged so as to fill between the solder bumps. In the area of the surface of the wafer-like semiconductor element 10 where the protrusions are arranged, the protrusions are provided at different densities according to the positions in the area. Furthermore, a plurality of protrusions of different shapes are provided on the surface of the wafer-like semiconductor element 10, and the density of the protrusions in the central region of the surface of the wafer-like semiconductor element 10 is higher than that of the peripheral region surrounding the central region. In the example shown in the figure, the surface of the wafer-like semiconductor element 10 is divided into four blocks. Furthermore, it is basically a structure in which the large-sized protrusions 12B are arranged at a high density in a region near the center of the wafer-like semiconductor element 10 , and the small-sized protrusions are eliminated when the region is far from the center of the wafer-like semiconductor element 10 . 12A and reduced density. [Sixth Embodiment] The sixth embodiment is a modification of the fifth embodiment. In the fifth embodiment, the solder bumps are arranged in a matrix on the surface of the wafer-like semiconductor element. On the other hand, the sixth embodiment is different in that a part of the solder bump is not arranged, and a protrusion is formed instead. 14A and 14B are schematic plan views for explaining the structure of the wafer-like semiconductor element of the sixth embodiment, FIG. 14A shows the arrangement relationship of electrodes, and FIG. 14B shows the arrangement relationship of protrusions. FIG. 15 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the sixth embodiment, and shows the arrangement relationship between electrodes and protrusions. In the sixth embodiment, the solder bumps 11 are not arranged in the region denoted by the reference numeral 13 . The protrusions 12A and 12B are arranged so as to fill the region 13 . [Seventh Embodiment] The seventh embodiment is a modification of the sixth embodiment. 16A and 16B are schematic plan views for explaining the structure of the wafer-like semiconductor element of the seventh embodiment, FIG. 16A shows the arrangement relationship of electrodes, and FIG. 16B shows the arrangement relationship of protrusions. FIG. 17 is a schematic plan view for explaining the structure of the wafer-like semiconductor element according to the seventh embodiment, and shows the arrangement relationship between electrodes and protrusions. In the seventh embodiment, projections 12C formed so as to mimic a planar shape are formed in the region 13 where the solder bumps 11 are not arranged. [Eighth Embodiment] The eighth embodiment also relates to the wafer-like semiconductor element of the first aspect of the present invention. 18A and 18B are schematic plan views for explaining the structure of the wafer-like semiconductor element of the eighth embodiment, FIG. 18A shows the arrangement relationship of electrodes, and FIG. 18B shows the arrangement relationship of protrusions. FIG. 19 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the eighth embodiment, and shows the arrangement relationship between electrodes and protrusions. In the first embodiment, the steps in the case where the protrusions are lower than the solder bumps have been described with reference to FIGS. 8A to 8D . In this case, since the solder bumps come into contact with the underfill material earlier than the protrusions, it is preferable to arrange the solder bumps and the like in such a manner as to ensure a via which communicates with the outside of the chip. In the wafer-like semiconductor element 10 according to the eighth embodiment, the solder bumps 11 are arranged along each side of the outer peripheral portion of the wafer-like semiconductor element 10 . However, the solder bumps 11 are arranged at intervals in the four corners of the wafer-like semiconductor element 10 and the central portion of each of the left and right sides so as to ensure passages communicating with the outside of the wafer. In addition, on the surface of the wafer-like semiconductor element 10 in which the projections are arranged (more specifically, the region surrounded by the solder bumps), the projections 12C and 12D are arranged so as to ensure a flow path communicating with the outside of the wafer. , 12E. According to this configuration, even if the solder bumps 11 first come into contact with the underfill material 22 during reflow, the passage from the center of the wafer-like semiconductor element 10 to the outside of the wafer is secured, so that voids can be effectively reduced. [Ninth Embodiment] The ninth embodiment relates to a semiconductor device and a wafer-like semiconductor element according to the first aspect of the present invention. In the first embodiment, the semiconductor device has been described as having a configuration in which one wafer-like semiconductor element is mounted on a wiring board. On the other hand, the semiconductor device of the ninth embodiment has a so-called multi-wafer structure. FIG. 20 is a schematic plan view for explaining the structure of the semiconductor device of the ninth embodiment including a pair of wafer-like semiconductor elements. The semiconductor device 1A of the ninth embodiment is a semiconductor device having a multi-chip configuration, and is formed by mounting wafer-like semiconductor elements 10A and 10B on a wiring board. In addition, in FIG. 20, description of a wiring board is abbreviate|omitted. 21A and 21B are schematic plan views for explaining the structure of one of the wafer-like semiconductor elements according to the ninth embodiment, FIG. 21A shows the arrangement relationship of electrodes, and FIG. 21B shows the arrangement relationship of protrusions. In one wafer-shaped semiconductor element 10A, as in the fifth embodiment, the solder bumps 11 are arranged in a matrix on the surface of the wafer-shaped semiconductor element 10A. In addition, on the surface of the wafer-shaped semiconductor element 10A, in the region where the projections are arranged (more specifically, the region where the solder bumps are not arranged), the projections 12A and 12B are arranged so as to fill in between the solder bumps. . 22A and 22B are schematic plan views for explaining the structure of the other one of the wafer-like semiconductor elements in the ninth embodiment, FIG. 22A shows the arrangement relationship of electrodes, and FIG. 22B shows the arrangement relationship of protrusions. In the other wafer-like semiconductor element 10B, as in the sixth embodiment, the solder bumps 11 are not arranged in a part, and protrusions are formed instead. Regardless of the wafer-like semiconductor elements 10A and 10B, the surface of the wafer-like semiconductor element is divided into four blocks. And it is a structure which increases the size of the protrusion in the area|region close to the center part of each wafer-shaped semiconductor element, and raises density, and reduces in size and density as it goes to the outside. Furthermore, it is a structure in which the size of a protrusion is made small compared with the other side and the density is reduced on the side where the wafer-shaped semiconductor elements 10A and 10B face each other. By reducing the density of the protrusions, the underfill material can be prevented from flowing excessively into the surfaces of the wafer-shaped semiconductor elements 10A and 10B facing the wafer-shaped semiconductor elements 10B, and the tension generated between the wafer-shaped semiconductor elements can be appropriately controlled. [Tenth Embodiment] The tenth embodiment relates to a semiconductor device according to the first aspect of the present invention. The semiconductor device of the tenth embodiment is a semiconductor device in which the wiring of flip chip mounting and the wiring of wire bonding are mixed. 23A and 23B are schematic partial cross-sectional views for explaining the manufacturing steps of the semiconductor device of the tenth embodiment. Uniform application of the underfill material is a hindrance in making wire bonds. Therefore, on the wiring board 20, the underfill material 22 is selectively applied to a portion corresponding to the flip-chip mounted wafer-like semiconductor element 10C. Then, after the wafer-like semiconductor element 10D is arranged thereon, a reflow process is performed, and then a curing process is performed. FIG. 23A shows the situation in the reflow process. Next, after mounting the wafer-like semiconductor element 10D wire-bonded by the bonding layer 30 on the flip-chip mounted wafer-like semiconductor element 10C, for example, the semiconductor device 1B can be obtained by wiring the electrodes 23 by the wire bonding 40 (see Figure 23B). [Eleventh Embodiment] The eleventh embodiment relates to a wafer-like semiconductor element according to the first aspect of the present invention. In the case where the protrusions disposed on the wafer-like semiconductor device are symmetrical in shape, the underfill material is substantially isotropically pressed out toward the periphery of the protrusions as the protrusions sink into the softened underfill material. In the case of uneven filling of the underfill material, in addition to adjusting the arrangement density of the protrusions on the surface of the wafer-like semiconductor device, a process of making the shape of the protrusions asymmetric is also considered. FIG. 24 is a schematic diagram for explaining the structure of the protrusion of the wafer-like semiconductor element of the tenth embodiment. The protrusion 12 shown in the figure has the following asymmetric shape, that is, with respect to the surface of the wafer-like semiconductor element, the angle formed by the left slope (represented by the symbol A1) and the angle formed by the right slope (represented by the symbol A2) ) are different, and the center positions are different between the surface of the front end of the protrusion 12 and the surface on the side of the wafer-shaped semiconductor element. 25A and 25B are schematic diagrams for explaining the function of the protrusions of the wafer-like semiconductor element of the eleventh embodiment. When the wafer-like semiconductor element sinks further from the state shown in FIG. 25A to the state shown in FIG. 25B , the underfill material 22A in the flowing state is pressed out more toward the right side of the protrusion 12 . Thereby, the filling degree of the underfill material 22 can be adjusted. What asymmetric shape the protrusions 12 are made into can be appropriately selected based on the specifications of the wafer-like semiconductor element and the like. The asymmetrically shaped protrusions can be formed using, for example, 3D printing techniques or the like. [Twelfth Embodiment] A twelfth embodiment of the present invention is an electronic device on which the semiconductor device obtained in each of the above-described embodiments is mounted. A schematic configuration of an electronic device is shown in FIG. 26 . The electronic apparatus 1100 is configured by, for example, arranging necessary parts inside and outside a casing 1101 formed in a horizontally elongated flat shape, and is used, for example, as a game machine. A display panel 1102 is provided on the front surface of the housing 1101 in the center in the left-right direction, and four operation keys 1103 and four operation keys 1104 are provided on the left and right sides of the display panel 1102, which are spaced apart in the circumferential direction. In addition, four operation keys 1105 are provided on the lower end of the front surface of the casing 1101 . The operation key 1103 , the operation key 1104 , and the operation key 1105 function as direction keys and decision keys for selection of menu items displayed on the display panel 1102 and progress of a game, and the like. On the upper surface of the casing 1101, a connection terminal 1106 for connecting to an external device, a supply terminal 1107 for power supply, a light-receiving window 1108 for performing infrared communication with an external device, and the like are provided. Next, the circuit configuration of the electronic device 1100 will be described. FIG. 27 is a schematic block diagram showing the circuit configuration of the electronic apparatus shown in FIG. 26 . The electronic apparatus 1100 includes a main CPU (Central Processing Unit) 1110 and a system controller 1120 . Power is supplied to the main CPU 1110 and the system controller 1120 in different systems, for example, from a battery not shown. The electronic device 1100 further includes a setting information holding unit 1130 including a memory that holds various information set by the user and the like. The main CPU 1110, the system controller 1120, and the setting information holding unit 1130 constitute an integrated semiconductor device of the present invention. The main CPU 1110 includes a menu processing unit 111 that generates a menu screen for allowing the user to set various information and select an application, and an application processing unit 112 that executes the application. The set information is sent from the main CPU 1110 to the setting information holding unit 1130 , and is held in the setting information holding unit 1130 . The system controller 1120 includes an operation input accepting unit 121 , a communication processing unit 122 , and a power control unit 123 . The state detection of the operation keys 1103 , 1104 , and 1105 is performed by the operation input accepting unit 121 , the communication processing with external equipment is performed by the communication processing unit 122 , and the power supply to each unit is controlled by the power control unit 123 . control. (Others) Although the embodiment of the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various changes based on the technical idea of the present invention can be made. For example, the numerical values, structures, substrates, materials, and processes exemplified in the above-mentioned embodiments are only examples in the end, and values, structures, substrates, materials, and processes that are different from the above can be used as needed. In addition, the technology of the present invention may employ the following configurations. [A1] A semiconductor device comprising: a wiring board; and a wafer-like semiconductor element flip-chip mounted on the wiring board; and a plurality of solder bumps provided on a surface of the wafer-like semiconductor element on the side facing the wiring board A block, and a plurality of protrusions including an insulating material; a wafer-like semiconductor element is arranged to be underfilled by applying an underfill material having a property of decreasing viscosity with temperature rise on a wiring board The material and the wiring substrate are subjected to a reflow process, and the flip chip is mounted on the wiring substrate. [A2] The semiconductor device according to the above [A1], wherein the wafer-shaped semiconductor element has a protrusion formed so that the tip does not reach the wiring board in a state where the wafer-shaped semiconductor element is mounted on a flip chip. [A3] The semiconductor device according to the above [A1] or [A2], wherein the wafer-like semiconductor element is fused by a reflow process between the solder bumps provided on the wiring board and the solder bumps provided on the wafer-like semiconductor element, and the wafer-like semiconductor elements are opposite to each other. Installed with the wiring board positioned. [A4] The semiconductor device according to any one of the above [A1] to [A3], wherein the underfill material is batch-coated on the wiring substrate. [A5] The semiconductor device according to any one of the above [A1] to [A4], wherein the underfill material has a flux function. [A6] The semiconductor device according to any one of the above [A1] to [A5], wherein the protrusions are provided at a constant density in a region where the protrusions are disposed on the surface of the wafer-shaped semiconductor element. [A7] The semiconductor device according to any one of the above [A1] to [A5], wherein a region on the surface of the wafer-like semiconductor element where the protrusions are disposed is provided with protrusions at different densities according to positions in the region . [A8] The semiconductor device according to the above [A7], wherein gaps between adjacent protrusions on the surface of the wafer-like semiconductor element are provided so as to traverse a region where the protrusions are arranged. [A9] The semiconductor device of the above [A7] or [A8], wherein the density of protrusions in the central region of the surface of the wafer-like semiconductor element is higher than the density of protrusions in the peripheral region surrounding the central region. [A10] The semiconductor device according to any one of the above [A1] to [A9], wherein protrusions of the same shape are provided on the surface of the wafer-like semiconductor element. [A11] The semiconductor device according to any one of the above [A1] to [A9], wherein a plurality of types of protrusions having different shapes are provided on the surface of the wafer-like semiconductor element. [A12] The semiconductor device according to the above [A11], wherein a plurality of types of protrusions having different heights are provided on the surface of the wafer-like semiconductor element. [A13] The semiconductor device according to any one of the above [A1] to [A12], wherein the protrusions on the surface of the wafer-like semiconductor element are formed so as to become smaller in shape as they are farther away from the surface of the wafer-like semiconductor element. [A14] The semiconductor device according to any one of the above [A1] to [A13], wherein the protrusions on the surface of the wafer-like semiconductor element are symmetrically shaped. [A15] The semiconductor device according to any one of the above [A1] to [A13], wherein the protrusions on the surface of the wafer-like semiconductor element are asymmetrical. [B1] A wafer-shaped semiconductor element, which is flip-chip mounted on a wiring substrate coated with an underfill material, and a plurality of solder bumps are provided on the surface of the wafer-shaped semiconductor element on the side opposite to the wiring substrate , and a plurality of protrusions comprising insulating material. [B2] The wafer-like semiconductor element according to the above [B1], wherein the wafer-like semiconductor element has a protrusion formed so that the tip does not reach the wiring board when the wafer-like semiconductor element is mounted on a flip chip. [B3] The wafer-like semiconductor element according to the above [B1] or [B2], wherein protrusions are provided at a constant density in a region of the surface of the wafer-like semiconductor element where the protrusions are arranged. [B4] The wafer-like semiconductor element according to any one of the above [B1] to [B3], wherein a region on the surface of the wafer-like semiconductor element in which the projections are arranged is provided with different densities corresponding to positions in the region. protrusions. [B5] The wafer-like semiconductor device according to the above [B4], wherein the gaps between adjacent protrusions are set so as to traverse the region where the protrusions are arranged. [B6] The wafer-like semiconductor element according to the above [B4] or [B5], wherein the density of protrusions in the central region of the surface of the wafer-like semiconductor element is higher than the density of protrusions in the peripheral region surrounding the central region. [B7] The wafer-like semiconductor element according to any one of the above [B1] to [B6], wherein protrusions of the same shape are provided on the surface of the wafer-like semiconductor element. [B8] The wafer-like semiconductor element according to any one of the above [B1] to [B6], wherein a plurality of types of protrusions having different shapes are provided on the surface of the wafer-like semiconductor element. [B9] The wafer-like semiconductor element according to the above [B8], wherein a plurality of types of protrusions having different heights are provided. [B10] The wafer-like semiconductor element according to any one of the above [B1] to [B9], wherein the protrusions are formed so as to be smaller in shape as they are farther away from the surface of the wafer-like semiconductor element. [B11] The wafer-like semiconductor element according to any one of the above [B1] to [B10], wherein the protrusions are symmetrically shaped. [B12] The wafer-like semiconductor element according to any one of the above [B1] to [B10], wherein the protrusions are asymmetrically shaped. [C1] An electronic device including a semiconductor device including a wiring board and a wafer-like semiconductor element flip-chip mounted on the wiring board; and provided on the surface of the wafer-like semiconductor element on the side facing the wiring board; A plurality of solder bumps, and a plurality of protrusions including an insulating material; the wafer-like semiconductor element is arranged in a state where an underfill material having a property of decreasing viscosity with temperature rise is applied on a wiring board The flip chip is mounted on the wiring substrate in order to perform a reflow process on the wiring substrate via the underfill material. [C2] The electronic device according to the above [C1], wherein the wafer-shaped semiconductor element has a protrusion formed so that the tip does not reach the wiring board in a state where the wafer-shaped semiconductor element is mounted on a flip chip. [C3] The electronic apparatus according to the above [C1] or [C2], wherein the wafer-like semiconductor element is fused by a reflow process between the solder bumps provided on the wiring board and the solder bumps provided on the wafer-like semiconductor element, and the opposite Installed with the wiring board positioned. [C4] The electronic apparatus of any one of the above [C1] to [C3], wherein the underfill material is batch-coated on the wiring substrate. [C5] The electronic apparatus of any one of the above [C1] to [C4], wherein the underfill material has a flux function. [C6] The electronic device according to any one of the above [C1] to [C5], wherein protrusions are provided at a constant density in a region of the surface of the wafer-like semiconductor element where the protrusions are disposed. [C7] The electronic device according to any one of the above [C1] to [C5], wherein protrusions are provided at different densities corresponding to positions within the region in a region of the surface of the wafer-like semiconductor element where the protrusions are disposed . [C8] The electronic device according to the above [C7], wherein the gaps between the adjacent protrusions on the surface of the wafer-like semiconductor element are provided so as to traverse the region where the protrusions are arranged. [C9] The electronic device according to the above [C7] or [C8], wherein the density of protrusions in the central region of the surface of the wafer-like semiconductor element is higher than the density of protrusions in the peripheral region surrounding the central region. [C10] The electronic device according to any one of the above [C1] to [C9], wherein protrusions of the same shape are provided on the surface of the wafer-like semiconductor element. [C11] The electronic device according to any one of the above [C1] to [C9], wherein a plurality of types of protrusions having different shapes are provided on the surface of the wafer-like semiconductor element. [C12] The electronic device according to the above [C11], wherein a plurality of types of protrusions having different heights are provided on the surface of the wafer-like semiconductor element. [C13] The electronic device according to any one of the above [C1] to [C12], wherein the protrusions on the surface of the wafer-like semiconductor element are formed so as to become smaller in shape as they are farther away from the surface of the wafer-like semiconductor element. [C14] The electronic device according to any one of the above [C1] to [C13], wherein the protrusions on the surface of the wafer-like semiconductor element are symmetrically shaped. [C15] The electronic device according to any one of the above [C1] to [C13], wherein the protrusions on the surface of the wafer-like semiconductor element are asymmetrical. [D1] A method of manufacturing a semiconductor device, comprising the steps of: disposing a chip having a plurality of solder bumps and a plurality of protrusions of an insulating material on a surface opposite to a wiring board The wafer-shaped semiconductor element is placed in a state where the underfill material having the property of decreasing the viscosity as the temperature rises is applied on the wiring board, and the wafer-shaped semiconductor element is disposed so as to be opposed to the wiring board via the underfill material and then subjected to a reflow process. The element flip chip is mounted on the wiring board. [D2] The method of manufacturing a semiconductor device according to the above [D1], wherein the wafer-like semiconductor element has a protrusion formed so that the tip does not reach the wiring board when the wafer-like semiconductor element is mounted on a flip chip. [D3] The method of manufacturing a semiconductor device according to the above [D1] or [D2], wherein the wafer-like semiconductor element is fused by a reflow process by means of the solder bumps provided on the wiring board and the solder bumps provided on the wafer-like semiconductor element, And it is mounted in the state positioned with respect to the wiring board. [D4] The method of manufacturing a semiconductor device according to any one of the above [D1] to [D3], wherein the underfill material is batch-coated on the wiring substrate. [D5] The method of manufacturing a semiconductor device according to any one of the above [D1] to [D4], wherein the underfill material has a flux function. [D6] The method of manufacturing a semiconductor device according to any one of the above [D1] to [D5], wherein the protrusions are provided at a constant density in a region of the surface of the wafer-like semiconductor element where the protrusions are disposed. [D7] The method for manufacturing a semiconductor device according to any one of the above [D1] to [D5], wherein a region on the surface of the wafer-like semiconductor element where the protrusions are arranged is provided at a density that differs according to the position in the region There are protrusions. [D8] The method of manufacturing a semiconductor device according to the above [D7], wherein the gaps between the adjacent protrusions on the surface of the wafer-like semiconductor element are set to traverse the region where the protrusions are arranged. [D9] The method of manufacturing a semiconductor device according to the above [D7] or [D8], wherein the density of the protrusions in the central region of the surface of the wafer-like semiconductor element is higher than the density of the protrusions in the peripheral region surrounding the central region. [D10] The method for manufacturing a semiconductor device according to any one of the above [D1] to [D9], wherein protrusions of the same shape are provided on the surface of the wafer-like semiconductor element. [D11] The method for manufacturing a semiconductor device according to any one of the above [D1] to [D9], wherein a plurality of types of protrusions having different shapes are provided on the surface of the wafer-like semiconductor element. [D12] The method of manufacturing a semiconductor device according to the above [D11], wherein a plurality of types of protrusions having different heights are provided on the surface of the wafer-like semiconductor element. [D13] The method for manufacturing a semiconductor device according to any one of the above [D1] to [D12], wherein the protrusions on the surface of the wafer-like semiconductor element are formed so as to become smaller in shape as they are farther away from the surface of the wafer-like semiconductor element. [D14] The method of manufacturing a semiconductor device according to any one of the above [D1] to [D13], wherein the protrusions on the surface of the wafer-like semiconductor element are symmetrically shaped. [D15] The method for manufacturing a semiconductor device according to any one of the above [D1] to [D13], wherein the protrusions on the surface of the wafer-like semiconductor element are asymmetrical.

1‧‧‧半導體裝置1A‧‧‧半導體裝置1B‧‧‧半導體裝置10‧‧‧晶片狀半導體元件10A‧‧‧晶片狀半導體元件10B‧‧‧晶片狀半導體元件10C‧‧‧晶片狀半導體元件10D‧‧‧晶片狀半導體元件11‧‧‧晶片狀半導體元件之電極(焊料凸塊)12‧‧‧突起物12A‧‧‧突起物12B‧‧‧突起物12C‧‧‧突起物12D‧‧‧突起物12E‧‧‧突起物12F‧‧‧突起物13‧‧‧間隙/區域20‧‧‧配線基板20A‧‧‧對向部21‧‧‧配線基板之電極(焊料凸塊)22‧‧‧底部填充材料22A‧‧‧底部填充材料22B‧‧‧底部填充材料23‧‧‧電極30‧‧‧接著層40‧‧‧引線接合1100‧‧‧電子機器1101‧‧‧外殼1102‧‧‧顯示面板1103‧‧‧操作鍵1104‧‧‧操作鍵1105‧‧‧操作鍵1106‧‧‧連接端子1107‧‧‧電力供給用之供給端子1108‧‧‧受光窗1110‧‧‧主CPU/中央處理單元1111‧‧‧選單處理部1112‧‧‧應用程式處理部1120‧‧‧系統控制器1121‧‧‧操作輸入受理部1122‧‧‧通訊處理部1123‧‧‧電力控制部1130‧‧‧設定資訊保持部A1‧‧‧角A2‧‧‧角1‧‧‧Semiconductor device 1A‧‧‧Semiconductor device 1B‧‧‧Semiconductor device 10‧‧‧Wafer-shaped semiconductor element 10A‧‧‧Wafer-shaped semiconductor device 10B‧‧‧Wafer-shaped semiconductor device 10C‧‧‧Wafer-shaped semiconductor device 10D‧‧‧Wafer-shaped semiconductor device 11‧‧‧Electrodes (solder bumps) of chip-shaped semiconductor device 12‧‧‧Protrusions 12A‧‧‧Protrusions 12B‧‧‧Protrusions 12C‧‧‧Protrusions 12D‧‧ ‧Projection 12E‧‧‧Projection 12F‧‧‧Projection 13‧‧‧Gap/area 20‧‧‧Wiring board 20A‧‧‧Opposing part 21‧‧‧Electrode (solder bump) of wiring board 22‧ ‧‧Underfill material 22A‧‧‧Underfill material 22B‧‧‧Underfill material 23‧‧‧Electrode 30‧‧‧Adhesion layer 40‧‧‧Wire bonding 1100‧‧‧Electronic equipment 1101‧‧‧Enclosure 1102‧‧ ‧Display panel 1103‧‧‧Operation keys 1104‧‧‧Operation keys 1105‧‧‧Operation keys 1106‧‧‧Connecting terminals 1107‧‧‧Supply terminals for power supply 1108‧‧‧Light receiving window 1110‧‧‧Main CPU/ Central processing unit 1111‧‧‧Menu processing part 1112‧‧‧Application processing part 1120‧‧‧System controller 1121‧‧‧Operation input receiving part 1122‧‧‧Communication processing part 1123‧‧‧Power control part 1130‧‧ ‧Setting information holding part A1‧‧‧corner A2‧‧‧corner

圖1係用於說明本發明之第1態樣之半導體裝置之示意性分解立體圖。 圖2係用於說明本發明之第1態樣之半導體裝置之基本的製造步驟之步驟圖。 圖3A及圖3B係用於說明晶片狀半導體元件之電極與突起物之配置之示意性立體圖。圖3A顯示突起物形成前之狀態；圖3B顯示突起物形成後之狀態。 圖4係用於說明配線基板之電極配置之示意性立體圖。 圖5係用於說明配線基板之電極與先塗佈底部填充材料層之配置之示意性立體圖。 圖6A至圖6E係用於說明半導體裝置之製造步驟之示意性部分剖視圖。 圖7A至圖7C係接續圖6E用於說明半導體裝置之製造步驟之示意性部分剖視圖。 圖8A至圖8D係用於說明半導體裝置之製造步驟之示意性部分剖視圖。 圖9係用於說明第2實施形態之晶片狀半導體元件之構造之示意性平面圖。 圖10係用於說明第3實施形態之晶片狀半導體元件之構造之示意性平面圖。 圖11係用於說明第4實施形態之晶片狀半導體元件之構造之示意性平面圖。 圖12A及圖12B係用於說明第5實施形態之晶片狀半導體元件之構造之示意性平面圖；圖12A顯示電極之配置關係；圖12B顯示突起物之配置關係。 圖13係用於說明第5實施形態之晶片狀半導體元件之構造之示意性平面圖，顯示電極與突起物之配置關係。 圖14A及圖14B係用於說明第6實施形態之晶片狀半導體元件之構造之示意性平面圖；圖14A顯示電極之配置關係；圖14B顯示突起物之配置關係。 圖15係用於說明第6實施形態之晶片狀半導體元件之構造之示意性平面圖，顯示電極與突起物之配置關係。 圖16A及圖16B係用於說明第7實施形態之晶片狀半導體元件之構造之示意性平面圖；圖16A顯示電極之配置關係；圖16B顯示突起物之配置關係。 圖17係用於說明第7實施形態之晶片狀半導體元件之構造之示意性平面圖，顯示電極與突起物之配置關係。 圖18A及圖18B係用於說明第8實施形態之晶片狀半導體元件之構造之示意性平面圖；圖18A顯示電極之配置關係；圖18B顯示突起物之配置關係。 圖19係用於說明第8實施形態之晶片狀半導體元件之構造之示意性平面圖，顯示電極與突起物之配置關係。 圖20係用於說明具備一對晶片狀半導體元件之第9實施形態之半導體裝置之構造之示意性平面圖。 圖21A及圖21B係用於說明第9實施形態之一對晶片狀半導體元件中一者之構造之示意性平面圖；圖21A顯示電極之配置關係；圖21B顯示突起物之配置關係。 圖22A及圖22B係用於說明第9實施形態之一對晶片狀半導體元件中另一者之構造之示意性平面圖；圖22A顯示電極之配置關係；圖22B顯示突起物之配置關係。 圖23A及圖23B係用於說明第10實施形態之半導體裝置之製造步驟之示意性部分剖視圖。 圖24係用於說明第11實施形態之晶片狀半導體元件之突起部之構造之示意圖。 圖25A及圖25B係用於說明第11實施形態之晶片狀半導體元件之突起部之功能之示意圖。 圖26係針對第12實施形態之圖，係本發明之半導體裝置所使用之電子機器之示意性立體圖。 圖27係顯示圖26所示之電子機器之電路構成之示意性方塊圖。 圖28A及圖28B係用於說明半導體裝置之製造步驟之步驟圖。FIG. 1 is a schematic exploded perspective view for explaining a semiconductor device according to a first aspect of the present invention. 2 is a step diagram for explaining the basic manufacturing steps of the semiconductor device according to the first aspect of the present invention. 3A and 3B are schematic perspective views for explaining the arrangement of electrodes and protrusions of the wafer-like semiconductor element. FIG. 3A shows the state before the protrusions are formed; FIG. 3B shows the state after the protrusions are formed. FIG. 4 is a schematic perspective view for explaining the electrode arrangement of the wiring board. FIG. 5 is a schematic perspective view for explaining the configuration of the electrodes of the wiring substrate and the first coating of the underfill material layer. 6A to 6E are schematic partial cross-sectional views for explaining manufacturing steps of the semiconductor device. 7A to 7C are schematic partial cross-sectional views for explaining the manufacturing steps of the semiconductor device following FIG. 6E. 8A to 8D are schematic partial cross-sectional views for explaining the manufacturing steps of the semiconductor device. FIG. 9 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the second embodiment. 10 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the third embodiment. FIG. 11 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the fourth embodiment. 12A and 12B are schematic plan views for explaining the structure of the wafer-like semiconductor element according to the fifth embodiment; FIG. 12A shows the arrangement relationship of electrodes; and FIG. 12B shows the arrangement relationship of protrusions. FIG. 13 is a schematic plan view for explaining the structure of the wafer-like semiconductor element according to the fifth embodiment, and shows the arrangement relationship between electrodes and protrusions. 14A and 14B are schematic plan views for explaining the structure of the wafer-like semiconductor element of the sixth embodiment; FIG. 14A shows the arrangement relationship of the electrodes; and FIG. 14B shows the arrangement relationship of the protrusions. FIG. 15 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the sixth embodiment, and shows the arrangement relationship between electrodes and protrusions. 16A and 16B are schematic plan views for explaining the structure of the wafer-like semiconductor element of the seventh embodiment; FIG. 16A shows the arrangement relationship of electrodes; and FIG. 16B shows the arrangement relationship of protrusions. FIG. 17 is a schematic plan view for explaining the structure of the wafer-like semiconductor element according to the seventh embodiment, and shows the arrangement relationship between electrodes and protrusions. 18A and 18B are schematic plan views for explaining the structure of the wafer-like semiconductor element of the eighth embodiment; FIG. 18A shows the arrangement relationship of the electrodes; and FIG. 18B shows the arrangement relationship of the protrusions. FIG. 19 is a schematic plan view for explaining the structure of the wafer-like semiconductor element of the eighth embodiment, and shows the arrangement relationship between electrodes and protrusions. FIG. 20 is a schematic plan view for explaining the structure of the semiconductor device of the ninth embodiment including a pair of wafer-like semiconductor elements. 21A and 21B are schematic plan views for explaining the structure of one of the wafer-like semiconductor elements in the ninth embodiment; FIG. 21A shows the arrangement of electrodes; and FIG. 21B shows the arrangement of protrusions. 22A and 22B are schematic plan views for explaining the structure of the other of the wafer-like semiconductor elements in one of the ninth embodiments; FIG. 22A shows the arrangement of electrodes; and FIG. 22B shows the arrangement of protrusions. 23A and 23B are schematic partial cross-sectional views for explaining the manufacturing steps of the semiconductor device of the tenth embodiment. FIG. 24 is a schematic diagram for explaining the structure of the protrusion of the wafer-like semiconductor element of the eleventh embodiment. 25A and 25B are schematic diagrams for explaining the function of the protrusions of the wafer-like semiconductor element of the eleventh embodiment. FIG. 26 is a diagram for the twelfth embodiment, and is a schematic perspective view of an electronic device used in the semiconductor device of the present invention. FIG. 27 is a schematic block diagram showing the circuit configuration of the electronic apparatus shown in FIG. 26 . 28A and 28B are step diagrams for explaining the manufacturing steps of the semiconductor device.

1‧‧‧半導體裝置 1‧‧‧Semiconductor device

10‧‧‧晶片狀半導體元件 10‧‧‧Chip-like semiconductor devices

20‧‧‧配線基板 20‧‧‧Wiring board

22‧‧‧底部填充材料 22‧‧‧Underfill material

Claims (16)

一種半導體裝置，其包含：配線基板；及晶片狀半導體元件，其覆晶安裝於上述配線基板上；且上述晶片狀半導體元件在上述晶片狀半導體元件之面，設置有複數個焊料凸塊、及複數個突起物；上述面與上述配線基板對向；上述複數個焊料凸塊與上述複數個突起物之各者包含絕緣性材料；上述複數個突起物之第1突起物組設置於上述晶片狀半導體元件之上述面之中央區域；上述複數個突起物之第2突起物組設置於上述晶片狀半導體元件之上述面之周邊區域；上述周邊區域包圍上述中央區域；上述第1突起物組之各者之尺寸較上述第2突起物組之各者之尺寸更大；上述第1突起物組之密度較上述第2突起物組之密度更高；上述配線基板包含底部填充材料。 A semiconductor device comprising: a wiring board; and a wafer-like semiconductor element, which is flip-chip mounted on the wiring board; and the wafer-like semiconductor element is provided with a plurality of solder bumps on a surface of the wafer-like semiconductor element, and a plurality of protrusions; the surface is opposite to the wiring board; each of the plurality of solder bumps and the plurality of protrusions includes an insulating material; the first protrusion group of the plurality of protrusions is provided in the wafer shape a central area of the above-mentioned surface of the semiconductor element; a second group of protrusions of the plurality of protrusions is provided in a peripheral area of the above-mentioned surface of the wafer-like semiconductor element; the above-mentioned peripheral area surrounds the above-mentioned central area; each of the above-mentioned first group of protrusions The size of the first protrusion group is larger than the size of each of the second protrusion group; the density of the first protrusion group is higher than the density of the second protrusion group; the wiring substrate includes an underfill material. 如請求項1之半導體裝置，其中在上述晶片狀半導體元件被覆晶安裝於上述配線基板之狀態下，上述複數個突起物之各突起物之前端不到達上述配線基板。 The semiconductor device according to claim 1, wherein in a state in which the wafer-like semiconductor element is flip-chip mounted on the wiring board, the leading end of each of the plurality of protrusions does not reach the wiring board. 如請求項1之半導體裝置，其中設置於上述配線基板之上述複數個焊料凸塊之各者，與設置於晶片狀半導體元件之複數個焊料凸塊中對應的焊料凸塊融合。 The semiconductor device of claim 1, wherein each of the plurality of solder bumps provided on the wiring board is fused with a corresponding solder bump among the plurality of solder bumps provided on the wafer-like semiconductor element. 如請求項1之半導體裝置，其中上述底部填充材料被統一塗佈於上述配線基板上。 The semiconductor device of claim 1, wherein the underfill material is uniformly coated on the wiring substrate. 如請求項1之半導體裝置，其中上述底部填充材料具有助銲劑功能。 The semiconductor device of claim 1, wherein the underfill material has a flux function. 一種晶片狀半導體元件，其係覆晶安裝於配線基板上者，且具有複數個焊料凸塊及複數個突起物；且上述複數個焊料凸塊與上述複數個突起物之各者設置於上述晶片狀半導體元件；上述面與上述配線基板對向；上述複數個焊料凸塊與上述複數個突起物之各者包含絕緣性材料；上述複數個突起物之第1突起物組設置於上述晶片狀半導體元件之上述面之中央區域；上述複數個突起物之第2突起物組設置於上述晶片狀半導體元件之上述面之周邊區域；上述周邊區域包圍上述中央區域；上述第1突起物組之各者之尺寸較上述第2突起物組之各者之尺寸更大；上述第1突起物組之密度較上述第2突起物組之密度更高； 上述配線基板包含底部填充材料。 A wafer-like semiconductor device, which is flip-chip mounted on a wiring substrate, and has a plurality of solder bumps and a plurality of protrusions; and each of the plurality of solder bumps and the plurality of protrusions is provided on the chip the above-mentioned surface is opposite to the above-mentioned wiring board; each of the above-mentioned plurality of solder bumps and the above-mentioned plurality of protrusions includes an insulating material; the first group of protrusions of the plurality of protrusions is provided on the wafer-shaped semiconductor the central area of the above-mentioned surface of the device; the second group of protrusions of the plurality of protrusions is provided in the peripheral area of the above-mentioned surface of the wafer-like semiconductor element; the above-mentioned peripheral area surrounds the above-mentioned central area; each of the above-mentioned first group of protrusions The size is larger than the size of each of the above-mentioned second group of protrusions; the density of the above-mentioned first group of protrusions is higher than the density of the above-mentioned second group of protrusions; The above-mentioned wiring board contains an underfill material. 如請求項6之晶片狀半導體元件，其中在上述晶片狀半導體元件被覆晶安裝於上述配線基板之狀態下，上述複數個突起物之各突起物之前端不到達上述配線基板。 The wafer-like semiconductor element according to claim 6, wherein in a state where the wafer-like semiconductor element is flip-chip mounted on the wiring board, the leading ends of each of the plurality of protrusions do not reach the wiring board. 如請求項6之晶片狀半導體元件，其中在上述晶片狀半導體元件之上述面之配置上述複數個突起物之區域，以一定之密度設置有突起物。 The wafer-like semiconductor element according to claim 6, wherein the projections are provided at a constant density in a region where the plurality of projections are arranged on the surface of the wafer-like semiconductor element. 如請求項6之晶片狀半導體元件，其中上述複數個突起物之相鄰之突起物間之間隙，橫穿上述晶片狀半導體元件之上述面之區域。 The wafer-like semiconductor element according to claim 6, wherein the gaps between the adjacent protrusions of the plurality of protrusions traverse the area of the surface of the wafer-like semiconductor element. 如請求項6之晶片狀半導體元件，其中在上述晶片狀半導體元件之上述面設置有相同形狀之突起物。 The wafer-like semiconductor element according to claim 6, wherein protrusions of the same shape are provided on the surface of the wafer-like semiconductor element. 如請求項6之晶片狀半導體元件，其中上述複數個突起物之上述第1突起物組之突起物之形狀與上述複數個突起物之上述第2突起物組之突起物之形狀不同。 The wafer-like semiconductor device of claim 6, wherein the shape of the protrusions of the first protrusion group of the plurality of protrusions is different from the shape of the protrusions of the second protrusion group of the plurality of protrusions. 如請求項6之晶片狀半導體元件，其上述複數個突起物之上述第1突起物組之突起物之高度與上述複數個突起物之上述第2突起物組之突起物之高度不同。 The wafer-like semiconductor device according to claim 6, wherein the height of the protrusions of the first protrusion group of the plurality of protrusions is different from the height of the protrusions of the second protrusion group of the plurality of protrusions. 如請求項6之晶片狀半導體元件，其中上述複數個突起物之各突起物越遠離上述晶片狀半導體元件之上述面，則形狀越變小。 The wafer-like semiconductor element according to claim 6, wherein the shape of each of the plurality of protrusions becomes smaller as the protrusions are farther away from the surface of the wafer-like semiconductor element. 如請求項6之晶片狀半導體元件，其中上述複數個突起物係對稱形狀。 The wafer-like semiconductor device according to claim 6, wherein the plurality of protrusions are symmetrical in shape. 如請求項6之晶片狀半導體元件，其中上述複數個突起物係非對稱形狀。 The wafer-like semiconductor device of claim 6, wherein the plurality of protrusions are asymmetrically shaped. 一種電子機器，其係包含半導體裝置者，該半導體裝置含有配線基板、及覆晶安裝於上述配線基板上之晶片狀半導體元件；且上述晶片狀半導體元件在晶片狀半導體元件之面包含複數個焊料凸塊、及複數個突起物；上述面與上述配線基板對向；上述複數個焊料凸塊與上述複數個突起物之各者包含絕緣性材料；上述複數個突起物之第1突起物組設置於上述晶片狀半導體元件之上述面之中央區域；上述複數個突起物之第2突起物組設置於上述晶片狀半導體元件之上述面之周邊區域；上述周邊區域包圍上述中央區域；上述第1突起物組之各者之尺寸較上述第2突起物組之各者之尺寸更大；上述第1突起物組之密度較上述第2突起物組之密度更高；上述配線基板包含底部填充材料。 An electronic device including a semiconductor device including a wiring board and a wafer-like semiconductor element flip-chip mounted on the wiring board; and the wafer-like semiconductor element includes a plurality of solders on the surface of the wafer-like semiconductor element bumps, and a plurality of protrusions; the surface facing the wiring board; each of the plurality of solder bumps and the plurality of protrusions includes an insulating material; the first protrusion group of the plurality of protrusions is provided in the central area of the surface of the wafer-like semiconductor element; the second protrusion group of the plurality of protrusions is provided in the peripheral area of the surface of the wafer-like semiconductor element; the peripheral area surrounds the central area; the first protrusions The size of each of the groups is larger than that of the second group of protrusions; the density of the first group of protrusions is higher than that of the second group of protrusions; the wiring substrate includes an underfill material.
TW107103153A 2017-02-17 2018-01-30 Semiconductor device, wafer-like semiconductor element, electronic apparatus including semiconductor device, and manufacturing method of semiconductor device TWI759413B (en)

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