JPH09275162A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH09275162A
JPH09275162A JP10458596A JP10458596A JPH09275162A JP H09275162 A JPH09275162 A JP H09275162A JP 10458596 A JP10458596 A JP 10458596A JP 10458596 A JP10458596 A JP 10458596A JP H09275162 A JPH09275162 A JP H09275162A
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
electrode
protruding
protruding electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10458596A
Other languages
Japanese (ja)
Inventor
Yoshio Miura
義男 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Japan Ltd
Original Assignee
Nippon Motorola Ltd
Motorola Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Motorola Ltd, Motorola Japan Ltd filed Critical Nippon Motorola Ltd
Priority to JP10458596A priority Critical patent/JPH09275162A/en
Publication of JPH09275162A publication Critical patent/JPH09275162A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Abstract

PROBLEM TO BE SOLVED: To prevent a fail of a bump electrode due to a thermal stress by a difference in the heat swelling coefficient of an IC chip and a chip support substrate and a mounting substrate in a semiconductor device in which the IC chip is provided on one face side of the chip support substrate and a number of bump electrodes are provided on the other face side thereof. SOLUTION: In a bump electrode 5A near an outer peripheral edge 23 of an IC chip out of a number of bump electrodes 5 of a chip support substrate 3, for example, an In-Sn low melting point alloy having the melting point at 177 deg.C is used, and in the other bump electrode 5B, in order to secure a mechanical strength between a semiconductor device and a mounting substrate, for example, a Pb-Sn alloy having a melting point at 255 deg.C is used. Incidentally, the bump electrode 5A has the same effect even if using gold instead of the low melting alloy.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、例えば球状あるい
は円柱状の突起電極を、チップ支持基板に半導体集積回
路チップが設けられた面と反対側の面に配列した構造、
または半導体集積回路チップ上に前記突起電極を配列し
た構造の半導体装置及びその製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure in which, for example, spherical or columnar protruding electrodes are arranged on the surface opposite to the surface on which a semiconductor integrated circuit chip is provided on a chip supporting substrate,
Alternatively, the present invention relates to a semiconductor device having a structure in which the protruding electrodes are arranged on a semiconductor integrated circuit chip and a method for manufacturing the semiconductor device.

【0002】[0002]

【従来の技術】半導体パッケージの代表的なものとして
は、半導体ウエハから切り出されたIC(半導体集積回
路)チップ(ダイ)をダイパッドなどと呼ばれているチ
ップ支持基板上にボンディングすると共に、チップ支持
基板の周囲に配設された多数の外部リードとICチップ
とをワイヤで接続し、全体をモールドした構造のものが
知られている。ところで最近においてBGA(Ball
Grid Array)型パッケージチップあるいは
LGA(Land Grid Array)型パッケー
ジチップなどと呼ばれる半導体装置が実用化されつつあ
る。
2. Description of the Related Art As a typical semiconductor package, an IC (semiconductor integrated circuit) chip (die) cut out from a semiconductor wafer is bonded onto a chip support substrate called a die pad and the chip support is also provided. There is known a structure in which a large number of external leads arranged around the substrate and an IC chip are connected by wires and the whole is molded. By the way, recently, BGA (Ball
Semiconductor devices called “Grid Array” type package chips or LGA (Land Grid Array) type package chips are being put to practical use.

【0003】この種の半導体装置は、チップ支持基板の
一面にICチップを搭載し、外部リードに代ってチップ
支持基板の他面に多数の突起電極を格子状に配列して構
成されるものである。図10はこの半導体装置をチップ
支持基板11の他面側から見た図であり、ICチップの
外周縁を便宜上実線12として示してある。突起電極1
3は例えばPb−Sn合金で作られ、突起電極13とI
Cチップとは、チップ支持基板11の一面側のボンディ
ングワイヤ及びチップ支持基板11内の配線によって電
気的に接続されている。
This type of semiconductor device is constructed by mounting an IC chip on one surface of a chip supporting substrate and arranging a large number of protruding electrodes in a grid pattern on the other surface of the chip supporting substrate instead of external leads. Is. FIG. 10 is a view of this semiconductor device viewed from the other surface side of the chip support substrate 11, and the outer peripheral edge of the IC chip is shown as a solid line 12 for convenience. Protruding electrode 1
3 is made of, for example, a Pb-Sn alloy, and has projection electrodes 13 and I
The C chip is electrically connected by a bonding wire on one surface side of the chip support substrate 11 and a wiring in the chip support substrate 11.

【0004】このような半導体装置によれば、突起電極
13が面状に並ぶので電極の数を多くすることができ、
このためICチップの集積度を高くしながらパッケージ
全体を小型化できるという利点があり、また電極とIC
チップとの距離を短くでき、信号の授受の高速化を図る
ことができるという利点もある。
According to such a semiconductor device, since the protruding electrodes 13 are arranged in a plane, the number of electrodes can be increased,
Therefore, there is an advantage that the entire package can be downsized while increasing the degree of integration of the IC chip, and the electrode and the IC
There is also an advantage that the distance to the chip can be shortened and the speed of signal transfer can be increased.

【0005】[0005]

【発明が解決しようとする課題】しかしながらBGAや
LGAタイプなどの半導体装置は、基板に実装して温度
サイクル試験を行うと、ICチップの外周縁付近の突起
電極が不良になりやすい傾向がある。その原因は、IC
チップの材質がシリコンであり、チップ支持基板及び実
装基板の材質がガラスエポキシであるため、これらの熱
膨張係数が異なり、ICチップ、チップ支持基板、突起
電極及び実装基板との間の各界面に熱歪に応じた応力が
加わることによると考えられる。
However, when a semiconductor device such as a BGA or LGA type is mounted on a substrate and subjected to a temperature cycle test, the protruding electrodes near the outer peripheral edge of the IC chip tend to be defective. The cause is IC
Since the material of the chip is silicon and the material of the chip supporting board and the mounting board is glass epoxy, they have different thermal expansion coefficients, so that each interface between the IC chip, the chip supporting board, the protruding electrode and the mounting board is different. It is considered that this is due to the stress applied according to the thermal strain.

【0006】そしてICチップの外周縁に相当する領域
において最も大きな応力が発生し、このためチップ支持
基板の他面側の配線の端部である例えば銅箔よりなる電
極パッドと突起電極との圧着接続部や、突起電極と実装
基板との接続部が剥れたり、剥れるに至らなくとも接触
抵抗が大きくなることがある。このような現象は、IC
チップの外周縁付近において最も起こりやすく、ICチ
ップの配置領域の内方側に向かう程緩和される。
The largest stress is generated in the area corresponding to the outer peripheral edge of the IC chip, and therefore the electrode pad made of, for example, copper foil, which is the end of the wiring on the other surface of the chip support substrate, is crimped to the protruding electrode. The contact resistance may increase even if the connection part or the connection part between the protruding electrode and the mounting substrate is peeled off or is not peeled off. Such a phenomenon is caused by IC
It is most likely to occur in the vicinity of the outer peripheral edge of the chip, and is relaxed toward the inner side of the IC chip arrangement region.

【0007】ところで半導体装置は過酷な環境に置かれ
る場合があり、例えば自動車に組み込まれた場合には1
25℃もの高温になる。従って上述の半導体装置を用い
ると電極不良が発生するおそれがあり、信頼性が低いと
いう問題がある。
A semiconductor device may be placed in a harsh environment. For example, when the semiconductor device is incorporated in an automobile,
It can reach temperatures as high as 25 ° C. Therefore, when the above-described semiconductor device is used, there is a possibility that an electrode defect may occur and the reliability is low.

【0008】本発明はこのような事情の下になされたも
のであり、その目的は、多数の突起電極を備えた半導体
装置において高い信頼性を得ることを目的とする。
The present invention has been made under such circumstances, and an object thereof is to obtain high reliability in a semiconductor device having a large number of protruding electrodes.

【0009】[0009]

【課題を解決するための手段】本発明は、半導体集積回
路チップと、この半導体集積回路チップに電気的に接続
された多数の突起電極とを備えた半導体装置、例えば突
起電極をチップ支持基板における半導体集積回路チップ
が設けられた面と反対側の面に配列した構造、または半
導体集積回路チップ上に前記突起電極を配列した構造の
半導体装置を対象としており、前記多数の突起電極のう
ちの一部の突起電極を他の突起電極とは異なる材質によ
り構成したことを特徴とする。
According to the present invention, there is provided a semiconductor device including a semiconductor integrated circuit chip and a large number of protruding electrodes electrically connected to the semiconductor integrated circuit chip, for example, a protruding electrode on a chip support substrate. The present invention is directed to a semiconductor device having a structure in which the semiconductor integrated circuit chip is arranged on a surface opposite to the surface on which the semiconductor integrated circuit chip is provided, or a structure in which the protruding electrodes are arranged on the semiconductor integrated circuit chip. It is characterized in that the protruding electrodes of the part are made of a material different from that of the other protruding electrodes.

【0010】ここで突起電極の材質を異ならせるとは、
例えば半導体集積回路チップの高温になる領域に対応す
る領域の突起電極を他の突起電極よりも熱伝導度の高い
材質により構成する場合、あるいは一部の突起電極を他
の突起電極よりも抵抗値の低い材質により構成する場合
などが挙げあげられる。
Here, different materials for the protruding electrodes mean that
For example, when the protruding electrodes in the area corresponding to the high temperature area of the semiconductor integrated circuit chip are made of a material having higher thermal conductivity than other protruding electrodes, or when some protruding electrodes have a higher resistance value than other protruding electrodes. The case where it is made of a material having a low

【0011】また本発明は、前記半導体装置のうち、突
起電極をチップ支持基板における半導体集積回路チップ
が設けられた面と反対側の面に配列した構造のものにお
いて、前記多数の突起電極のうち、前記半導体集積回路
チップの外周縁付近に位置する突起電極を粘性の高い材
質により構成したものも含まれ、この場合には、熱歪に
よる応力を突起電極により吸収して突起電極の不良を防
止できる効果がある。粘性の高い材質の一例としては、
低融点金属を挙げることができる。
In the semiconductor device according to the present invention, the protruding electrodes are arranged on the surface of the chip supporting substrate opposite to the surface on which the semiconductor integrated circuit chip is provided. The semiconductor integrated circuit chip also includes a protruding electrode located near the outer peripheral edge made of a highly viscous material. In this case, the protruding electrode absorbs the stress due to thermal strain to prevent the defective protruding electrode. There is an effect that can be done. As an example of a highly viscous material,
A low melting point metal can be mentioned.

【0012】さらに本発明は、こうした半導体装置を製
造する方法も対象としており、その方法は、第1の吸着
用孔が形成された第1の真空吸着装置を用い、前記第1
の吸着用孔に第1の突起電極となる粒状体を真空吸着さ
せて前記電極パッドに圧着させる工程と、第2の吸着用
孔が形成された第2の真空吸着装置を用い、前記第2の
吸着用孔に第2の突起電極となる粒状体を真空吸着させ
て残りの電極パッドに圧着させる工程と、を含むことを
特徴とする。
Further, the present invention is also directed to a method of manufacturing such a semiconductor device, which method uses a first vacuum suction device having a first suction hole, and uses the first vacuum suction device.
A step of vacuum-adsorbing the granular body to be the first protruding electrode to the suction hole of the second suction electrode and press-bonding it to the electrode pad; and using the second vacuum suction device in which the second suction hole is formed, A step of vacuum-adsorbing the granular body to be the second protruding electrode in the adsorption hole and press-bonding it to the remaining electrode pad.

【0013】[0013]

【発明の実施の形態】本発明の第1の実施の形態に係る
半導体装置を図1及び図2に示す。ただし突起電極の数
は、図の制約から対応していない。図中2はICチップ
(ダイ)であり、チップ支持基板3の一面側にペースト
剤によりボンディングされている。チップ支持基板3
は、ガラスエポキシよりなり、一面側及び他面側に例え
ば銅箔よりなる電極パッド31、32が形成されている
と共に、これら電極パッド31、32間はチップ支持基
板3内に形成された配線(図示せず)により電気的に接
続されている。ICチップ2の電極パッド21とチップ
支持基板3の一面側の電極パッド31とはボンディング
ワイヤ22により接続されており、ICチップ2及びボ
ンディングワイヤ22を含む領域は、モールド樹脂4に
より成型されている。
1 and 2 show a semiconductor device according to a first embodiment of the present invention. However, the number of protruding electrodes does not correspond to the limitation of the figure. Reference numeral 2 in the drawing denotes an IC chip (die), which is bonded to one surface side of the chip support substrate 3 with a paste agent. Chip support substrate 3
Is made of glass epoxy, and electrode pads 31 and 32 made of, for example, copper foil are formed on one surface side and the other surface side, and a wiring formed in the chip support substrate 3 between these electrode pads 31 and 32 ( (Not shown) electrically connected. The electrode pad 21 of the IC chip 2 and the electrode pad 31 on the one surface side of the chip support substrate 3 are connected by the bonding wire 22, and the region including the IC chip 2 and the bonding wire 22 is molded by the molding resin 4. .

【0014】前記チップ支持基板3の他面側の電極パッ
ド32は例えば格子状に配列されており、これら電極パ
ッド32には、多数の球状の突起電極5が圧着されてい
る。これら突起電極5のうち、ICチップ2の外周縁部
23(図2では便宜上実線で示してある)付近の斜線で
示す第1の突起電極5Aについては、例えばInを48
%、Snを52%含む、融点が117℃である低融点の
In−Sn合金が用いられている。また突起電極5A以
外の白抜きで示す第2の突起電極5Bについては、Pb
を60%、Snを40%含む、融点が225℃であるP
b−Sn合金が用いられている。
The electrode pads 32 on the other surface side of the chip support substrate 3 are arranged, for example, in a grid pattern, and a large number of spherical protruding electrodes 5 are pressure-bonded to these electrode pads 32. Of these protruding electrodes 5, for the first protruding electrode 5A shown by the diagonal lines near the outer peripheral edge portion 23 of the IC chip 2 (indicated by a solid line in FIG. 2 for convenience), for example, In is 48
%, Sn, 52%, and a low melting point In—Sn alloy having a melting point of 117 ° C. is used. For the second protruding electrodes 5B other than the protruding electrodes 5A, which are shown in white, Pb
Containing 60% of Sn and 40% of Sn and having a melting point of 225 ° C.
A b-Sn alloy is used.

【0015】これら突起電極5は、各々の球径が例えば
およそ0.2〜0.65mm程度であり、縦横の配列間
隔はおよそ0.5〜1.5mm程度である。突起電極5
A、5Bをチップ支持基板3の他面に圧着する方法は、
例えば図3及び図4に示す工程により行われる。図中6
Aは第1の真空吸着装置であり、第1の吸着孔61が配
列された吸着プレート62を備えている。第1の吸着孔
61は、チップ支持基板3の他面側の電極パッド32の
うち、ICチップ2の外周縁部付近の電極パッド32の
配列に対応して配列されている。
The spherical diameter of each of the protruding electrodes 5 is, for example, about 0.2 to 0.65 mm, and the vertical and horizontal arrangement intervals are about 0.5 to 1.5 mm. Protruding electrode 5
The method of crimping A and 5B to the other surface of the chip support substrate 3 is as follows.
For example, the steps shown in FIGS. 3 and 4 are performed. 6 in the figure
Reference numeral A denotes a first vacuum suction device, which includes a suction plate 62 in which first suction holes 61 are arranged. The first suction holes 61 are arranged corresponding to the arrangement of the electrode pads 32 on the other surface side of the chip support substrate 3 near the outer peripheral edge of the IC chip 2.

【0016】また図中6Bは、第2の真空吸着装置であ
り、第2の吸着孔63が配列された吸着プレート64を
備えている。第2の吸着孔63は、チップ支持基板3の
他面側の電極パッド32のうちICチップ2の外周縁部
付近の電極パッド32以外の電極パッド32の配列に対
応して配列されている。
Reference numeral 6B in the drawing is a second vacuum suction device, which is equipped with a suction plate 64 in which the second suction holes 63 are arranged. The second suction holes 63 are arranged corresponding to the arrangement of the electrode pads 32 on the other surface side of the chip support substrate 3 other than the electrode pads 32 near the outer peripheral edge of the IC chip 2.

【0017】先ず第1の真空吸着装置6Aを用い、図3
に示すように第1の吸着孔61に第1の突起電極6Aと
なる前記In−Sn合金の粒状体例えば球状体60Aを
真空吸着し、真空吸着装置6Aをチップ支持基板3側に
押圧して球状体60AをICチップ2の外周縁付近の電
極パッド32に圧着する。その後真空吸着を解除し、真
空吸着装置6Aをチップ支持基板3から離し、こうして
第1の突起電極6Aをチップ支持基板3に形成する。
First, using the first vacuum suction device 6A, as shown in FIG.
As shown in FIG. 4, the In—Sn alloy particles, eg, spherical bodies 60A, which become the first protruding electrodes 6A, are vacuum-sucked in the first suction holes 61, and the vacuum suction device 6A is pressed toward the chip support substrate 3 side. The spherical body 60A is pressure-bonded to the electrode pad 32 near the outer peripheral edge of the IC chip 2. Thereafter, the vacuum suction is released, the vacuum suction device 6A is separated from the chip support substrate 3, and thus the first protruding electrode 6A is formed on the chip support substrate 3.

【0018】次いで第2の真空吸着装置6Bを用い、第
2の吸着孔63に第2の突起電極6Bとなる前記Pb−
Sn合金の粒状体例えば球状体60Bを真空吸着し、真
空吸着装置6Bをチップ支持基板3側に押圧して球状体
60Bを、残りの電極パッド32に圧着する。その後真
空吸着を解除し、真空吸着装置6Bをチップ支持基板3
から離し、こうして第2の突起電極6Bをチップ支持基
板3に形成する。球状体60A、60Bの圧着時には、
チップ支持基板3をおよそ200℃に加熱する。
Next, using the second vacuum suction device 6B, the Pb- which becomes the second protruding electrode 6B in the second suction hole 63 is formed.
A granular body of Sn alloy, for example, a spherical body 60B is vacuum-sucked, and the vacuum suction device 6B is pressed against the chip support substrate 3 side to press-bond the spherical body 60B to the remaining electrode pad 32. Then, the vacuum suction is released, and the vacuum suction device 6B is attached to the chip support substrate 3
And the second protruding electrode 6B is thus formed on the chip support substrate 3. When pressing the spherical bodies 60A and 60B,
The chip support substrate 3 is heated to about 200 ° C.

【0019】上述の半導体装置を基板に実装し、突起電
極5の温度が例えば100℃を越える高温環境に半導体
装置を置くと、ICチップ2とチップ支持基板3及び実
装基板との間の熱膨張係数の差異により、ICチップ2
の外周縁付近において実装基板とICチップ2との間に
熱歪みによる大きな応力が発生するが、ICチップ2の
外周縁付近の突起電極5Aについては融点が117℃の
低融点合金で作られているため粘性が高く、従って前記
応力の一部が突起電極5Aに吸収されてこの突起電極5
Aが変形する。この結果突起電極5とチップ支持基板3
との界面や突起電極5と実装基板との界面に加わる応力
は小さくなるので、突起電極5Aが実装基板やチップ支
持基板3から剥れたり、圧着接続部の接触抵抗が大きく
なったりするおそれがない。
When the semiconductor device described above is mounted on a substrate and the semiconductor device is placed in a high temperature environment where the temperature of the projecting electrodes 5 exceeds, for example, 100 ° C., thermal expansion between the IC chip 2 and the chip support substrate 3 and the mounting substrate is performed. IC chip 2 due to the difference in coefficient
Although a large stress is generated between the mounting substrate and the IC chip 2 near the outer peripheral edge of the IC chip 2, the protruding electrode 5A near the outer peripheral edge of the IC chip 2 is made of a low melting point alloy having a melting point of 117 ° C. Therefore, the viscosity is high, so that part of the stress is absorbed by the protruding electrode 5A and
A deforms. As a result, the protruding electrode 5 and the chip support substrate 3
Since the stress applied to the interface between the mounting substrate and the chip supporting substrate 3 is small, the stress applied to the interface between the mounting substrate and the chip supporting substrate 3 is small, and the stress applied to the interface between the mounting electrode and the mounting substrate is small. Absent.

【0020】そして第1の突起電極5A以外の第2の突
起電極5Bについては融点の高い合金を用いており、粘
性が小さいので、基板への半導体装置の実装のために必
要な特性例えば高温下における機械的強度の確保は、こ
れら第2の突起電極5Bに受け持たせており、従って電
極不良が起こらず、機械的強度も確保されているため半
導体装置の信頼性が高いという効果がある。
An alloy having a high melting point is used for the second protruding electrodes 5B other than the first protruding electrodes 5A, and since the viscosity is low, the characteristics required for mounting the semiconductor device on the substrate, for example, under high temperature. The second projecting electrode 5B is responsible for ensuring the mechanical strength of the semiconductor device. Therefore, the electrode failure does not occur and the mechanical strength is ensured, so that the semiconductor device has an effect of high reliability.

【0021】このように電極間で、材質を異ならせる構
成は、1枚のプレートを打ち抜いてチップ支持基板(ダ
イパッド)及び外部リードを作製するタイプの半導体装
置では採用することができないが、突起電極をチップ支
持基板に配列するタイプの半導体装置であれば採用する
ことができ、上述実施の形態は、この点に着目して、I
Cチップ2の外周縁部付近の突起電極5Aについてだけ
低融点合金で形成するようにしたものである。この場合
本発明では、低融点合金に限らずもともと粘性の大きい
材質例えば金により第1の突起電極5Aを形成してもよ
く、この場合全ての突起電極5を金で構成する場合に比
べ、コスト的に有利である。また第1の突起電極5Aを
低融点合金で形成するにあたっては、半導体装置の使用
時において突起電極5Aの粘性が大きくなる材質を選定
すればよく、突起電極5の機械的強度に問題がなけれ
ば、第1の突起電極5Aのみならず全部の突起電極を低
融点合金で作ってもよい。なお突起電極の形状は、球状
に限らず円柱状などであってもよい。
Such a configuration in which the materials are made different between the electrodes cannot be adopted in a semiconductor device of a type in which one plate is punched out to form a chip support substrate (die pad) and external leads, but the protruding electrode is used. Any semiconductor device of the type in which the chips are arranged on the chip support substrate can be adopted. In the above-described embodiment, focusing on this point,
Only the protruding electrode 5A near the outer peripheral edge of the C chip 2 is formed of a low melting point alloy. In this case, in the present invention, not only the low melting point alloy but also the material having a large viscosity such as gold may be used to form the first protruding electrode 5A. In this case, compared to the case where all the protruding electrodes 5 are made of gold, the cost is low. Is advantageous. Further, when forming the first protruding electrode 5A with a low melting point alloy, a material that increases the viscosity of the protruding electrode 5A when the semiconductor device is used may be selected, and there is no problem in the mechanical strength of the protruding electrode 5. Not only the first protruding electrodes 5A but all the protruding electrodes may be made of a low melting point alloy. The shape of the protruding electrode is not limited to a spherical shape, and may be a cylindrical shape or the like.

【0022】ここで本発明の効果を確認するために次の
ような試験を行った。第1の突起電極5Aの材質とし
て、Pbが38%、Snが62%含まれる、融点183
℃のPb−Sn合金を用いた半導体装置を実施例1と
し、第1の突起電極5Aの材質としてInが48%、S
nが52%含まれる融点117℃のIn−Sn合金を用
いた半導体装置を実施例2とした。その他の突起電極
(第2の突起電極5B)の材質としてはPbが60%、
Snが40%含まれる、融点が225℃のPb−Sn合
金を用いた。またこのPb−Sn合金により全ての突起
電極を形成した半導体装置を比較例とした。
Here, in order to confirm the effect of the present invention, the following test was conducted. The material of the first protruding electrode 5A contains 38% of Pb and 62% of Sn, and has a melting point 183.
A semiconductor device using a Pb-Sn alloy at a temperature of C is used as Example 1 and the first protruding electrode 5A is made of In of 48% and S
A semiconductor device using an In—Sn alloy with a melting point of 117 ° C. containing 52% of n is set as Example 2. As the material of the other protruding electrode (second protruding electrode 5B), Pb is 60%,
A Pb—Sn alloy containing 40% Sn and having a melting point of 225 ° C. was used. In addition, a semiconductor device in which all the protruding electrodes were formed of this Pb-Sn alloy was used as a comparative example.

【0023】これら3種類の半導体装置を各種類毎に5
0個ずつ用意してプリント基板に実装し、これらを−6
5℃の低温環境に10分間置いた後、150℃の高温環
境に10分間置き、−65℃→150℃を1回の温度サ
イクル試験として突起電極の電極不良が起こるまで温度
サイクル試験を繰り返した。突起電極の電極不良が起こ
った温度試験の回数を、突起電極の材質と共に図5に示
す。
Each of these three types of semiconductor devices has five types.
Prepare 0 each and mount it on a printed circuit board.
After being placed in a low temperature environment of 5 ° C. for 10 minutes, placed in a high temperature environment of 150 ° C. for 10 minutes, and a temperature cycle test of −65 ° C. → 150 ° C. was performed once, and the temperature cycle test was repeated until electrode failure of the protruding electrode occurred. . FIG. 5 shows the number of temperature tests in which the electrode failure of the bump electrode occurred, together with the material of the bump electrode.

【0024】図5から分かるように、比較例ではICチ
ップの外周縁付近の突起電極5Aとして融点が225℃
もの高いPb−Sn合金を使用しているため、高温時に
おいて突起電極5Aの粘性は小さいので、既述した界面
に大きな熱応力が作用し、温度サイクル試験を2900
〜3500回行った時点で電極不良が発生している。そ
の他の突起電極5Bについては、ICチップの外周縁付
近程熱応力が大きくないため、試験回数が4600〜5
700回まで耐えているが、半導体装置全体の耐久性と
しては、突起電極5Aの2900〜3500回で決まっ
てしまう。
As can be seen from FIG. 5, in the comparative example, the melting point of the protruding electrode 5A near the outer peripheral edge of the IC chip is 225 ° C.
Since the protrusion electrode 5A has a small viscosity at a high temperature because a high Pb-Sn alloy is used, a large thermal stress acts on the interface described above, and the temperature cycle test is performed at 2900.
An electrode defect has occurred at a point of time up to 3500 times. Regarding the other protruding electrodes 5B, the thermal stress is not so large as in the vicinity of the outer peripheral edge of the IC chip.
Although it withstands up to 700 times, the durability of the entire semiconductor device is determined by 2900 to 3500 times of the protruding electrode 5A.

【0025】これに対し実施例1、2では夫々突起電極
5Aとして融点が183℃及び117℃の低融点合金を
用いているため、高温時において突起電極5Aの粘性が
大きく、このため熱応力がこの突起電極5Aに吸収され
る。この結果電極不良に至るまでの温度サイクル試験の
回数が実施例1では3700〜4400回と比較例に比
べてかなり大きくなり、また実施例2では6000回行
っても電極不良は発生しないため、本発明の半導体装置
によれば耐久性が大きく、高い信頼性が得られることが
分かる。
On the other hand, in Examples 1 and 2, since low melting point alloys having melting points of 183 ° C. and 117 ° C. are used as the protruding electrodes 5A, respectively, the protruding electrodes 5A have large viscosity at high temperature, and therefore thermal stress is high. It is absorbed by the protruding electrode 5A. As a result, the number of temperature cycle tests leading to electrode failure is 3700 to 4400 times in Example 1, which is considerably larger than that in Comparative Example, and in Example 2, no electrode failure occurs even after 6000 times. It can be seen that the semiconductor device of the present invention has high durability and high reliability.

【0026】次に本発明の第2及び第3の実施の形態に
ついて夫々図6及び図7を参照しながら説明する。図6
に示す半導体装置では、チップ支持基板3の他面側の突
起電極5のうちICチップの高温になる領域に対応する
領域つまり高温になる領域を投影した領域に位置する突
起電極5C(斜線で示す突起電極)を、熱放散電極をな
す熱伝導度の高い金属例えばAu、Ag、Cuなどによ
り構成し、その他の突起電極5の材質については熱放散
の要請が少ないため熱伝導度の低い金属、例えば既述の
Pb(60%)−Sn(40%)合金を用いる。このよ
うに熱放散電極を用いることにより半導体装置の信頼性
が向上し、また熱伝導度の高い金属は高価であることか
ら、高温になる領域だけ熱放散電極を用いることにより
コストアップを抑えることができる。
Next, second and third embodiments of the present invention will be described with reference to FIGS. 6 and 7, respectively. FIG.
In the semiconductor device shown in FIG. 5, the protruding electrode 5C (indicated by diagonal lines) is located in a region of the protruding electrode 5 on the other surface side of the chip support substrate 3 that corresponds to the region of the IC chip where the temperature becomes high, that is, the region where the temperature becomes high. The protruding electrode) is made of a metal having a high thermal conductivity, such as Au, Ag, or Cu, which forms a heat-dissipating electrode, and other materials of the protruding electrode 5 have a low thermal conductivity because there is little demand for heat dissipation, For example, the Pb (60%)-Sn (40%) alloy described above is used. Thus, the reliability of the semiconductor device is improved by using the heat-dissipating electrode, and the metal having high thermal conductivity is expensive. Therefore, the cost increase can be suppressed by using the heat-dissipating electrode only in the high temperature region. You can

【0027】更に図7に示す半導体装置では、チップ支
持基板3の他面側の突起電極5のうち信号の伝送速度を
早くする要請のある伝送路の突起電極5D(斜線で示す
突起電極)については、低抵抗値の金属例えば金により
構成し、その他の突起電極5の材質については、例えば
前記Pb(60%)−Sn(40%)合金を用いる。こ
のように構成すれば信号伝送の高速化を図ることができ
るので高速処理を達成することができ、また金などの材
質は高価であるため、必要な個所だけ金を用いることに
よりコストアップを抑えることができる。突起電極5と
して金を用いれば低抵抗化を図れるが、低抵抗突起電極
としては、信号伝送の高速化を要請される個所に限ら
ず、信号レベルが小さい個所についても、このレベルを
落とさないようにするために用いることが有効である。
Further, in the semiconductor device shown in FIG. 7, of the protruding electrodes 5 on the other surface side of the chip support substrate 3, the protruding electrodes 5D (projected electrodes shown by hatched lines) of the transmission line which are required to increase the signal transmission speed. Is made of a metal having a low resistance value, for example, gold, and as the material of the other protruding electrodes 5, for example, the Pb (60%)-Sn (40%) alloy is used. With this configuration, high-speed processing can be achieved because the signal transmission can be speeded up, and since materials such as gold are expensive, the cost increase can be suppressed by using gold only at necessary parts. be able to. Although resistance can be reduced by using gold as the protruding electrode 5, the low resistance protruding electrode is not limited to a portion where high speed signal transmission is required, and does not drop at a portion where a signal level is low. It is effective to use to

【0028】このように本発明は、多数の突起電極のう
ち、熱放散や信号の高速化などの要請が大きい個所につ
いては、必要に応じた材質を用いるようにしているが、
対象となる半導体装置としては、図8に示す第4の実施
の形態のように半導体ウエハから切り出したICチップ
7の電極パッド71に導電性の材質例えば金属よりなる
突起電極72を直接圧着した、FC(Flip Chi
p)などと呼ばれているタイプのものや、図9に示す第
5の実施の形態のようにICチップ8の表面に絶縁層8
1を形成し、この絶縁層81の表面に突起電極82を配
列して設けると共に、突起電極82とICチップ8の図
では見えない電極パッドとを絶縁層81内の配線により
電気的に接続した、DCA(Direct Chip
Attach)などと呼ばれているタイプのものなども
含まれる。図8の例では突起電極72A(黒で塗り潰し
たもの)を、高速伝送用とするため金で構成しており、
図9の例では、突起電極82A(黒で塗り潰したもの)
を、熱放散電極とするため金で構成している。
As described above, according to the present invention, of the many protruding electrodes, a material which is required is used for a portion where a demand for heat dissipation or speeding up of a signal is great.
As the target semiconductor device, as in the fourth embodiment shown in FIG. 8, a protruding electrode 72 made of a conductive material such as a metal is directly pressure-bonded to the electrode pad 71 of the IC chip 7 cut out from the semiconductor wafer. FC (Flip Chi
p) or the like, or the insulating layer 8 on the surface of the IC chip 8 as in the fifth embodiment shown in FIG.
1 is formed, and the protruding electrodes 82 are arranged and provided on the surface of the insulating layer 81, and the protruding electrodes 82 and the electrode pads of the IC chip 8 which are not visible in the drawing are electrically connected by the wiring in the insulating layer 81. , DCA (Direct Chip
Also included are types called Attach). In the example of FIG. 8, the protruding electrode 72A (painted in black) is made of gold for high-speed transmission,
In the example of FIG. 9, the protruding electrode 82A (painted in black)
Is made of gold to serve as a heat dissipation electrode.

【0029】[0029]

【発明の効果】以上のように本発明によれば、チップ支
持基板の他面側の突起電極のうちICチップの外周縁に
対応する領域の突起電極を粘性の高い材質で構成してい
るため、熱歪に応じた応力が突起電極で吸収されるた
め、突起電極の接触不良や剥がれを抑えることができ、
高い信頼性が得られる。また必要に応じて突起電極の材
質を他の突起電極の材質と異ならせているので、熱放散
性や低抵抗化などを確保しながらコストを低く抑えるこ
とができる。
As described above, according to the present invention, among the protruding electrodes on the other surface of the chip support substrate, the protruding electrodes in the region corresponding to the outer peripheral edge of the IC chip are made of a highly viscous material. Since the stress corresponding to the thermal strain is absorbed by the protruding electrode, it is possible to suppress the contact failure and peeling of the protruding electrode,
High reliability can be obtained. Moreover, since the material of the protruding electrode is made different from the material of the other protruding electrodes as needed, it is possible to keep the cost low while ensuring heat dissipation and low resistance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態に係る半導体装置を
示す縦断側面図である。
FIG. 1 is a vertical sectional side view showing a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第1の実施の形態に係る半導体装置を
示す底面図である。
FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment of the present invention.

【図3】本発明の第1の実施の形態に係る半導体装置の
製造工程を示す縦断側面図である。
FIG. 3 is a vertical cross-sectional side view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

【図4】本発明の第1の実施の形態に係る半導体装置の
製造工程を示す縦断側面図である。
FIG. 4 is a vertical cross-sectional side view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

【図5】本発明の効果を確認するために行った温度試験
結果を示す図表である。
FIG. 5 is a table showing the results of temperature tests conducted to confirm the effects of the present invention.

【図6】本発明の第2の実施の形態に係る半導体装置を
示す底面図である。
FIG. 6 is a bottom view showing a semiconductor device according to a second embodiment of the present invention.

【図7】本発明の第3の実施の形態に係る半導体装置を
示す底面図である。
FIG. 7 is a bottom view showing a semiconductor device according to a third embodiment of the present invention.

【図8】本発明の第4の実施の形態に係る半導体装置を
示す斜視図である。
FIG. 8 is a perspective view showing a semiconductor device according to a fourth embodiment of the present invention.

【図9】本発明の第5の実施の形態に係る半導体装置を
示す斜視図である。
FIG. 9 is a perspective view showing a semiconductor device according to a fifth embodiment of the present invention.

【図10】従来の半導体装置を示す底面図である。FIG. 10 is a bottom view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

2 集積回路チップ 21 電極パッド 22 ボンディングワイヤ 23 集積回路チップの外周縁 3 チップ支持基板 31、32 電極パッド 4 モールド樹脂 5 突起電極 5A 第1の突起電極 5B 第2の突起電極 6A 第1の真空吸着装置 6B 第2の真空吸着装置 61 第1の吸着孔 63 第2の吸着孔 5C、5D 突起電極 7、8 集積回路チップ 81 絶縁層 72、72A、82、82A 突起電極 2 integrated circuit chip 21 electrode pad 22 bonding wire 23 outer peripheral edge of integrated circuit chip 3 chip support substrate 31, 32 electrode pad 4 mold resin 5 protruding electrode 5A first protruding electrode 5B second protruding electrode 6A first vacuum adsorption Device 6B Second vacuum suction device 61 First suction hole 63 Second suction hole 5C, 5D Projection electrode 7,8 Integrated circuit chip 81 Insulating layer 72, 72A, 82, 82A Projection electrode

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路チップと、この半導体集
積回路チップに電気的に接続された多数の突起電極とを
備えた半導体装置において、 前記多数の突起電極のうちの一部の突起電極を他の突起
電極とは異なる材質により構成したことを特徴とする半
導体装置。
1. A semiconductor device comprising a semiconductor integrated circuit chip and a large number of protruding electrodes electrically connected to the semiconductor integrated circuit chip, wherein some of the plurality of protruding electrodes are replaced by other protruding electrodes. The semiconductor device is made of a material different from that of the bump electrode.
【請求項2】 多数の突起電極のうちの一部の突起電極
を他の突起電極よりも熱伝導度の高い材質により構成し
たことを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein some of the plurality of protruding electrodes are made of a material having higher thermal conductivity than the other protruding electrodes.
【請求項3】 多数の突起電極のうちの一部の突起電極
を他の突起電極よりも抵抗値の低い材質により構成した
ことを特徴とする請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein some of the plurality of protruding electrodes are made of a material having a resistance value lower than that of the other protruding electrodes.
【請求項4】 チップ支持基板の一面側に設けられた半
導体集積回路チップと、前記チップ支持基板の他面側に
設けられ、前記半導体集積回路チップに電気的に接続さ
れた多数の突起電極とを備えた半導体装置において、 前記多数の突起電極のうち、前記半導体集積回路チップ
の外周縁付近に位置する突起電極を粘性の高い材質によ
り構成したことを特徴とする半導体装置。
4. A semiconductor integrated circuit chip provided on one surface side of a chip support substrate, and a large number of protruding electrodes provided on the other surface side of the chip support substrate and electrically connected to the semiconductor integrated circuit chip. A semiconductor device comprising: a plurality of protruding electrodes, wherein the protruding electrodes located near the outer peripheral edge of the semiconductor integrated circuit chip are made of a highly viscous material.
【請求項5】 粘性の高い材質は、低融点金属であるこ
とを特徴とする請求項4記載の半導体装置。
5. The semiconductor device according to claim 4, wherein the highly viscous material is a low melting point metal.
【請求項6】 半導体集積回路チップと、この半導体集
積回路チップに電気的に接続され、各々電極支持面に形
成された電極パッドに圧着された多数の突起電極とを備
えた半導体装置において、 第1の吸着用孔が形成された第1の真空吸着装置を用
い、前記第1の吸着用孔に第1の突起電極となる粒状体
を真空吸着させて前記電極パッドに圧着させる工程と、 第2の吸着用孔が形成された第2の真空吸着装置を用
い、前記第2の吸着用孔に第2の突起電極となる粒状体
を真空吸着させて残りの電極パッドに圧着させる工程
と、を含むことを特徴とする半導体装置の製造方法。
6. A semiconductor device comprising: a semiconductor integrated circuit chip; and a plurality of projecting electrodes electrically connected to the semiconductor integrated circuit chip and crimped to electrode pads formed on an electrode supporting surface, respectively. Using a first vacuum suction device in which a first suction hole is formed, a step of vacuum-sucking a granular body to be a first protruding electrode in the first suction hole and crimping the granular body to the electrode pad; Using a second vacuum suction device in which two suction holes are formed, a step of vacuum-sucking a granular body to be the second protruding electrode in the second suction hole and pressure-bonding to the remaining electrode pad; A method of manufacturing a semiconductor device, comprising:
JP10458596A 1996-04-02 1996-04-02 Semiconductor device Pending JPH09275162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10458596A JPH09275162A (en) 1996-04-02 1996-04-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10458596A JPH09275162A (en) 1996-04-02 1996-04-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH09275162A true JPH09275162A (en) 1997-10-21

Family

ID=14384522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10458596A Pending JPH09275162A (en) 1996-04-02 1996-04-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH09275162A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110383440A (en) * 2017-02-17 2019-10-25 索尼半导体解决方案公司 Semiconductor device, shaped like chips semiconductor element, equipped with semiconductor device electronic equipment and manufacture semiconductor device method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110383440A (en) * 2017-02-17 2019-10-25 索尼半导体解决方案公司 Semiconductor device, shaped like chips semiconductor element, equipped with semiconductor device electronic equipment and manufacture semiconductor device method

Similar Documents

Publication Publication Date Title
US6282094B1 (en) Ball-grid array integrated circuit package with an embedded type of heat-dissipation structure and method of manufacturing the same
JP5079493B2 (en) Multi-chip module manufacturing method
US6208025B1 (en) Microelectronic component with rigid interposer
JP3526788B2 (en) Method for manufacturing semiconductor device
US6512176B2 (en) Semiconductor device
US7015070B2 (en) Electronic device and a method of manufacturing the same
US7374969B2 (en) Semiconductor package with conductive molding compound and manufacturing method thereof
US10177060B2 (en) Chip package structure and manufacturing method thereof
US7605020B2 (en) Semiconductor chip package
JPH08255965A (en) Microchip module assembly
JP2008507126A (en) Assembly parts on external board and method for providing assembly parts
US5757068A (en) Carrier film with peripheral slits
JPH11135679A (en) Electronic device and semiconductor package
JP3339881B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
JP3686047B2 (en) Manufacturing method of semiconductor device
JP3529507B2 (en) Semiconductor device
US20080283982A1 (en) Multi-chip semiconductor device having leads and method for fabricating the same
US6963129B1 (en) Multi-chip package having a contiguous heat spreader assembly
KR100192758B1 (en) Method of manufacturing semiconductor package and structure of the same
US6291893B1 (en) Power semiconductor device for “flip-chip” connections
JPH09275162A (en) Semiconductor device
KR100737217B1 (en) Substrateless flip chip package and fabricating method thereof
JP4175339B2 (en) Manufacturing method of semiconductor device
KR100520443B1 (en) Chip scale package and its manufacturing method
JP3462465B2 (en) Semiconductor package mounting structure