JP2005072212A - Electronic component, its manufacturing method, and electronic device - Google Patents

Electronic component, its manufacturing method, and electronic device Download PDF

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JP2005072212A
JP2005072212A JP2003299287A JP2003299287A JP2005072212A JP 2005072212 A JP2005072212 A JP 2005072212A JP 2003299287 A JP2003299287 A JP 2003299287A JP 2003299287 A JP2003299287 A JP 2003299287A JP 2005072212 A JP2005072212 A JP 2005072212A
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substrate
solder
solder bump
electronic component
bump
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Toshiaki Inoue
俊明 井上
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Fujikura Ltd
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Fujikura Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component that has both excellent durability and high reliability after the component is mounted, and to provide a method of manufacturing the component and an electronic device. <P>SOLUTION: In the first electronic component of this invention, a first substrate 1 and a second substrate 10 are disposed to face each other and solder bumps are individually disposed between the plurality of conductive sections 6 of the first substrate 1 and the plurality of conductive sections 12 of the second substrate 10. The solder bumps are provided with at least one solder bump α8A which has an outwardly projecting side face having a radius of curvature larger than that of a circle having the diameter which is equal to the interval between the first and second substrates 1 and 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、配線基板（インタポーザ）を使用しないウェハレベルＣＳＰ(Chip Size/Scale Package）等の半導体パッケージや、ＬＳＩチップを裏返して回路基板に接合する実装方法であるフリップチップに代表される、半田バンプを介して基板間の電気的接続が図られる電子部品とその製造方法及びこのような電子部品を含む電子装置に関する。   The present invention relates to a semiconductor package such as a wafer level CSP (Chip Size / Scale Package) that does not use a wiring board (interposer), or a flip chip that is a mounting method in which an LSI chip is turned over and bonded to a circuit board. The present invention relates to an electronic component in which electrical connection between substrates is achieved through bumps, a manufacturing method thereof, and an electronic device including such an electronic component.

従来、電子部品で用いられる半導体パッケージ構造として、たとえば半導体チップを樹脂により封止したパッケージ（いわゆるDual Inline PackageやQuad Flat Package）では、樹脂パッケージ周辺の側面に金属リード線を配置する周辺端子配置型が主流であった。   Conventionally, as a semiconductor package structure used in electronic components, for example, a package in which a semiconductor chip is sealed with resin (so-called Dual Inline Package or Quad Flat Package), a peripheral terminal arrangement type in which metal lead wires are arranged on the side surface around the resin package Was the mainstream.

これに対し、近年急速に普及している半導体パッケージ構造として、例えばチップスケールパッケージ（ＣＳＰ：Chip Scale Package）とよばれ、パッケージの平坦な表面に電極を平面状に配置した、いわゆるボールグリッドアレイ（ＢＧＡ：Ball Grid Array ）技術の採用により、同一電極端子数を持つ同一投影面積の半導体チップを、従来よりも小さい面積で電子回路基板に高密度実装することを可能にしたパッケージ構造がある。   On the other hand, as a semiconductor package structure that has been rapidly spread in recent years, for example, called a chip scale package (CSP: Chip Scale Package), a so-called ball grid array in which electrodes are arranged in a plane on a flat surface of the package ( By adopting BGA (Ball Grid Array) technology, there is a package structure that enables high-density mounting of a semiconductor chip having the same number of electrode terminals and having the same projected area on an electronic circuit board with a smaller area than conventional ones.

ＢＧＡタイプの半導体パッケージにおいては、パッケージの面積が半導体チップの面積にほぼ等しいＣＳＰ構造が、前述のＢＧＡ電極配置構造とともに開発され、電子機器の小型軽量化に大きく貢献している。ＣＳＰは、回路を形成した例えばシリコンからなるウエハを切断し、個々の半導体チップに対して個別にパッケージ工程を施し、パッケージを完成するものである。   In the BGA type semiconductor package, a CSP structure in which the area of the package is almost equal to the area of the semiconductor chip has been developed together with the BGA electrode arrangement structure described above, and greatly contributes to the reduction in size and weight of electronic devices. The CSP cuts a wafer made of, for example, silicon on which a circuit is formed, and performs a packaging process on each individual semiconductor chip to complete a package.

これに対し、一般的に「ウエハレベルＣＳＰ」とよばれる製法においては、このウエハ上に、絶縁層、再配線層、封止層等を形成し、半田バンプを形成する。そして最終工程においてウエハを所定のチップ寸法に切断することでパッケージ構造を具備した半導体チップを得ることができる。   On the other hand, in a manufacturing method generally called “wafer level CSP”, an insulating layer, a rewiring layer, a sealing layer, and the like are formed on this wafer, and solder bumps are formed. A semiconductor chip having a package structure can be obtained by cutting the wafer into a predetermined chip size in the final process.

ウエハ前面にこれらの回路を積層し、最終工程においてウエハをダイシングすることから、切断したチップそのものの大きさが、パッケージの施された半導体チップとなり、実装基板に対して最小投影面積を有する半導体チップを得ることが可能になる。   Since these circuits are stacked on the front surface of the wafer and the wafer is diced in the final process, the size of the cut chip itself becomes a packaged semiconductor chip, which has a minimum projected area with respect to the mounting substrate. Can be obtained.

ウエハレベルＣＳＰの製造方法における特徴は、パッケージを構成する部材を、すべてウエハの形状において加工することにある。すなわち、絶縁層、導電層（再配線層）、封止樹脂層、半田バンプ等は、すべてウエハをハンドリングすることで形成される。これは、例えば半田バンプの形成においても同じことである。   A feature of the wafer level CSP manufacturing method is that all members constituting the package are processed in the shape of the wafer. That is, the insulating layer, conductive layer (redistribution layer), sealing resin layer, solder bump, and the like are all formed by handling the wafer. This also applies to the formation of solder bumps, for example.

従来のウエハレベルＣＳＰの製造工程では、半田バンプを形成する際にウエハの一方の平面の多数の電極を配置する所定位置に、半田材料を必要量設け、リフロー工程と呼ばれる半田融点以上の温度での加熱溶融、また、半田融点以下での冷却凝固を経ることにより、その形状が球状に近い半田バンプを得る。   In the conventional wafer level CSP manufacturing process, when forming solder bumps, a necessary amount of solder material is provided at a predetermined position where a large number of electrodes on one plane of the wafer are arranged, and at a temperature equal to or higher than the solder melting point called a reflow process. A solder bump having a nearly spherical shape is obtained by heating and melting and cooling and solidifying below the solder melting point.

図６は従来の一般的な半田バンプ形成工程の概略フロー図であり、図７は従来のＣＳＰ等の電子部品（以下、半導体装置とも呼ぶ）の構造を例示する断面図である。   FIG. 6 is a schematic flow diagram of a conventional general solder bump forming process, and FIG. 7 is a cross-sectional view illustrating the structure of a conventional electronic component (hereinafter also referred to as a semiconductor device) such as a CSP.

図７に示した半導体装置５１は、不図示の回路を一方の面上に設けたウエハからなる半導体基板（以下、半導体チップとも呼ぶ）５２と、この回路に導通し、半導体基板５２の表面に形成された電極５３と、半導体基板５２の表面に設けられた絶縁層５４と、電極５３と接続されて絶縁層５４上に配線された導電層（再配線層５５及び電極パッド５６）と、電極パッド５６上に設けられた半田バンプ５８と、この半田バンプ５８を突出させた状態で導電層を覆う封止層５７とを備えて構成されている。図６では導電層（再配線層５５及び電極パッド５６）を設けるまでの工程を纏めて、「ウエハ加工」と表記した。   A semiconductor device 51 shown in FIG. 7 is electrically connected to a semiconductor substrate (hereinafter also referred to as a semiconductor chip) 52 made of a wafer provided with a circuit (not shown) on one surface, and is connected to the surface of the semiconductor substrate 52. The formed electrode 53, the insulating layer 54 provided on the surface of the semiconductor substrate 52, the conductive layer connected to the electrode 53 and wired on the insulating layer 54 (the rewiring layer 55 and the electrode pad 56), the electrode A solder bump 58 provided on the pad 56 and a sealing layer 57 covering the conductive layer with the solder bump 58 protruding are configured. In FIG. 6, the process until the conductive layer (redistribution layer 55 and electrode pad 56) is collectively referred to as “wafer processing”.

リフロー前の半田バンプ形成方法（図６では「半田材料の形成」と表記）としては、例えば（イ）電解半田めっき法、（ロ）半田ボール搭載法、（ハ）半田ペースト印刷法、（ニ）半田ペーストディスペンス法、（ホ）半田蒸着法などの製法が一般に使用されている。いずれの製法も、ウエハ全面の電極配置位置に、半田バンプ下部が所定の形状となるように形成された、半田と濡れ性の良い表面性状を持つ電極パッド上に、所定の面積および高さを持つ半田材料を形成するものである。   As solder bump formation methods before reflow (indicated as “formation of solder material” in FIG. 6), for example, (a) electrolytic solder plating method, (b) solder ball mounting method, (c) solder paste printing method, (d) Manufacturing methods such as () solder paste dispensing method and (e) solder vapor deposition method are generally used. In any of the manufacturing methods, a predetermined area and height are formed on an electrode pad having a surface property that has good wettability with solder and is formed so that the lower part of the solder bump has a predetermined shape at an electrode arrangement position on the entire surface of the wafer. It forms the solder material it has.

その後、半田をリフロー加熱することにより半田を溶融させる（図６では「半田材の加熱溶融」と表記）。リフロー前の半田としては、各製法ごとに異なるものが使用される。製法（イ）では半田成分を含有するめっき層が、製法（ロ）では予め所定のバンプ径に近い形状に分粒された半田ボールが、それぞれ用いられる。製法（ハ）や製法（ニ）では所定のバンプ径に比較して微細な半田粒子をフラックス成分に混合した印刷用のペースト状の半田を用いる。製法（ホ）では真空中で蒸着法により形成された半田成分を含有する金属蒸着膜を使用する。   Thereafter, the solder is melted by reflow heating (indicated as “heat melting of the solder material” in FIG. 6). As the solder before reflow, a different solder is used for each manufacturing method. In the manufacturing method (a), a plating layer containing a solder component is used, and in the manufacturing method (b), solder balls that are sized in advance to a shape close to a predetermined bump diameter are used. In the manufacturing method (c) or manufacturing method (d), a paste solder for printing in which fine solder particles are mixed with a flux component in comparison with a predetermined bump diameter is used. In the manufacturing method (e), a metal vapor deposition film containing a solder component formed by a vapor deposition method in a vacuum is used.

いずれのリフロー前の半田形成工程であっても、リフロー時に半田が融点以上の温度に到達すると、半田が溶融し、溶融した半田は表面張力により凝集する。その形状は、下地をなす電極パッド周縁における金属の濡れ性、溶融した半田の表面張力、溶融した半田自体の重さによる変形等により決定される。溶融した半田は、リフロー工程の後半において、半田の融点より低い温度で冷却処理を施すことにより固体となる。その結果、いわゆる半田バンプと呼ばれる球状に近い形状の半田塊が得られる。   In any solder formation step before reflow, when the solder reaches a temperature higher than the melting point during reflow, the solder melts and the melted solder aggregates due to surface tension. Its shape is determined by the wettability of the metal at the periphery of the electrode pad forming the base, the surface tension of the molten solder, the deformation due to the weight of the molten solder itself, and the like. The molten solder becomes a solid by performing a cooling process at a temperature lower than the melting point of the solder in the latter half of the reflow process. As a result, a solder lump having a nearly spherical shape called a so-called solder bump is obtained.

このような半田バンプを有する半導体装置では、その性能向上のために種々の改良が提案されている（例えば、特許文献１参照）。   In the semiconductor device having such a solder bump, various improvements have been proposed to improve its performance (see, for example, Patent Document 1).

図８は、従来の電子部品の実装時、半田にくびれが生じた状態を示す断面図であり、図７に示した半導体装置５１を例とした場合である。ここで、半導体装置５１から半田バンプ５８を除いた部分を半導体パッケージと呼ぶことにする。   FIG. 8 is a cross-sectional view showing a state in which the solder is constricted during mounting of a conventional electronic component, and is an example of the semiconductor device 51 shown in FIG. Here, a portion obtained by removing the solder bumps 58 from the semiconductor device 51 is referred to as a semiconductor package.

図８は、半田バンプ５８を回路基板６０（以下では、基板とも呼ぶ）の電極パッド６２に押し付けることにより、半導体装置５１（以下では、半導体チップとも呼ぶ）が回路基板６０に実装される様子を示している。なお、図７及び図８には半田バンプ５８を突出させた状態で導電層を覆うように封止層５７を設けた例を示しているが、封止層５７は必須要件ではない。   FIG. 8 shows how the semiconductor device 51 (hereinafter also referred to as a semiconductor chip) is mounted on the circuit board 60 by pressing the solder bumps 58 against the electrode pads 62 of the circuit board 60 (hereinafter also referred to as a substrate). Show. 7 and 8 show an example in which the sealing layer 57 is provided so as to cover the conductive layer with the solder bumps 58 protruding, the sealing layer 57 is not an essential requirement.

つまり、上述した半田バンプ５８は、半導体基板５２と回路基板６０との電気的な導通を図るための電極端子として機能するとともに、両者の熱変形や反りによって発生する応力を緩和、吸収する役割も担う。   That is, the above-described solder bump 58 functions as an electrode terminal for electrical connection between the semiconductor substrate 52 and the circuit substrate 60, and also serves to relieve and absorb stress generated by thermal deformation and warpage of both. Bear.

しかしながら、図７に示すように、従来の半田バンプはその側面方向から見て球状に近い。また、従来の半田バンプは電極バッドに載置された状態では、半田バンプが電極バッドと接してなる面は円形をなす傾向がある。このため、半田バンプが電極パッドや電極部と接触する接合部に応力の集中が発生しやすい。これは半田バンプの破壊をもたらす恐れがあることから、半導体パッケージの信頼性を著しく低下させる原因の一つとして考えられていた。具体的には、従来の半田バンプを有する半導体装置においては、以下の（１）〜（５）に示すような不具合が生じていた。   However, as shown in FIG. 7, the conventional solder bump is nearly spherical when viewed from the side. Further, when the conventional solder bump is placed on the electrode pad, the surface where the solder bump contacts the electrode pad tends to be circular. For this reason, stress concentration tends to occur at the joint where the solder bump contacts the electrode pad or the electrode portion. Since this may cause destruction of the solder bumps, it has been considered as one of the causes for remarkably reducing the reliability of the semiconductor package. Specifically, in the conventional semiconductor device having solder bumps, the following problems (1) to (5) have occurred.

（１）くびれ部の存在に起因する問題
従来の半田バンプ５８は、半田バンプ５８を有する半導体装置５１を基板６０の所定位置に実装する際、半導体装置５１側においては半田バンプ５８と電極パッド５６との接触部６１ａがくびれた構造になる。すなわち、図８に示すように、半田バンプ５８を側方から見た場合、半田バンプの高さ方向において中央部は太く、電極パッド５６との接触部６１ａ付近は中央部より細い構造となる。この細い部分（以下、くびれ部と呼ぶ）に応力が集中し易い。同様の現象は、基板６０側においても半田バンプ５８と電極パッド６２との接触部６１ｂで発生する。このため、接触部６１ａ、６１ｂあるいはその近傍からクラックが発生する傾向があった。 (1) Problems due to the presence of the constricted portion In the conventional solder bump 58, when the semiconductor device 51 having the solder bump 58 is mounted at a predetermined position on the substrate 60, the solder bump 58 and the electrode pad 56 are disposed on the semiconductor device 51 side. The contact portion 61a is constricted. That is, as shown in FIG. 8, when the solder bump 58 is viewed from the side, the center portion is thick in the height direction of the solder bump, and the vicinity of the contact portion 61a with the electrode pad 56 is narrower than the center portion. Stress tends to concentrate on this narrow portion (hereinafter referred to as a constricted portion). A similar phenomenon occurs at the contact portion 61b between the solder bump 58 and the electrode pad 62 on the substrate 60 side. For this reason, there was a tendency for cracks to occur from the contact portions 61a and 61b or the vicinity thereof.

（２）パッケージ薄型化に伴う問題
熱歪みや反りに起因して、半導体チップ５１側の電極パッド５６と回路基板６０側の電極パッド６２との間に、位置ズレが生じた場合、半田バンプ５８にかかる応力は、スタンドオフ量（チップと基板とのギャップ量、つまり実装後の半田バンプ高さとも言える）が大きいほど小さくなる。そのため、接続信頼性を確保するためにはスタンドオフ量を大きくする必要がある。しかし、スタンドオフ量を大きくすると、半導体パッケージとしては厚みが大きくなってしまう。携帯電話を筆頭とするモバイル機器などでは、半導体パッケージを薄型化することが必須であり、従来の半田バンプ構造では、信頼性を確保しつつパッケージを薄型化するには不利である。 (2) Problems associated with package thinning When a misalignment occurs between the electrode pad 56 on the semiconductor chip 51 side and the electrode pad 62 on the circuit board 60 side due to thermal distortion or warping, the solder bump 58 The stress applied to becomes smaller as the standoff amount (the gap amount between the chip and the substrate, that is, the solder bump height after mounting) is larger. Therefore, in order to ensure connection reliability, it is necessary to increase the standoff amount. However, increasing the standoff amount increases the thickness of the semiconductor package. In mobile devices such as mobile phones, it is essential to make the semiconductor package thinner, and the conventional solder bump structure is disadvantageous for making the package thinner while ensuring reliability.

（３）パッケージ多ピン化の問題
半導体チップ５１は高機能・多機能化にともない、小型化とともに多ピン化が求められている。この多ピン化を実現するためには半田バンプ５８間のピッチを狭くしなければならない。ところが、従来の半田バンプ５８は球に近い形状をなしているため、多ピン化を図ろうとすると、小さな径からなる半田バンプ５８を用いざるを得ないので、半田バンプ５８の高さが低くなってしまう。しかし、半導体パッケージの接続信頼性はバンプが高いほど良くなることから、従来の半田バンプ５８を用いて無理に狭ピッチ化を図ると、必然的に信頼性の低下を招くことになる。 (3) Problem of Package Multi-Pin The semiconductor chip 51 is required to be miniaturized and multi-pin as the function and multi-function are increased. In order to realize this increase in the number of pins, the pitch between the solder bumps 58 must be narrowed. However, since the conventional solder bump 58 has a shape close to a sphere, when trying to increase the number of pins, the solder bump 58 having a small diameter must be used, so that the height of the solder bump 58 is reduced. End up. However, since the connection reliability of the semiconductor package is improved as the bump is higher, if the pitch is forcibly reduced by using the conventional solder bump 58, the reliability is inevitably lowered.

（４）電気的接続の信頼性の問題
半田バンプ５８にかかる応力が電極パッド５６、６２との接続部６１ａ、６１ｂに集中するため、ここからクラックが発生して断線不良を引き起こしやすい。回路基板６０と半導体パッケージの熱変形や反りは、半導体チップ５１の中心から外側に向かうほど大きくなるので、半導体チップ５１上に複数個の半田バンプ５８が配置されている場合、一般的に半導体チップ５１の中心から離れた半田バンプ５８ほど強い応力がかかる。これは、半導体チップ５１の中心から離れた半田バンプ５８ほどクラックが発生しやすいことを意味する。 (4) Problem of reliability of electrical connection Since stress applied to the solder bumps 58 is concentrated on the connection portions 61a and 61b with the electrode pads 56 and 62, cracks are generated from this, and disconnection failure tends to occur. Since the thermal deformation and warpage of the circuit board 60 and the semiconductor package increase from the center of the semiconductor chip 51 to the outside, generally, when a plurality of solder bumps 58 are arranged on the semiconductor chip 51, the semiconductor chip As the solder bump 58 is farther from the center of 51, a stronger stress is applied. This means that cracks are more likely to occur as the solder bump 58 is farther from the center of the semiconductor chip 51.

（５）半田バンプ内のボイドの問題
リフロー・プロセスにおいて、半田バンプ５８の内部に発生したガスは、そのまま内部に残存するとボイドが形成されることになる。ＣＳＰをはじめとする小型パッケージでは大きな半田バンプ５８を形成する必要があり、このために電極パッド５６上にできるだけ多くの半田を載せてからリフローが行われる。ところで、電極パッド５６の中心付近に発生したガスは、半田バンプ５８内を通過して外部に抜けていくため、半田の量が多いほどガスは抜けにくくなり、半田バンプ５８の内部にガスが残存してしまう傾向が強まる。つまり、半田バンプ５８を形成するために要する半田の量が多いほど、得られた半田バンプ５８内にボイドが発生しやすい。特に、半田材料として旧来広く使われてきたＳｎ−Ｐｂ共晶半田に比べて、最近よく使われるＳｎ−Ａｇ−ＣｕやＳｎ−Ｚｎ−Ｂｉといった鉛フリー半田は、上記ボイドが発生しやすく、これがチップ実装後の接続信頼性に大きな影響を及ぼすことが危惧されている。 (5) Problem of Void in Solder Bump In the reflow process, if the gas generated inside the solder bump 58 remains inside the void, a void is formed. In a small package such as a CSP, it is necessary to form a large solder bump 58. For this reason, as much solder as possible is placed on the electrode pad 56, and then reflow is performed. By the way, the gas generated in the vicinity of the center of the electrode pad 56 passes through the solder bump 58 and escapes to the outside. Therefore, as the amount of solder increases, the gas becomes difficult to escape, and the gas remains inside the solder bump 58. The tendency to do is strengthened. That is, as the amount of solder required to form the solder bump 58 is larger, voids are more likely to occur in the obtained solder bump 58. In particular, lead-free solders such as Sn-Ag-Cu and Sn-Zn-Bi, which are often used recently, are more likely to generate voids than Sn-Pb eutectic solder that has been widely used as a solder material. There is a concern that it will greatly affect the connection reliability after chip mounting.

したがって、パッケージの薄型化や多ピン化に対応でき、外力が作用した際に半田バンプのくびれ部に集中する応力が緩和され、かつ、半田バンプ内にボイドが形成されにくい構造を備えてなる電子部品の開発が期待されていた。
特開平５−１３４１８号公報 Therefore, it is possible to cope with the thinning of the package and the increase in the number of pins, the stress concentrated on the constricted part of the solder bump when an external force is applied, and the structure having a structure in which a void is not easily formed in the solder bump. Development of parts was expected.
JP-A-5-13418

本発明は上記事情に鑑みてなされたもので、実装後における優れた耐久性と高い信頼性とを兼ね備えた電子部品とその製造方法及び電子装置の提供を目的とする。   The present invention has been made in view of the above circumstances, and an object thereof is to provide an electronic component having excellent durability after mounting and high reliability, a manufacturing method thereof, and an electronic device.

本発明に係る第一の電子部品は、第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品であって、前記半田バンプとして、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプαを、少なくとも具備してなることを特徴としている。   In the first electronic component according to the present invention, a first substrate and a second substrate are positioned to face each other, and a plurality of conductive portions included in the first substrate and a plurality of conductive portions included in the second substrate. An electronic component in which solder bumps are individually arranged between the side surfaces, and the solder bumps have side surfaces convex outward, and the curvature radius of the curved surface formed by the side surfaces is the first substrate and the first It is characterized by comprising at least solder bumps α larger than the radius of curvature of a circle whose diameter is the distance between two substrates.

従来の半田バンプは、その側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径と同じもしくはそれより小さい外形をなしていたため、第一基板や第二基板に外力が加わると、半田バンプがこれらの基板と接合されている部分あるいはその近傍に応力が集中し、クラック発生などが生じていた。   In the conventional solder bump, the side surface is convex outward, and the curvature radius of the curved surface formed by the side surface is the same as the curvature radius of a circle whose diameter is the distance between the first substrate and the second substrate, or Because the outer shape was smaller than that, when external force was applied to the first board or the second board, the stress was concentrated at the part where the solder bumps were joined to these boards or in the vicinity thereof, and cracks were generated. .

これに対し、本発明に係る半田バンプαは、その側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きいことから、従来の半田バンプに比べて半田バンプαは、太い部分（高さ方向の中央付近）と細い部分（上下基板との接合部付近）との差分を小さくできる。これは、太い部分と細い部分における両者の外回りの長さが近づくことを意味する。   On the other hand, the solder bump α according to the present invention has the side surface convex outward, and the curvature radius of the curved surface formed by the side surface is the distance between the first substrate and the second substrate. Since the radius of curvature of the circle is larger than that of the conventional solder bump, the difference between the thick portion (near the center in the height direction) and the thin portion (near the junction with the upper and lower substrates) can be reduced. This means that the outer lengths of both the thick part and the thin part approach each other.

半田バンプαはその太い部分が従来より細くなっているので、太い部分がもつ剛性は従来より小さくなり、かつ、細い部分の剛性に近づいたことになる。したがって、上下基板を介して半田バンプに外力が伝わる場合、この外力が電極パッドとの接合部分（細い部分）のみに集中すること無く、バンプ全体に分散される。その結果、バンプに生じる最大応力が小さくなり、かつ、細い部分に局所的に応力が加わる現象を和らげることができるので、使用環境においてバンプにクラックが発生しにくくなる。よって、本発明によれば、実装後における優れた耐久性と高い信頼性とを兼ね備えた電子部品が得られる。   Since the thick part of the solder bump α is thinner than the conventional one, the rigidity of the thick part is smaller than that of the conventional one, and the rigidity of the thin part is approached. Therefore, when an external force is transmitted to the solder bumps via the upper and lower substrates, the external force is distributed over the entire bump without concentrating only on the joint portion (thin portion) with the electrode pad. As a result, the maximum stress generated in the bump is reduced, and the phenomenon in which the stress is locally applied to the thin portion can be relieved, so that the bump is hardly generated in the use environment. Therefore, according to the present invention, an electronic component having both excellent durability after mounting and high reliability can be obtained.

本発明に係る第二の電子部品は、第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品であって、前記半田バンプとして、側面が外側に凹状である半田バンプβを、少なくとも具備してなることを特徴としている。   The second electronic component according to the present invention includes a first substrate and a second substrate facing each other, and a plurality of conductive portions included in the first substrate and a plurality of conductive portions included in the second substrate. An electronic component in which solder bumps are individually disposed between the solder bumps, wherein the solder bumps include at least solder bumps β whose side surfaces are concave outward.

かかる構成からなる半田バンプβは、その側面が外側に凹状であることから、従来の半田バンプや上述した半田バンプαとは逆に、上下基板との接合部付近が太い部分となり、高さ方向の中央付近が細い部分をなす。つまり、本発明に係る半田バンプβでは、太い部分と細い部分が従来の半田バンプや上述した半田バンプαとは異なり、逆転した構造を有している。   Since the solder bump β having such a configuration has a concave shape on the outer side, the vicinity of the junction with the upper and lower substrates becomes a thick portion contrary to the conventional solder bump and the above-described solder bump α, and the height direction The center of the area is narrow. That is, the solder bump β according to the present invention has a structure in which a thick portion and a thin portion are reversed unlike a conventional solder bump or the above-described solder bump α.

半田バンプβは高さ方向の中央付近よりも、根元の部分、すなわち上下基板との接合部付近が太い構造となっているので、上下基板を介して半田バンプに外力が伝わる場合、従来のように外力が電極パッドとの接合部分（従来は細い部分）のみに集中すること無く、バンプ全体に分散されるので、バンプに生じる最大応力が小さくなる。   Since the solder bump β has a thicker structure at the base, that is, the vicinity of the junction with the upper and lower substrates than near the center in the height direction, when external force is transmitted to the solder bumps via the upper and lower substrates, In addition, since the external force is not concentrated on only the joint portion with the electrode pad (conventionally a thin portion) but is distributed over the entire bump, the maximum stress generated in the bump is reduced.

また、半田バンプβでは、細い部分に対する太い部分の太さの比率を適宜、調整することにより、細い部分に局所的に応力が加わる現象をより一層和らげることが可能となるので、使用環境においてバンプ内のクラック発生が抑制される。したがって、本発明によれば、実装後における優れた耐久性と高い信頼性とを兼ね備えた電子部品が得られる。   Also, in the solder bump β, by appropriately adjusting the ratio of the thickness of the thick part to the thin part, it is possible to further reduce the phenomenon of locally applying stress to the thin part. The occurrence of cracks inside is suppressed. Therefore, according to the present invention, an electronic component having both excellent durability after mounting and high reliability can be obtained.

本発明に係る第三の電子部品は、第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品であって、前記半田バンプとして、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプαと、側面が外側に凹状である半田バンプβとを、少なくとも具備してなることを特徴としている。   In the third electronic component according to the present invention, the first substrate and the second substrate are positioned to face each other, and a plurality of conductive portions included in the first substrate and a plurality of conductive portions included in the second substrate. An electronic component in which solder bumps are individually arranged between the side surfaces, and the solder bumps have side surfaces convex outward, and the curvature radius of the curved surface formed by the side surfaces is the first substrate and the first It is characterized by comprising at least solder bumps α larger than the radius of curvature of a circle whose diameter is the distance between two substrates, and solder bumps β whose side surfaces are concave outward.

かかる構成からなる電子部品は、第一の電子部品が備える半田バンプαと、第二の電子部品が備える半田バンプβを併せ持つことから、上述した両者の作用・効果を同時に有することができる。特に、第一基板が有する複数個の導電部と第二基板が有する複数個の導電部との間に個別に半田バンプが配される場合、上記２種類の特徴をもつバンプを二次元的に分散して配置することによって、個々のバンプが受ける影響の均一化が図れる。   Since the electronic component having such a configuration has both the solder bump α included in the first electronic component and the solder bump β included in the second electronic component, the above-described operations and effects can be simultaneously achieved. In particular, when solder bumps are individually arranged between the plurality of conductive portions of the first substrate and the plurality of conductive portions of the second substrate, the bumps having the above two types of features are two-dimensionally arranged. By distributing and arranging, the influence which each bump receives can be made uniform.

したがって、特定の設置位置にあるバンプに応力が集中的に発生することが解消されるので、個々のバンプに生じる最大応力は一段と抑制されることから、本発明によれば、実装後において、さらに優れた耐久性と高い信頼性とを兼ね備えた電子部品が得られる。   Therefore, since it is eliminated that stress is concentrated on the bumps at a specific installation position, the maximum stress generated in each bump is further suppressed. Therefore, according to the present invention, after mounting, An electronic component having both excellent durability and high reliability can be obtained.

上述した第一から第三の電子部品は、一組の前記第一基板と前記第二基板との間に、前記半田バンプα及び／又は前記半田バンプβと、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径と同じもしくはそれより小さい、通常の半田バンプγとを混在して設けた構成にしてもよい。   In the first to third electronic components described above, the solder bumps α and / or the solder bumps β and the side surfaces are convex outwardly between the pair of the first substrate and the second substrate. In addition, a normal solder bump γ having a radius of curvature of the curved surface formed by the side surface that is equal to or smaller than a radius of curvature of a circle having a diameter between the first substrate and the second substrate is provided. A configuration may be used.

かかる構成の電子部品では、半田バンプαと半田バンプβに加えて、従来使用されている通常の半田バンプγを、二次元的に分散して配置することによって、個々のバンプが受ける影響の均一化がさらに図れるので好ましい。   In an electronic component having such a configuration, in addition to the solder bump α and the solder bump β, the conventional solder bumps γ that are conventionally used are two-dimensionally distributed to uniformly affect each bump. This is preferable because it can be further improved.

上述した電子部品を構成する半田バンプα及び／又は半田バンプβは、前記第一基板または前記第二基板のうち、面積が狭い方の基板に対応して、その基板の周辺又はその近傍領域に配置される構成としてもよい。一般に、バンプに生じる応力の大きさは、第一基板や第二基板の中心から離れるほど大きくなる傾向がある。したがって、半導体装置において一番応力が発生する位置、すなわち基板の周辺又はその近傍領域に、半田バンプα及び／又は半田バンプβを設けることにより、これらのバンプは元より、その他の領域に設けられたバンプが受ける影響も著しく改善が図れるので望ましい。   The solder bump α and / or the solder bump β constituting the electronic component described above corresponds to the substrate having the smaller area of the first substrate or the second substrate, and is formed in the vicinity of the substrate or in the vicinity thereof. It is good also as a structure arranged. In general, the magnitude of the stress generated in the bump tends to increase as the distance from the center of the first substrate or the second substrate increases. Therefore, by providing the solder bumps α and / or solder bumps β at the position where the stress is most generated in the semiconductor device, that is, at the periphery of the substrate or in the vicinity thereof, these bumps are provided not only in the original area but also in other areas. It is desirable because the effect of bumps can be significantly improved.

本発明に係る第一の電子部品の製造方法は、第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品の製造方法であって、
予め前記第一基板の導電部上に設けられた略半球状の半田に熱を加えながら、該半田に対して前記第二基板の導電部を接触させる第一工程と、
前記第一工程の後、前記第一基板に対して前記第二基板を離間させる方向に移動させて、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプα、及び／又は、側面が外側に凹状である半田バンプβを形成する第二工程とを、少なくとも具備していることを特徴としている。 In the first electronic component manufacturing method according to the present invention, the first substrate and the second substrate are positioned to face each other, the plurality of conductive portions included in the first substrate and the plurality of conductive portions included in the second substrate. A method of manufacturing an electronic component in which solder bumps are individually arranged between the parts,
A first step of bringing the conductive portion of the second substrate into contact with the solder while applying heat to a substantially hemispherical solder previously provided on the conductive portion of the first substrate;
After the first step, the second substrate is moved away from the first substrate, the side surface is convex outward, and the curvature radius of the curved surface formed by the side surface is A solder bump α larger than the radius of curvature of a circle whose diameter is the distance between one substrate and the second substrate, and / or a second step of forming a solder bump β whose side surface is concave outward. It is characterized by being.

第一の電子部品の製造方法では、まず第一工程において、予め第一基板の導電部上に設けられた略半球状の半田に熱を加えて、半田を溶融状態とし、この溶融状態にある半田に対して第二基板の導電部を接触させる。これにより、２つの基板上に配された導電部間に、溶融状態にある半田が挟まれた構成をつくる。   In the first method for manufacturing an electronic component, first, in a first step, heat is applied to a substantially hemispherical solder provided in advance on the conductive portion of the first substrate to bring the solder into a molten state, which is in this molten state. The conductive part of the second substrate is brought into contact with the solder. As a result, a structure in which solder in a molten state is sandwiched between conductive portions arranged on two substrates is created.

次の第二工程では、第一工程を経た第一基板に対して第二基板を離間させる方向に移動させることにより、溶融されてかつ２つの基板に接した状態にある半田は両方の基板で引っ張られることになる。その結果、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプαや、側面が外側に凹状である半田バンプβ、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径と同じもしくはそれより小さい、通常の半田バンプγを形成することができる。   In the next second step, the solder that has been melted and in contact with the two substrates by moving the second substrate away from the first substrate that has passed through the first step is in both substrates. Will be pulled. As a result, the side surface is convex outward, and the curvature radius of the curved surface formed by the side surface is larger than the curvature radius of the circle whose diameter is the distance between the first substrate and the second substrate. Solder bump β whose side surface is concave outward, the side surface is convex outward, and the curvature radius of the curved surface formed by the side surface is the curvature of a circle whose diameter is the distance between the first substrate and the second substrate A normal solder bump γ having the same radius or smaller than the radius can be formed.

本発明に係る第二の電子部品の製造方法は、第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品の製造方法であって、
予め前記第一基板の各導電部上にそれぞれ異なる量の半田を設け、該半田に対して前記第二基板の各導電部を接触させる第三工程と、
前記第三工程の後、前記半田に熱を加えることにより、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプα、及び／又は、側面が外側に凹状である半田バンプβを形成する第四工程とを、
少なくとも具備していることを特徴としている。 In the second electronic component manufacturing method according to the present invention, the first substrate and the second substrate are positioned to face each other, the plurality of conductive portions included in the first substrate and the plurality of conductive portions included in the second substrate. A method of manufacturing an electronic component in which solder bumps are individually arranged between the parts,
Providing a different amount of solder on each conductive portion of the first substrate in advance, and contacting each conductive portion of the second substrate with the solder;
After the third step, by applying heat to the solder, the side surface is convex outward, and the radius of curvature of the curved surface formed by the side surface is the diameter between the first substrate and the second substrate. A solder bump α larger than the radius of curvature of the circle and / or a fourth step of forming a solder bump β whose side surface is concave outward,
It is characterized by having at least.

第二の電子部品の製造方法では、まず第三工程において、予め第一基板の各導電部上にそれぞれ異なる量の半田を設け、これらの半田に対して前記第二基板の各導電部を接触させる。これにより、個々の半田が第一基板の各導電部と第二基板の各導電部との間に挟まれた構成とする。   In the second electronic component manufacturing method, first, in the third step, different amounts of solder are previously provided on the respective conductive portions of the first substrate, and the respective conductive portions of the second substrate are brought into contact with these solders. Let Thereby, it is set as the structure by which each solder was pinched | interposed between each electroconductive part of a 1st board | substrate, and each electroconductive part of a 2nd board | substrate.

次の第四工程では、前記半田に対して熱を加えることにより、半田には表面張力が発生し、各半田がそれぞれ変形することにより、前記第一基板は前記第二基板から離間する方向に移動させられる。この現象を利用すると、異なる量の半田を設けることによって、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプαや、側面が外側に凹状である半田バンプβを、作り分けることが可能となる。   In the next fourth step, by applying heat to the solder, surface tension is generated in the solder, and each solder is deformed, so that the first substrate moves away from the second substrate. Moved. By utilizing this phenomenon, by providing different amounts of solder, the side surface is convex outward, and the curvature radius of the curved surface formed by the side surface is the distance between the first substrate and the second substrate as the diameter. Thus, it is possible to separately produce solder bumps α that are larger than the radius of curvature of the circle to be bent and solder bumps β whose side surfaces are concave outward.

複数個の半田バンプを、上述した半田バンプα、半田バンプβ及び半田バンプγとして、同じ２つの基板間で各々の形態を変えて作り分けるためには、例えば個々の半田量を微妙に変えた半田を用いたり、あるいは溶融状態にある半田が接する導電部の面積を微妙に変える手法が好適に用いられる。また、溶融状態にある半田を冷却して固化させるときの条件を変えることによっても、上記作り分けは制御できる。   In order to create a plurality of solder bumps as the above-described solder bump α, solder bump β, and solder bump γ by changing each form between the same two substrates, for example, the amount of each solder is slightly changed. A technique that uses solder or slightly changes the area of the conductive portion that is in contact with the molten solder is preferably used. Further, the above-mentioned making can be controlled by changing the conditions for cooling and solidifying the solder in the molten state.

第一及び第二の電子部品の製造方法において、前記半田バンプα及び／又は前記半田バンプβを、前記第一基板又は前記第二基板の何れか一方の周辺又はその近傍領域に作製し、その他の領域には、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径と同じもしくはそれより小さい、通常の半田バンプγを作製しても構わない。   In the first and second electronic component manufacturing methods, the solder bumps α and / or the solder bumps β are produced in the vicinity of one of the first substrate and the second substrate or in the vicinity thereof. In this region, the side surface is convex outward, and the curvature radius of the curved surface formed by the side surface is the same as or more than the curvature radius of a circle whose diameter is the distance between the first substrate and the second substrate. A small normal solder bump γ may be produced.

また本発明に係る第一及び第二の電子部品の製造方法において、半田バンプα、半田バンプβおよび半田バンプγを、半田ボール搭載法、半田ペースト印刷法、電解メッキ法、ペースト・ディスペンス・フロー法およびフロー半田法からなる群から選択される方法で形成することが好ましい。   In the first and second electronic component manufacturing methods according to the present invention, the solder bump α, the solder bump β, and the solder bump γ are applied to a solder ball mounting method, a solder paste printing method, an electrolytic plating method, a paste dispensing flow, and the like. Preferably, it is formed by a method selected from the group consisting of a method and a flow solder method.

さらに本発明は、半田バンプα及び／又は半田バンプβを少なくとも有する半導体パッケージを含むことを特徴とする電子装置を提供する。   Furthermore, the present invention provides an electronic device including a semiconductor package having at least a solder bump α and / or a solder bump β.

以上説明したように、本発明に係る電子部品を構成する半田バンプαと半田バンプβは、従来の半田バンプγと比較してバンプの高さ方向における中央部の剛性が低いので、外力や熱の影響を受けた場合に半田バンプの付け根に相当する導電部との接合付近への応力集中が抑制される。したがって、本発明は、実装後に半田バンプの耐久性に優れた、長期信頼性の高い電子部品の提供に寄与するとともに、電気的接続の信頼性も向上させる。   As described above, the solder bump α and the solder bump β constituting the electronic component according to the present invention have lower rigidity at the center in the height direction of the bump than the conventional solder bump γ. The stress concentration in the vicinity of the junction with the conductive portion corresponding to the root of the solder bump is suppressed. Therefore, the present invention contributes to the provision of an electronic component with excellent durability of solder bumps after mounting and high long-term reliability, and also improves the reliability of electrical connection.

上述した半田バンプと導電部の接合付近に応力が集中しにくい構造は、従来の半田バンプγからなる構造に比べてスタンドオフ量を小さくできることから、本発明は電子部品の薄型化をもたらす。   Since the structure in which stress hardly concentrates in the vicinity of the joint between the solder bump and the conductive portion described above can reduce the stand-off amount as compared with the structure composed of the conventional solder bump γ, the present invention brings about a reduction in the thickness of the electronic component.

また、本発明に係る電子部品は、この半田バンプと導電部の接合付近に応力が集中しにくい構造を備えているので、同等のスタンドオフ量であれば従来の構造に比べて信頼性が高い。このため狭ピッチ化を図るために半田バンプ径を小さくした場合でも良好な信頼性を確保できることから、本発明は多ピン化に有利である。   In addition, since the electronic component according to the present invention has a structure in which stress is unlikely to concentrate near the joint between the solder bump and the conductive portion, the reliability is higher than the conventional structure if the stand-off amount is equivalent. . Therefore, even when the solder bump diameter is reduced in order to reduce the pitch, good reliability can be ensured, and the present invention is advantageous for increasing the number of pins.

本発明の電子部品では、基板上において半田バンプα及び／又は半田バンプβを設置する領域や、耐応力特性の相違する半田バンプを混在すて設ける形態を採用することにより、個々のバンプに加わる応力を効果的に分散できるので、半田バンプにおいてクラックなどの発生が抑制されることから、電気的な接続信頼性の向上が一段と図れる。   In the electronic component of the present invention, an area where the solder bumps α and / or solder bumps β are installed on the substrate and a form in which solder bumps having different stress resistance characteristics are mixed are applied to the individual bumps. Since the stress can be effectively dispersed, the occurrence of cracks and the like is suppressed in the solder bumps, so that the electrical connection reliability can be further improved.

一般に、高さのある半田バンプほど内部にボイドが残りやすいが、本発明によれば高さを抑えた低いバンプでも、耐応力特性の相違する半田バンプを作り分けできるので、半田バンプ内部にボイドが発生しにくくなる。よって、本発明は、従来よりボイドが低減するので、半田バンプと導電部との接続部付近における強度低下を防ぐことができる。   In general, the higher the solder bump, the easier it is for voids to remain inside. However, according to the present invention, even with low bumps with reduced height, it is possible to create solder bumps with different stress resistance characteristics. Is less likely to occur. Therefore, according to the present invention, since voids are reduced as compared with the prior art, it is possible to prevent a decrease in strength in the vicinity of the connection portion between the solder bump and the conductive portion.

半田バンプα及び／又は半田バンプβは従来より細身の形状からなるので、半田の使用量を削減することができるので、本発明は電子部品の低コストにも貢献する。   Since the solder bump α and / or the solder bump β has a thinner shape than before, the amount of solder used can be reduced, and the present invention contributes to the low cost of the electronic component.

以下では、本発明に係る電子部品の一実施形態を図面に基づいて説明する。   Below, one Embodiment of the electronic component which concerns on this invention is described based on drawing.

図１は本発明に係る電子部品の作製に用いる第一基板の構造を例示する部分断面図であり、一つの導電部に半田を設けた状態を示している。図１において、１が第一基板を、６がその上に設けた導電部を表している。具体的には、第一基板１は、半導体基材２の一面上に絶縁層４、導電層５、封止層７を順に積層し、封止層７に導電層５を露出させた導電部（以下、電極パッドとも呼ぶ）６を設けてなる。また図１は、電極パッド６上に半田バンプ８を載置した状態も示している。なお、３は電極であり、絶縁層４と同様に半導体基板２の一面上に設けられ、導電層５と接して配置される。   FIG. 1 is a partial cross-sectional view illustrating the structure of a first substrate used for manufacturing an electronic component according to the present invention, and shows a state where solder is provided on one conductive portion. In FIG. 1, 1 represents a first substrate, and 6 represents a conductive portion provided thereon. Specifically, the first substrate 1 includes a conductive portion in which an insulating layer 4, a conductive layer 5, and a sealing layer 7 are sequentially laminated on one surface of a semiconductor substrate 2, and the conductive layer 5 is exposed on the sealing layer 7. (Hereinafter also referred to as an electrode pad) 6 is provided. FIG. 1 also shows a state in which solder bumps 8 are placed on the electrode pads 6. Reference numeral 3 denotes an electrode, which is provided on one surface of the semiconductor substrate 2 similarly to the insulating layer 4 and is in contact with the conductive layer 5.

図１から明らかなように、電極パッド６は導電層５のうち封止層７を除去した領域であることから、電極パッド６の外周辺は封止層７の側断面７ａと一致することになる。そして、この電極パッド６上に半田バンプを設けるので、半田バンプの初期成長部８’は、電極パッド６の外周辺すなわち封止層７の側断面７ａにより、その外周面が規制を受ける。このような初期成長部８’の上にさらに成長した部分は略球形をとり、半田バンプ８を構成している。   As apparent from FIG. 1, the electrode pad 6 is a region where the sealing layer 7 is removed from the conductive layer 5, so that the outer periphery of the electrode pad 6 coincides with the side cross section 7 a of the sealing layer 7. Become. Since the solder bump is provided on the electrode pad 6, the outer peripheral surface of the initial growth portion 8 'of the solder bump is restricted by the outer periphery of the electrode pad 6, that is, the side cross section 7a of the sealing layer 7. A portion further grown on the initial growth portion 8 ′ has a substantially spherical shape and constitutes a solder bump 8.

図２は本発明に係る電子部品の部分断面図であり、第一基板を第二基板に実装した際に、半田にくびれが生じた状態を示しており、（ａ）は半田バンプαを、（ｂ）は半田バンプβを、（ｃ）は半田バンプγをそれぞれ表す。図２の図面は全て、対向する一組の導電部間に半田バンプが挟まれた様子を示す。   FIG. 2 is a partial cross-sectional view of the electronic component according to the present invention, and shows a state in which the solder is constricted when the first substrate is mounted on the second substrate, and (a) shows the solder bump α, (B) represents the solder bump β, and (c) represents the solder bump γ. All the drawings in FIG. 2 show a state in which solder bumps are sandwiched between a pair of opposing conductive portions.

図２（ａ）は本発明に係る第一の電子部品の部分断面図に相当する。すなわち、第一基板１と第二基板１０が対向して位置され、第一基板１が有する導電部６と第二基板１０が有する導電部１２との間に半田バンプα８Ａが配されてなる半導体パッケージであって、半田バンプα８Ａは、側面が外側に凸状であり、かつ、側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きいことを特徴としている。   FIG. 2A corresponds to a partial cross-sectional view of the first electronic component according to the present invention. That is, a semiconductor in which the first substrate 1 and the second substrate 10 are located facing each other, and the solder bump α8A is disposed between the conductive portion 6 of the first substrate 1 and the conductive portion 12 of the second substrate 10. The solder bump α8A is a package, the side surface of which is convex outward, and the curvature radius of the curved surface formed by the side surface is greater than the curvature radius of a circle whose diameter is the distance between the first substrate and the second substrate. It is characterized by being large.

かかる構成からなる半田バンプα８Ａは、その側面が外側に凸状であり、かつ、側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きいので、後述する図２（ｃ）に示す従来の半田バンプに比べて、太い部分（高さ方向の中央付近）と細い部分（上下基板との接合部付近）との差が小さくなる。すなわち、半田バンプα８Ａは、従来の半田バンプより、太い部分と細い部分の外回りの長さが近づく。   The solder bump α8A having such a configuration has a side surface convex outward, and the curvature radius of the curved surface formed by the side surface is larger than the curvature radius of a circle whose diameter is the distance between the first substrate and the second substrate. Since it is large, the difference between the thick part (near the center in the height direction) and the thin part (near the joint between the upper and lower substrates) is smaller than that of the conventional solder bump shown in FIG. In other words, the outer lengths of the thick and thin portions of the solder bump α8A are closer than those of the conventional solder bump.

換言すると、半田バンプα８Ａはその太い部分が従来より細くなっているので、太い部分の剛性は細い部分のそれに近づくことから、上下基板を介して半田バンプ８Ａに外力が伝達される際に、この外力が電極パッドとの接合部分（細い部分）のみに集中することが回避され、バンプ全体に分散されるようになる。   In other words, since the thick portion of the solder bump α8A is thinner than the conventional one, the rigidity of the thick portion approaches that of the thin portion. Therefore, when an external force is transmitted to the solder bump 8A through the upper and lower substrates, It is avoided that the external force concentrates only on the joint portion (thin portion) with the electrode pad, and is distributed over the entire bump.

半田バンプα８Ａは、上述した構造をなしているので、第一の基板１を第二の基板１０に実装した時、半田バンプα８Ａのくびれ部１１ａ、１１ｂは、図２（ｃ）に示す従来の半田バンプγ８Ｃより大きな角度をもつことができる。したがって、例えば２つの基板１、１０がずれ方向に変位しても、このずれによって発生する応力はくびれ部１１ａ、１１ｂに従来より集中しにくくなる。   Since the solder bump α8A has the above-described structure, when the first substrate 1 is mounted on the second substrate 10, the constricted portions 11a and 11b of the solder bump α8A have the conventional structure shown in FIG. The angle can be larger than that of the solder bump γ8C. Therefore, for example, even if the two substrates 1 and 10 are displaced in the displacement direction, the stress generated by the displacement is less likely to concentrate on the constricted portions 11a and 11b than in the past.

したがって、半田バンプα８Ａに生じる最大応力は従来より低減され、また細い部分に局所的に加わる応力も緩和されるので、使用環境におけるバンプ内のクラック発生を抑制できる。ゆえに、本発明は、実装後における優れた耐久性と高い信頼性とを兼ね備えた電子部品をもたらす。   Therefore, the maximum stress generated in the solder bump α8A is reduced as compared to the conventional case, and the stress locally applied to the narrow portion is also alleviated, so that the occurrence of cracks in the bump in the use environment can be suppressed. Therefore, the present invention provides an electronic component having both excellent durability after mounting and high reliability.

図２（ｂ）は本発明に係る第二の電子部品の部分断面図を表している。すなわち、第一基板１と第二基板１０が対向して位置され、第一基板１が有する導電部６と第二基板１０が有する導電部１２との間に半田バンプβ８Ｂが配されてなる電子部品であって、前記半田バンプβ８Ｂは、側面が外側に凹状であることを特徴としている。   FIG. 2B is a partial cross-sectional view of the second electronic component according to the present invention. That is, the first substrate 1 and the second substrate 10 are opposed to each other, and the solder bump β8B is arranged between the conductive portion 6 of the first substrate 1 and the conductive portion 12 of the second substrate 10. It is a component, and the solder bump β8B is characterized in that the side surface is concave outward.

かかる構成からなる半田バンプβ８Ｂは、その側面が外側に凹状である点において、従来の半田バンプや上述した半田バンプα８Ａと相違している。つまり、半田バンプβ８Ｂは、上下基板との接合部付近が太い部分をなし、高さ方向の中央付近が細い部分となる。   The solder bump β8B having such a configuration is different from the conventional solder bump and the above-described solder bump α8A in that the side surface is concave outward. That is, the solder bump β8B has a thick portion near the junction with the upper and lower substrates, and a thin portion near the center in the height direction.

つまり、半田バンプβ８Ｂは高さ方向の中央付近よりも、根元の部分、すなわち上下基板との接合部付近が太い構造を有するので、上下基板を介して半田バンプに外力が伝わる場合、従来のように外力が電極パッドとの接合部分（従来の半田バンプでは細い部分）のみに集中すること無く、バンプ全体に分散される。その結果、半田バンプβ８Ｂでは、バンプに生じる最大応力が低減される。   That is, since the solder bump β8B has a thicker structure at the base portion, that is, near the junction with the upper and lower substrates than near the center in the height direction, when external force is transmitted to the solder bumps via the upper and lower substrates, In addition, the external force is distributed over the entire bump without concentrating only on the joint portion with the electrode pad (thin portion in the conventional solder bump). As a result, in the solder bump β8B, the maximum stress generated in the bump is reduced.

このバンプに生じる最大応力の低減は、使用環境におけるバンプ内のクラックの発生が抑制するので、本発明によっても、実装後における優れた耐久性と高い信頼性とを兼ね備えた電子部品の提供が可能となる。   This reduction of the maximum stress generated in the bumps suppresses the occurrence of cracks in the bumps in the usage environment, so that the present invention can also provide an electronic component having both excellent durability after mounting and high reliability. It becomes.

本発明に係る第三の電子部品は、上述した図２（ａ）と図２（ｂ）を同時に有する構成からなる。すなわち、第一基板１と第二基板１０が対向して位置され、第一基板１が有する導電部６と第二基板１０が有する導電部６との間に半田バンプが配されてなる電子部品であって、この半田バンプとして、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプα８Ａと、側面が外側に凹状である半田バンプβ８Ｂとを、少なくとも具備している。   The third electronic component according to the present invention has a configuration having the above-described FIG. 2 (a) and FIG. 2 (b) at the same time. That is, an electronic component in which the first substrate 1 and the second substrate 10 are positioned to face each other, and solder bumps are arranged between the conductive portion 6 of the first substrate 1 and the conductive portion 6 of the second substrate 10. In this solder bump, the side surface is convex outward, and the curvature radius of the curved surface formed by the side surface is larger than the curvature radius of a circle whose diameter is the distance between the first substrate and the second substrate. It includes at least a large solder bump α8A and a solder bump β8B whose side surface is concave outward.

上記第三の電子部品は、第一の電子部品が備える半田バンプα８Ａと、第二の電子部品が備える半田バンプβ８Ｂを併せ持つので、上述した両者の作用・効果を同時にもつことが可能となる。例えば、第一基板が有する複数個の導電部と第二基板が有する複数個の導電部との間に個別に半田バンプを配する際に、上記２種類の特徴をもつ半田バンプα８Ａと半田バンプβ８Ｂを、二次元的に分散あるいは交互に設けたり、または局所的に集中して設けるなどの特色のある配置構成を採用すれば、個々のバンプが受ける影響の均一化が一段と図れることから好ましい。   Since the third electronic component has both the solder bump α8A included in the first electronic component and the solder bump β8B included in the second electronic component, it is possible to have both the functions and effects described above. For example, when solder bumps are individually disposed between a plurality of conductive portions of the first substrate and a plurality of conductive portions of the second substrate, the solder bump α8A having the above two characteristics and the solder bumps are arranged. It is preferable to adopt a characteristic arrangement such as two-dimensionally distributed or alternately provided β8B, or to be locally concentrated so that influences of individual bumps can be made more uniform.

つまり、第三の電子部品では、特定の設置位置にあるバンプに応力が集中的に発生しにくくなり、ひいては個々のバンプに生じる最大応力のさらなる低減が図れる。ゆえに、第三の電子部品も、実装後において、優れた耐久性と高い信頼性とを兼ね備えることができる。   That is, in the third electronic component, it is difficult for stress to occur intensively on the bumps at a specific installation position, and as a result, the maximum stress generated in each bump can be further reduced. Therefore, the third electronic component can also have excellent durability and high reliability after mounting.

上述した第一から第三の電子部品は、一組の前記第一基板と前記第二基板との間に、前記半田バンプα８Ａ及び／又は前記半田バンプβ８Ｂと、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率が円の曲率と同じもしくはそれより大きい、通常の半田バンプγ８Ｃとを混在して設けた構成を採用しても構わない。   In the first to third electronic components described above, the solder bumps α8A and / or the solder bumps β8B and the side surfaces are convex outwardly between the pair of the first substrate and the second substrate. In addition, a configuration in which a normal solder bump γ8C having a curvature of the curved surface formed by the side surface is the same as or larger than that of a circle may be used.

半田バンプα８Ａや半田バンプβ８Ｂに加えて、図２（ｃ）に示すような通常の半田バンプγ８Ｃを混在させることにより、個々の半田バンプはその設置された箇所ごとに、多段階に異なる大きさの応力に対応することが可能となる。すなわち、半田バンプα８Ａや半田バンプβ８Ｂが複数配置された中に、半田バンプγ８Ｃが混在してなる配置を採用すると、多岐にわたる外力の方向に対応可能な、高い自由度が期待できるので望ましい。   In addition to the solder bump α8A and the solder bump β8B, a normal solder bump γ8C as shown in FIG. 2C is mixed, so that each solder bump has different sizes in multiple stages at each installation location. It is possible to cope with the stress of. That is, it is desirable to employ an arrangement in which a plurality of solder bumps α8A and a plurality of solder bumps β8B are mixed with solder bumps γ8C because a high degree of freedom that can deal with various external force directions can be expected.

上述した電子部品を構成する半田バンプα８Ａ及び／又は半田バンプβ８Ｂは、前記第一基板または前記第二基板のうち、面積が狭い方の基板に対応して、その基板の周辺又はその近傍領域に配置される構成としてもよい。   The solder bumps α8A and / or solder bumps β8B constituting the electronic component described above correspond to the substrate having the smaller area of the first substrate or the second substrate, and are formed in the vicinity of the substrate or in the vicinity thereof. It is good also as a structure arranged.

一般に、外力がバンプに及ぼす応力の大きさは、第一基板や第二基板の中心から離れるほど大きくなる傾向がある。したがって、例えば第一基板において一番応力が発生する位置に、半田バンプα８Ａ及び／又は半田バンプβ８Ｂを設けることにより、これらのバンプは元より、他のバンプが受ける影響も著しく改善が図れるので望ましい。   In general, the magnitude of stress exerted on a bump by an external force tends to increase as the distance from the center of the first substrate or the second substrate increases. Therefore, for example, by providing the solder bump α8A and / or the solder bump β8B at the position where the most stress is generated on the first substrate, it is desirable that these bumps can be significantly improved not only from the original but also from other bumps. .

具体的には、図５の（ａ）〜（ｃ）に示すように、第一基板または第二基板のうち、面積が狭い方の基板に対応して、その基板の周辺又はその近傍領域のバンプに配置するとより効果的である。何故ならば、バンプに生じる応力の大きさは、基板の中心から離れるほど大きくなるからである。図４において、⇒印は基板に加わりやすい外力の方向を表す。   Specifically, as shown in (a) to (c) of FIG. 5, in the first substrate or the second substrate, corresponding to the substrate having the smaller area, the periphery of the substrate or the vicinity thereof. It is more effective when placed on the bump. This is because the magnitude of the stress generated in the bump increases as the distance from the center of the substrate increases. In FIG. 4, ⇒ represents the direction of external force that is likely to be applied to the substrate.

図５（ａ）は基板が略四角形で小さな面積からなり、その上に設置されるバンプが数十個程度でよい場合である。このような場合には、基板の四隅の各バンプ（◎印）のみに、本発明に係る半田バンプα８Ａ及び／又は半田バンプβ８Ｂを適用すればよい。その他のバンプ（○印）としては、通常の半田バンプγ８Ｃを用いてもよいし、半田バンプα８Ａや半田バンプβ８Ｂを配置しても構わない。   FIG. 5A shows a case where the substrate has a substantially square shape and a small area, and only a few tens of bumps are required on the substrate. In such a case, the solder bump α8A and / or solder bump β8B according to the present invention may be applied only to the bumps (（) at the four corners of the substrate. As other bumps (circles), normal solder bumps γ8C may be used, or solder bumps α8A and solder bumps β8B may be arranged.

図５（ｂ）は基板が略四角形で大きな面積からなり、その上に設置されるバンプが百個を越えるような場合である。このような場合には、基板の四隅ごとに、本発明に係る半田バンプα８Ａ及び／又は半田バンプβ８Ｂを複数個（◎印）、設置すると有効である。その他のバンプ（○印）としては、通常の半田バンプγ８Ｃを用いてもよいし、半田バンプα８Ａや半田バンプβ８Ｂを配置しても構わない。   FIG. 5B shows a case where the substrate is substantially square and has a large area, and there are over 100 bumps placed thereon. In such a case, it is effective to install a plurality of solder bumps α8A and / or solder bumps β8B according to the present invention at the four corners of the substrate. As other bumps (circles), normal solder bumps γ8C may be used, or solder bumps α8A and solder bumps β8B may be arranged.

図５（ｃ）は基板が長方形で長辺が短辺に比べてかなり長い場合である。このような形状の基板は、例えば液晶ドライバ等の用途で多用される。この場合は、基板の中心から遠い位置［図５（ｃ）では左右の一番端がこれに相当する］にあるバンプ（◎印）に、本発明に係る半田バンプα８Ａ及び／又は半田バンプβ８Ｂを適用すると有効である。その他のバンプ（○印）としては、通常の半田バンプγ８Ｃを用いてもよいし、半田バンプα８Ａや半田バンプβ８Ｂを配置しても構わない。   FIG. 5C shows a case where the substrate is rectangular and the long side is considerably longer than the short side. A substrate having such a shape is frequently used in applications such as a liquid crystal driver. In this case, solder bumps α8A and / or solder bumps β8B according to the present invention are formed on bumps (◎) at a position far from the center of the substrate (the left and right ends correspond to this in FIG. 5C). It is effective to apply As other bumps (circles), normal solder bumps γ8C may be used, or solder bumps α8A and solder bumps β8B may be arranged.

なお、基板上に設けた半田バンプα８Ａ及び／又は半田バンプβ８Ｂ（◎印）の配置は一例であり、本発明は図５に示すものに限定されるものではない。   The arrangement of solder bumps α8A and / or solder bumps β8B (（) provided on the substrate is an example, and the present invention is not limited to that shown in FIG.

また、上述した電子部品は半導体パッケージの一種であるウエハレベルＣＳＰに限定されることなく、ＢＧＡとして位置付けされる、半田バンプを介して半導体チップ（半導体装置）と実装基板とを接続させる各種パッケージ形態において適用が可能である。   In addition, the electronic component described above is not limited to a wafer level CSP which is a kind of semiconductor package, and various package forms which are positioned as a BGA and connect a semiconductor chip (semiconductor device) and a mounting substrate via solder bumps. Can be applied.

図３は、本発明に係る第一の電子部品の製造方法の一例を示す断面図であり、（ａ）は第二基板に接触する以前の第一基板の状態を、（ｂ）は第二基板と接触させた後、第一基板に対して第二基板を離間させた状態を、それぞれ表している。以下では、図３に基づき製造方法について説明する。   FIG. 3 is a cross-sectional view showing an example of the first electronic component manufacturing method according to the present invention, where (a) shows the state of the first substrate before contacting the second substrate, and (b) shows the second. A state where the second substrate is separated from the first substrate after being brought into contact with the substrate is shown. Below, a manufacturing method is demonstrated based on FIG.

本発明は、第一基板１と第二基板１０が対向して位置され、第一基板１が有する複数個の導電部６と第二基板１０が有する複数個の導電部１２との間に個別に半田バンプが配されてなる電子部品の製造方法であって、次に示す第一工程と第二工程とを少なくとも具備している。   In the present invention, the first substrate 1 and the second substrate 10 are positioned to face each other, and the first substrate 1 and the second substrate 10 are individually provided between the plurality of conductive portions 6 and the plurality of conductive portions 12 included in the second substrate 10. A method for manufacturing an electronic component in which solder bumps are disposed on the substrate, and includes at least a first step and a second step described below.

図３（ａ）は、第一工程において、予め第一基板１の導電部６上に設けられた半田８に熱を加えて（半田リフロー加熱と呼ぶ）、半田８を溶融状態とし、半田８が略半球状の形態をなしている状態を表している。この溶融状態にある半田に対して第二基板１０の導電部１２を接触させる。この操作により、図３（ｂ）に示すように、２つの基板上に配された導電部間に、溶融状態にある半田が挟まれた構成とする。   In FIG. 3A, in the first step, heat is applied in advance to the solder 8 provided on the conductive portion 6 of the first substrate 1 (referred to as solder reflow heating) to bring the solder 8 into a molten state. Represents a substantially hemispherical shape. The conductive portion 12 of the second substrate 10 is brought into contact with the solder in the molten state. As a result of this operation, as shown in FIG. 3B, the solder in a molten state is sandwiched between the conductive portions arranged on the two substrates.

次の第二工程では、上記第一工程を経た第一基板１に対して、第二基板１０を離間させる方向に移動させるので、溶融されてかつ２つの基板に接した状態にある半田は両方の基板で引っ張られる。そして、２つの基板が適当な離間距離をとるようにしてから、適当な冷却処理を施す。これにより、例えば図３（ｂ）に示すような、側面が外側に凸状であり、かつ、この側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプα８Ａ、及び／又は、側面が外側に凹状である半田バンプβ８Ｂを形成する。   In the next second step, the second substrate 10 is moved away from the first substrate 1 that has undergone the first step, so both the solder that is melted and in contact with the two substrates are both Pulled by the substrate. Then, an appropriate cooling process is performed after the two substrates have an appropriate distance. Thereby, for example, as shown in FIG. 3B, the side surface is convex outward, and the radius of curvature of the curved surface formed by this side surface is the distance between the first substrate and the second substrate. A solder bump α8A larger than the radius of curvature of the circle and / or a solder bump β8B whose side surface is concave outward is formed.

図４は、本発明に係る第二の電子部品の製造方法の一例を示す断面図であり、（ａ）は第二基板に接触する以前の第一基板の状態を、（ｂ）は第二基板と接触させた状態を、（ｃ）は半田に熱を加えた状態を、それぞれ表している。以下では、図４に基づき製造方法について説明する。図４における第一基板１は、封止層７を持たない点が図３に示した第一基板１と相違する。   FIG. 4 is a cross-sectional view showing an example of a second electronic component manufacturing method according to the present invention, where (a) shows the state of the first substrate before contacting the second substrate, and (b) shows the second. A state in which the substrate is brought into contact with the substrate and (c) shows a state in which heat is applied to the solder. Below, a manufacturing method is demonstrated based on FIG. The first substrate 1 in FIG. 4 is different from the first substrate 1 shown in FIG. 3 in that it does not have the sealing layer 7.

本発明は、第一基板１と第二基板１０が対向して位置され、第一基板１が有する複数個の導電部６と第二基板１０が有する複数個の導電部１２との間に個別に半田バンプが配されてなる電子部品の製造方法であって、次に示す第三工程と第四工程とを少なくとも具備している。   In the present invention, the first substrate 1 and the second substrate 10 are positioned to face each other, and the first substrate 1 and the second substrate 10 are individually provided between the plurality of conductive portions 6 and the plurality of conductive portions 12 included in the second substrate 10. A method for manufacturing an electronic component in which solder bumps are disposed on the substrate, and includes at least a third step and a fourth step described below.

第三工程では、予め第一基板１の各導電部６上にそれぞれ異なる量の半田８ａ、８ｂ、８ｃを設けた状態［図４（ａ）］にある第一基板１と、各導電部１２を有する第二基板１０を接近させることにより、第一基板１の各導電部６上に設けた半田８ａ、８ｂ、８ｃに対して第二基板１０の各導電部１２を接触させた状態［図４（ｂ）］とする。この接触を確実なものとするためには、異なる量の半田８ａ、８ｂ、８ｃの高さを揃えることが大切である。したがって、図４（ａ）に示すように、個々の半田８ａ、８ｂ、８ｃの量を変えるためには、各導電部６の上のみならず、第一基板１を構成する絶縁層４の上にはみ出した部分の割合を変えることにより調整される。   In the third step, the first substrate 1 in the state [FIG. 4 (a)] in which different amounts of solder 8a, 8b, and 8c are provided in advance on the respective conductive portions 6 of the first substrate 1 and the respective conductive portions 12 are provided. By bringing the second substrate 10 having the proximity to each other, the respective conductive portions 12 of the second substrate 10 are brought into contact with the solders 8a, 8b, 8c provided on the respective conductive portions 6 of the first substrate 1 [FIG. 4 (b)]. In order to ensure this contact, it is important to align the heights of different amounts of solder 8a, 8b, 8c. Therefore, as shown in FIG. 4A, in order to change the amount of each solder 8a, 8b, 8c, not only on each conductive portion 6, but also on the insulating layer 4 constituting the first substrate 1. It is adjusted by changing the ratio of the protruding part.

第四工程では、前記第三工程により、第一基板１の各導電部６と第二基板１０の各導電部１２で挟まれた状態にある半田８ａ、８ｂ、８ｃに熱を加える。この熱処理により、半田８ａ、８ｂ、８ｃを溶融状態にすると、半田８ａ、８ｂ、８ｃにはそれぞれ表面張力で変形する力が発生する。これにより、半田８ａ、８ｂ、８ｃは、第一基板１に対して第二基板１０を離間させる方向に移動させる。そして、２つの基板が適当な離間距離をとるようにしてから、適当な冷却処理を施す。これにより、側面が外側に凸状であり、かつ、この側面のなす曲面の曲率が、第一基板１と第二基板１０の間隔を直径とする円の曲率より小さい半田バンプα８Ａ、及び／又は、側面が外側に凹状である半田バンプβ８Ｂが自然に形成される［図４（ｃ）］。   In the fourth step, heat is applied to the solders 8a, 8b, and 8c that are sandwiched between the conductive portions 6 of the first substrate 1 and the conductive portions 12 of the second substrate 10 in the third step. When the solders 8a, 8b, and 8c are brought into a molten state by this heat treatment, the solders 8a, 8b, and 8c generate forces that are deformed by surface tension. Accordingly, the solders 8 a, 8 b, and 8 c are moved in a direction in which the second substrate 10 is separated from the first substrate 1. Then, an appropriate cooling process is performed after the two substrates have an appropriate distance. Accordingly, the solder bump α8A whose side surface is convex outward and the curvature of the curved surface formed by the side surface is smaller than the curvature of a circle whose diameter is the distance between the first substrate 1 and the second substrate 10, and / or The solder bumps β8B whose side surfaces are concave outward are naturally formed [FIG. 4C].

例えば、個々の半田が載置される導電部６の面積および形状が同一の場合は、上記の離間距離や溶融される個々の半田量を制御することにより、各種の半田バンプ、すなわち半田バンプα８Ａや半田バンプβ８Ｂ、半田バンプγ８Ｃが混在して有する電子部品を製造することができる。   For example, when the areas and shapes of the conductive portions 6 on which the individual solders are placed are the same, various solder bumps, that is, solder bumps α8A are controlled by controlling the above-mentioned separation distance and the amount of individual solder to be melted. In addition, an electronic component having a mixture of solder bumps β8B and solder bumps γ8C can be manufactured.

同様の構成、すなわち半田バンプα８Ａ、半田バンプβ８Ｂおよび半田バンプγ８Ｃを混在した構成は、個々の半田が載置される導電部６の面積や形状を変更することによっても実現できる。   A similar configuration, that is, a configuration in which the solder bump α8A, the solder bump β8B, and the solder bump γ8C are mixed can be realized by changing the area and shape of the conductive portion 6 on which each solder is placed.

このような半田バンプ、すなわち半田バンプα８Ａ、半田バンプβ８Ｂおよび半田バンプγ８Ｃの製法としては、半田ボール搭載法が好適に用いられるが、これに限定されるものではなく、半田ペースト印刷法、電解メッキ法、ペースト・ディスペンス・フロー法およびフロー半田法などを使用してもよい。これらの製法は、前述したように半田リフロー加熱をする前の半田として異なるものが用いられる点で相違している。   As a method for producing such solder bumps, that is, solder bump α8A, solder bump β8B, and solder bump γ8C, a solder ball mounting method is preferably used, but is not limited thereto, and is not limited to this. The paste, the dispense flow method, the flow solder method, etc. may be used. These manufacturing methods are different in that different solders are used as before solder reflow heating as described above.

本発明に係る電子装置は、上述した半田バンプα８Ａ及び／又は半田バンプβ８Ｂを少なくとも有する電子部品を含むものであれば特に限定されるものではなく、当該電子装置の具体的な例としては、携帯電話やビデオカメラなどが挙げられる。   The electronic device according to the present invention is not particularly limited as long as it includes an electronic component having at least the solder bump α8A and / or the solder bump β8B, and a specific example of the electronic device is a portable device. Examples include telephones and video cameras.

本発明によれば、実装後における優れた耐久性と高い信頼性とを兼ね備えた電子部品とその製造方法及び電子装置を提供することができる。ゆえに、本発明は、外部からの衝撃などを受けやすい商品、例えば携帯電話やビデオカメラにおいて、耐衝撃性の改善や長期信頼性の向上をもたらす。   ADVANTAGE OF THE INVENTION According to this invention, the electronic component which has the outstanding durability after mounting, and high reliability, its manufacturing method, and an electronic apparatus can be provided. Therefore, the present invention brings about improvement in impact resistance and long-term reliability in products that are susceptible to external impacts, such as mobile phones and video cameras.

本発明に係る電子部品の作製に用いる第一基板の構造をを例示する部分断面図である。It is a fragmentary sectional view which illustrates the structure of the 1st substrate used for manufacture of the electronic component concerning the present invention. 本発明に係る電子部品の部分断面図である。It is a fragmentary sectional view of the electronic component which concerns on this invention. 本発明に係る電子部品の製造方法の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing method of the electronic component which concerns on this invention. 本発明に係る電子部品の製造方法の他の一例を示す断面図である。It is sectional drawing which shows another example of the manufacturing method of the electronic component which concerns on this invention. 本発明の電子部品の別な実施形態を示す平面図である。It is a top view which shows another embodiment of the electronic component of this invention. 半田バンプの製造フロー図である。It is a manufacturing flowchart of a solder bump. 従来の電子部品の構造を例示する断面図である。It is sectional drawing which illustrates the structure of the conventional electronic component. 従来の電子部品の実装時、半田にくびれが生じた状態を例示する断面図である。It is sectional drawing which illustrates the state which the constriction produced in the solder at the time of mounting of the conventional electronic component.

符号の説明Explanation of symbols

１ 第一基板、２ 半導体基板、３ 電極、４ 絶縁層、５ 導電層、６ 導電部（電極パッド）、７ 封止層、８ 半田バンプ、８Ａ 半田バンプα、８Ｂ 半田バンプβ、８Ｃ 半田バンプγ、１０ 第二基板、１１ａ、１１ｂ くびれ部、１２ 導電部（電極パッド）。   DESCRIPTION OF SYMBOLS 1 1st board | substrate, 2 semiconductor substrate, 3 electrode, 4 insulating layer, 5 conductive layer, 6 conductive part (electrode pad), 7 sealing layer, 8 solder bump, 8A solder bump alpha, 8B solder bump beta, 8C solder bump γ, 10 second substrate, 11a, 11b constricted portion, 12 conductive portion (electrode pad).

Claims (10)

第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品であって、
前記半田バンプとして、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプαを、少なくとも具備してなることを特徴とする電子部品。 The first substrate and the second substrate are positioned to face each other, and solder bumps are individually arranged between the plurality of conductive portions of the first substrate and the plurality of conductive portions of the second substrate. Electronic components,
As the solder bump, a solder bump α having a convex side surface and a curvature radius of a curved surface formed by the side surface is larger than a curvature radius of a circle whose diameter is a distance between the first substrate and the second substrate. An electronic component comprising at least 第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品であって、
前記半田バンプとして、側面が外側に凹状である半田バンプβを、少なくとも具備してなることを特徴とする電子部品。 The first substrate and the second substrate are positioned to face each other, and solder bumps are individually arranged between the plurality of conductive portions of the first substrate and the plurality of conductive portions of the second substrate. Electronic components,
An electronic component comprising, as the solder bump, at least a solder bump β having a concave side surface. 第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品であって、
前記半田バンプとして、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプαと、側面が外側に凹状である半田バンプβとを、少なくとも具備してなることを特徴とする電子部品。 The first substrate and the second substrate are positioned to face each other, and solder bumps are individually arranged between the plurality of conductive portions of the first substrate and the plurality of conductive portions of the second substrate. Electronic components,
As the solder bump, a solder bump α having a convex side surface and a curvature radius of a curved surface formed by the side surface is larger than a curvature radius of a circle whose diameter is a distance between the first substrate and the second substrate. And at least solder bumps β whose side surfaces are concave on the outside. 一組の前記第一基板と前記第二基板との間に、前記半田バンプα及び／又は前記半田バンプβと、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径と同じもしくはそれより小さい、通常の半田バンプγとを混在して設けたことを特徴とする請求項１乃至３のいずれか１項に記載の電子部品。   Between the set of the first substrate and the second substrate, the solder bump α and / or the solder bump β, the side surface is convex outward, and the radius of curvature of the curved surface formed by the side surface is 4. A normal solder bump γ, which is equal to or smaller than a radius of curvature of a circle having a diameter between the first substrate and the second substrate, is provided in a mixed manner. The electronic component according to any one of the above items. 前記半田バンプα及び／又は前記半田バンプβは、前記第一基板あるいは前記第二基板において、その周辺又はその近傍領域に配置されることを特徴とする請求項４に記載の電子部品。   5. The electronic component according to claim 4, wherein the solder bump α and / or the solder bump β is disposed in the periphery or in the vicinity of the first substrate or the second substrate. 第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品の製造方法であって、
予め前記第一基板の導電部上に設けられた略半球状の半田に熱を加えながら、該半田に対して前記第二基板の導電部を接触させる第一工程と、
前記第一工程の後、前記第一基板に対して前記第二基板を離間させる方向に移動させて、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプα、及び／又は、側面が外側に凹状である半田バンプβを形成する第二工程とを、
少なくとも具備していることを特徴とする電子部品の製造方法。 The first substrate and the second substrate are positioned to face each other, and solder bumps are individually arranged between the plurality of conductive portions of the first substrate and the plurality of conductive portions of the second substrate. An electronic component manufacturing method comprising:
A first step of bringing the conductive portion of the second substrate into contact with the solder while applying heat to a substantially hemispherical solder previously provided on the conductive portion of the first substrate;
After the first step, the second substrate is moved away from the first substrate, the side surface is convex outward, and the curvature radius of the curved surface formed by the side surface is Forming a solder bump α larger than the radius of curvature of a circle whose diameter is the distance between one substrate and the second substrate, and / or a second step of forming a solder bump β whose side surface is concave.
An electronic component manufacturing method comprising at least the electronic component. 第一基板と第二基板が対向して位置され、前記第一基板が有する複数個の導電部と前記第二基板が有する複数個の導電部との間に個別に半田バンプが配されてなる電子部品の製造方法であって、
予め前記第一基板の各導電部上にそれぞれ異なる量の半田を設け、該半田に対して前記第二基板の各導電部を接触させる第三工程と、
前記第三工程の後、前記半田に熱を加えることにより、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径より大きい半田バンプα、及び／又は、側面が外側に凹状である半田バンプβを形成する第四工程とを、
少なくとも具備していることを特徴とする電子部品の製造方法。 The first substrate and the second substrate are positioned to face each other, and solder bumps are individually arranged between the plurality of conductive portions of the first substrate and the plurality of conductive portions of the second substrate. An electronic component manufacturing method comprising:
Providing a different amount of solder on each conductive portion of the first substrate in advance, and contacting each conductive portion of the second substrate with the solder;
After the third step, by applying heat to the solder, the side surface is convex outward, and the radius of curvature of the curved surface formed by the side surface is the diameter between the first substrate and the second substrate. A solder bump α larger than the radius of curvature of the circle and / or a fourth step of forming a solder bump β whose side surface is concave outward,
An electronic component manufacturing method comprising at least the electronic component. 前記半田バンプα及び／又は前記半田バンプβを、前記第一基板又は前記第二基板の何れか一方の周辺又はその近傍領域に作製し、その他の領域には、側面が外側に凸状であり、かつ、該側面のなす曲面の曲率半径が、前記第一基板と前記第二基板の間隔を直径とする円の曲率半径と同じもしくはそれより小さい、通常の半田バンプγを作製することを特徴とする請求項６又は７に記載の電子部品の製造方法。 The solder bumps α and / or the solder bumps β are prepared in the vicinity of one of the first substrate and the second substrate or in the vicinity thereof, and in other regions, the side surfaces are convex outward. In addition, a normal solder bump γ in which the radius of curvature of the curved surface formed by the side surface is equal to or smaller than the radius of curvature of a circle whose diameter is the distance between the first substrate and the second substrate is produced. The manufacturing method of the electronic component of Claim 6 or 7. 前記半田バンプα、前記半田バンプβおよび前記半田バンプγは、半田ボール搭載法、半田ペースト印刷法、電解メッキ法、ペーストディスペンスフロー法およびフロー半田法からなる群から選択される方法で形成されることを特徴とする請求項６乃至８のいずれか１項に記載の電子部品の製造方法。 The solder bump α, the solder bump β, and the solder bump γ are formed by a method selected from the group consisting of a solder ball mounting method, a solder paste printing method, an electrolytic plating method, a paste dispense flow method, and a flow solder method. The method for manufacturing an electronic component according to claim 6, wherein the electronic component is manufactured as described above. 請求項１〜５のいずれか１項に記載の電子部品を含むことを特徴とする電子装置。
An electronic device comprising the electronic component according to claim 1.
JP2003299287A 2003-08-22 2003-08-22 Electronic component, its manufacturing method, and electronic device Pending JP2005072212A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081150A (en) * 2005-09-14 2007-03-29 Rohm Co Ltd Semiconductor device and substrate
JP2013211854A (en) * 2009-06-03 2013-10-10 Qualcomm Inc Apparatus and method for frequency generation
CN109449271A (en) * 2018-11-01 2019-03-08 佛山市国星半导体技术有限公司 A kind of LED chip and preparation method thereof with solder electrode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081150A (en) * 2005-09-14 2007-03-29 Rohm Co Ltd Semiconductor device and substrate
JP2013211854A (en) * 2009-06-03 2013-10-10 Qualcomm Inc Apparatus and method for frequency generation
CN109449271A (en) * 2018-11-01 2019-03-08 佛山市国星半导体技术有限公司 A kind of LED chip and preparation method thereof with solder electrode
CN109449271B (en) * 2018-11-01 2024-04-16 佛山市国星半导体技术有限公司 LED chip with solder electrode and manufacturing method thereof

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