TWI754799B - 半導體製程方法與半導體裝置 - Google Patents

半導體製程方法與半導體裝置 Download PDF

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TWI754799B
TWI754799B TW108110369A TW108110369A TWI754799B TW I754799 B TWI754799 B TW I754799B TW 108110369 A TW108110369 A TW 108110369A TW 108110369 A TW108110369 A TW 108110369A TW I754799 B TWI754799 B TW I754799B
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dielectric material
substrate
active region
gate structure
shallow trench
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TW108110369A
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TW202004930A (zh
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郭哲銘
黃彥鈞
彭治棠
包天一
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台灣積體電路製造股份有限公司
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    • B05D3/065—After-treatment
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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Abstract

本發明實施例大抵上關於半導體裝置，且特別關於形成於半導體裝置中的介電材料。本發明實施例提供以循環旋轉塗布製程形成介電材料層的方法。在一實施例中，於基板上形成介電材料的方法包括旋轉塗布介電材料的第一部分於基板上、固化在基板上的介電材料第一部分、旋轉塗布介電材料的第二部分於基板上、以及熱退火介電材料以於基板上形成經退火的介電材料。

Description

半導體製程方法與半導體裝置
本發明實施例關於半導體裝置，且特別關於形成於半導體裝置中的介電材料。
半導體積體電路(IC)工業經歷了快速地成長。積體電路材料與設計之技術上的進展造就了積體電路之世代，而每一世代相對於前一世代具有較小且更為複雜的電路。在積體電路發展的過程中，功能密度(functional density，例如：單位晶片面積之互連裝置的數量)普遍地增加，而幾何尺寸(geometry size，例如：使用一製程可以形成之最小元件(或導線))則縮小。此縮小化的過程通常通過提高生產效率和降低相關成本來提供益處。然而，縮小化亦帶來了未出現於先前尺寸較大之世代的挑戰。在製造介電材料時，對於沉積與退火製程不準確與不適當之控制可能會不利地降低裝置結構之電氣性能。
本發明的一些實施例提供一種半導體製程方法。上述方法包括旋轉塗布介電材料的第一部分於基板上、固化在基板上的介電材料的第一部分、旋轉塗布介電材料的第二部分於基板上、以及熱退火介電材料以於基板上形成經退火的介電材料。
本發明的一些實施例提供一種半導體製程方法。上述方法包括旋轉塗布包括全氫聚矽氮烷化合物的第一溶液於基板上、固化第一溶液以在基板上形成介電材料之經固化的第一部分、旋轉塗布包括全氫聚矽氮烷化合物的第二溶液於基板上的介電材料經固化的第一部分上以於基板上形成介電材料的第 二部分、以及退火介電材料經固化的第一部分與第二部分。
本發明的一些實施例提供一種結構。上述結構包括位於基板上的淺溝槽隔離(shallow trench isolation，STI)與主動區。淺溝槽隔離鄰接主動區。上述結構亦包括位於主動區上的閘極結構。源極/汲極區域位於閘極結構附近的主動區中。上述結構亦包括第一介電材料。第一介電材料位於主動區與淺溝槽隔離上且從閘極結構橫向地設置。上述結構亦包括位於閘極結構與第一介電材料上的第二介電材料。淺溝槽隔離、第一介電材料與第二介電材料中之至少一者包括氮含量為約0.005原子百分比至約0.5原子百分比的氧化矽材料。
100:製程
102、104、106、108、112:操作步驟
110:迴圈
201:基板
202:介電材料之第一部分
204:介電材料之第一固相部分
206:介電材料之第二部分
208:經退火的介電材料
210:介電材料
250:介電材料之第一部分之上表面
252:介電材料之第一部分之下表面
260:介電材料之額外之部分
262:介電材料之第二固相部分
302:塗布儀器設備
304:固化儀器設備
306:退火儀器設備
308:迴圈
310:箭頭
208a:第一層間介電質
208b:第二層間介電質
208c:金屬間介電質
208d:淺溝槽隔離
501:導電填充材料
503:導電特徵部件
506:蝕刻停止層
514:阻障層
516:襯層
546:鰭片結構
553:導電填充材料
554:閘極間隔物
556:磊晶源極/汲極區
560:接觸蝕刻停止層
570:介面介電質
572:閘極介電層
574:共形層
576:導電填充材料
590:導電特徵部件
594:黏合層
596:阻障層
598:矽化物區
602:濕蝕刻速率軌跡線
藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多特徵部件(feature)並未按照比例繪製。事實上，為了能清楚地討論，各種特徵部件的尺寸可能被任意地放大或縮小。
第1圖係為一流程圖，其根據一些實施例繪示出製造半導體裝置之介電材料之製程的例子。
第2A至2E圖根據一些實施例繪示出於例示性之製造介電材料之製程之期間各中間結構的剖面圖。
第3圖描繪出一流程圖，其根據一些實施例繪示出在不同儀器設備之間轉移基板之順序的例子。
第4A至4D圖根據一些實施例繪示出於例示性之製造介電材料之製程之期間各中間結構的剖面圖。
第5A與5B圖根據一些實施例繪示出一半導體裝置之剖面圖，且其介電材料係以第1圖所例示之製程形成。
第6圖根據一些實施例繪示出介電材料之濕蝕刻速率軌跡線(wet etching rate trace line)，其中介電材料係以第1圖所例示之製程形成。
以下內容提供了很多不同的實施例或範例，用於實施本發明實施例的不同特徵部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中若提及第一特徵部件形成於第二特徵部件之上(over或on)，可能包含第一和第二特徵部件直接接觸的實施例，也可能包含額外的特徵部件形成於第一和第二特徵部件之間，而使得第一和第二特徵部件不直接接觸的實施例。另外，本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的，其本身並非代表所討論各種實施例及/或配置之間有特定的關係。
此外，此處可能使用空間上的相關用語，例如「在...之下」、「在...下方」、「下方的」、「在...上方」、「上方的」和其他類似的用語可用於此，以便描述如圖所示之一元件或特徵部件與其他元件或特徵部件之間的關係。此空間上的相關用語除了包含圖式繪示的方位外，也包含使用或操作中的裝置的不同方位。裝置可以被轉至其他方位(旋轉90度或其他方位)，則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
本發明實施例大抵上關於半導體裝置，且特別關於形成於半導體裝置中的介電材料。本發明實施例提供以旋轉塗布製程(spin-on coating process)形成介電材料之方法。以循環塗布製程(cyclic coating process)形成介電材料。以各塗布製程形成介電材料之一部分。於各塗布製程之後進行固化製程(curing process)以固化介電材料。固化製程有助於將水分/溶劑(moisture/solvent)自介電材料驅出。在循環塗布與固化製程之後，進行退火製程以密化(densifying)介電材料之薄膜結構並氧化介電材料。
於此所描述之例示性之實施例係於在前段製程(Front End Of the Line(FEOL))中形成介電材料的脈絡下進行描述。本發明實施例一些層面之實施可被用於其他製程。舉例而言，可於後段製程(Back End Of the Line(BEOL)processing)中及/或中段製程(Middle End Of the Line(MEOL)processing)中形成導電特徵部件。例示性之方法與結構的一些變化被描述。所屬領域具有通常知識者可輕易地理解其他可能之修飾改變係於其他實施例的範圍中被考慮到。雖然可以特定的順序描述方法實施例，各種其他方法實施例可以任何合理的順序進行且可包括較少或較多的步驟。在一些圖示中，一些所繪示之元件或特徵部件的標號可能被省略，以避免造成其他元件或特徵部件不清楚的情形，這是為了便於描繪這些圖示。
第1圖係為一流程圖，其根據一些實施例例示性地繪示出製造半導體裝置之介電材料之製程100。第2A至2E圖係根據第1圖之流程圖繪示出於各製造階段之介電材料的剖面圖。所屬領域具通常知識者應理解，於圖示或於此之敘述中並未描繪於半導體裝置中形成介電材料之全部的製程以及相關的結構，儘管第5A與5B圖中繪示出一例示性之結構。
流程圖係以提供基板201開始於操作步驟102(如第2A圖所示)，將以第1圖之製程100於基板201上形成介電材料。基板201係為半導體基板，且係為或包括塊狀(bulk)半導體基板(例如：晶圓)、絕緣層上半導體(semiconductor-on-insulator(SOI))基板或其他基板。基板201之半導體材料可包括或可為選自矽(例如：結晶矽，如Si<100>或Si<111>)、矽鍺、鍺、砷化鎵、或其他半導體材料中之至少一者之材料。半導體材料可被p型或n型摻質摻雜或未被摻雜。在一些實施例中，絕緣層上半導體結構被用於基板201，基板201可包括設置於絕緣層上的半導體材料，上述絕緣層可為設置於半導體基板中的埋藏絕緣體，或者為玻璃或藍寶石(sapphire)基板。在此所述的實施例中，基板201係為含矽的材料，例如：結晶矽基板。此外，基板201不限定為任何特定的尺寸、形狀 或材料。基板201可為圓形(round/circular)基板，其直徑可為200mm、300mm、或其他大小(例如：450mm等)。視需求，基板201亦可為任何多邊形、正方形、矩形、曲形、或其他非圓形的工作件，例如：多邊形基板。
基板201可包括或不包括形成於其上的結構。在一些實施例中，基板201可包括於積體電路之製造之各步驟中事先形成於基板201上的多層結構。舉例而言，上述結構可包括於前段製程中所形成的結構，例如包括淺溝槽隔離結構、閘極結構、接觸結構及/或其他適當之結構。舉例而言，基板201可包括場效電晶體(Field Effect Transistors(FETs)，例如：鰭式場效電晶體(FinFETs)、平面場效電晶體、垂直式環繞式閘極電晶體(vertical gate all around FETs(VGAA FETs))、或類似之場效電晶體)、二極體、電容器、電感器及其他裝置之部分。在一些例子中，上述結構可更包括於後段製程中所形成之結構之部分，其中各個裝置或元件以例如金屬線、導孔(vias)及/或形成於介電材料中的導電填充材料互連。應注意的是，在形成一材料層於基板201之上之前，可於基板201之上形成額外的結構、其他材料層、或裝置結構。各種裝置可在基板201之上。
於操作步驟104，進行第一塗布製程，以於基板201上形成介電材料210之第一部分202(如第2B圖所示)。如第3圖所示，基板201可被移置至塗布儀器設備302以進行塗布製程。塗布製程可為旋轉塗布製程、噴墨製程(inkjet process)、急驟蒸發器(flash evaporator)製程、噴塗披覆(spray coating)、噴塗塗布(aerosol coating)或類似之製程。在一些例子中，將含矽的液體前驅物引導至基板201之表面以進行第一塗布製程。使用旋轉塗布製程將含矽的液體前驅物塗布至基板201上。進行旋轉塗布製程，以於基板201之表面上全域地形成介電材料210之第一部分202，其可包括填充可能形成於基板201中的溝槽(trenches)、凹陷(recesses)、孔(apertures)、空隙(voids)、間隙(gaps)、表面裂痕(surface discontinuities)及/或段差(steps)。在一些例子中，含矽的液體前驅物包括全氫聚矽氮烷 (perhydro-polysilazane(PHPS))。全氫聚矽氮烷化合物具有-(SiH2NH)n-之化學式，n係為正整數。全氫聚矽氮烷化合物包含Si-N鍵作為重複單元且係為由Si、N以及H所組成的含矽高分子。全氫聚矽氮烷化合物具有分子中之線性結構、鏈結構、交聯結構或環狀結構。
在一些例子中，全氫聚矽氮烷化合物包括在所欲範圍內的分子量。舉例而言，全氫聚矽氮烷化合物之平均分子量可大於約300g/mol，例如：為約5000g/mol至約8000g/mol。分子量在上述範圍之全氫聚矽氮烷化合物於在基板上形成介電層時提供足夠的Si比率，以於後續的退火製程之後提供較佳的薄膜品質。
通常以溶液的形式提供全氫聚矽氮烷化合物，其中上述溶液包括約5至約50重量百分比之全氫聚矽氮烷、以及約30至約95重量百分比之溶劑。適當之溶劑包括二甲苯(xylene)、二丁醚(dibutyl ether)、三酚(trihydroxy benzene)、乙二醇(ethylene glycol)、甲苯(toluene)、啶(pyridine)、己烷(hexane)、或類似之溶劑。
由於全氫聚矽氮烷化合物包括由Si、N及H所組成的含矽高分子，形成於基板201上之介電材料210之第一部分202係為含有矽與氮的材料，且於後續將在操作步驟112之熱處理製程中經由氧化被轉化成含有矽與氧的材料。
在一些實施例中，可將全氫聚矽氮烷化合物塗布至基板201之上以形成介電材料210之第一部分202，其厚度為約50nm至約250nm，例如：為約70nm至約150nm(例如：為約100nm)。
於約5℃至約80℃(例如：為約10℃至約30℃(例如：約為室溫或為約25℃))之溫度下進行塗布製程。
於操作步驟106，在將介電材料210之第一部分202塗布至基板201上之後，固化介電材料210之第一部分202。將基板201與其上之第一部分202從 塗布儀器設備302轉置至固化儀器設備304(如第3圖所示)，以進行固化製程。固化製程將水分/溶劑從介電材料210之第一部分202移除，以形成介電材料210之第一固相部分204(如第2C圖所示)。由於介電材料210之第一部分202被固化，介電材料210之第一部分202中之水分與溶劑被驅出，而形成了介電材料210之第一固相部分204。在一些實施例中，固化儀器設備304(於其中可進行操作步驟104之固化製程)包括加熱板、烘箱、受熱腔體或適當之儀器。紫外光光源可提供輻射線，以產生熱能而使介電材料210之第一部分202之水氣或溶劑汽化(evaporate)、分解(decompose)或“被燒除(burn out)”。由紫外光輻射線所提供之熱能提供了用以將介電材料210之第一部分202分解之熱能，因而形成了可被輕易地從固化儀器設備304泵出(pumped out)及移除的揮發性氣相副產物。
在一些實施例中，固化製程為紫外線熱固化製程，且將基板暴露至紫外線熱能(可使用或不使用固化氣體)以進行固化製程。在一些實施例中，於紫外線熱固化製程中使用固化氣體，固化氣體之形式可為氣體或是汽化液體蒸汽(vaporized liquid vapor)，其可有助於將介電材料210之第一部分202之水分及/或溶劑反應並移除。在固化儀器設備304中開啟紫外光光源單元(例如：固化儀器設備304中的紫外光燈)的情況下進行紫外線熱固化製程而有助於解離(dissociation)及分解(decomposition)化學鍵，以從介電材料210之第一部分202移除水分及/或溶劑。當使用固化氣體時，可在使固化氣體流入固化儀器設備304的同時、之前或之後開啟紫外光光源單元。
由紫外光輻射線所提供的紫外線熱能可有效率地將介電材料210之第一部分202之水分及/或溶劑汽化成氣體或氣相，而可輕易地使其從基板表面被移除並從固化儀器設備304被泵出。由於在第一部分202中的溶劑通常具有相對較低的汽化點(例如：低於150℃)，因此經由使用來自於紫外光輻射線的紫外線熱能可將溶劑汽化並促進介電材料210之第一部分202中之全氫聚矽氮烷化合物 的持續分解。在一些實施例中，可選擇來自於紫外光光源之輻射線的波長來放射(activate)特定之能量模式(energy modes)，以促進第一部分202中之全氫聚矽氮烷化合物之分解並將水分與溶劑驅出。此外，紫外光功率位準(power level)亦被控制在相對較低的範圍，以確保由紫外光所提供的熱能均勻地傳遞通過介電材料210之第一部分202之整體厚度(bulk thickness)。據信，慢的熱固化製程有助於使高分子全氫聚矽氮烷化合物之分解製程相對較為全面。因此，橫跨第一部分202之Si-N與Si-H鍵被分解以形成第一部分202之含有氮化矽的材料，其橫跨第一部分202具有相對較強的鍵結。第一部分202之均勻的接合結構有助於在後續所進行之氧化製程中使氧接合至結構中。因此，介電材料210之含有氮化矽的材料可橫跨介電材料210之塊狀結構被有效率且均勻地轉化成含有矽與氧的材料。
在一些例子中，紫外光的波長為約100nm至約300nm。紫外光可為廣譜(broad spectrum)紫外光，或可具有單一波長。紫外線熱固化製程之處理時間可為約15秒至約900秒，例如：為約60秒。在熱固化製程之期間，基板溫度被加熱至為約20℃至約400℃，例如：為約200℃至約350℃(例如：為約300℃)。於固化製程中經由控制其上設置有基板之基板支撐台之溫度裝置加熱至基板溫度。紫外光功率可為約500mJ/cm2至約6000mJ/cm2，例如：為約2500mJ/cm2。於製程中，腔體壓力可為約5milliTorr至約200Torr，例如：為約80Torr。在一些特定的實施例中，紫外光光源提供波長約為200nm之輻射線，以自基板201上之介電材料210之第一部分202移除水分/溶劑。將紫外光功率控制在約為4000mJ/cm2。
將介電材料210之第一部分202之厚度維持在所欲之範圍可促進相對均勻之熱固化製程。過厚之介電材料210之第一部分202之厚度(例如：大於200nm)可能會影響熱能傳導(propagation)或傳遞(transmission)橫跨第一部分202。因此，第一部分202之上表面250與下表面252之間可能會出現熱梯度而造成不均勻之薄膜性質與接合結構，這最終可能導致裝置性能不良。不均勻之薄膜性質通 常會造成薄膜品質控制不良以及橫跨介電材料210之不相等的濕蝕刻速率，這可能造成不期望之裝置性能控制不良。因此，將介電材料210之第一部分202之厚度控制為小於200nm，例如：為約100nm至約150nm。因此，來自熱固化製程之熱能可被慢慢地且均勻地傳遞橫跨介電材料210之第一部分202，藉此將溶劑與水分驅出，形成第一固相部分204。
於操作步驟108，進行第二塗布製程，以於基板201上形成介電材料210之第二部分206(如第2D圖所示)。在此操作步驟中，如第3圖與迴圈308所示，可將基板201傳遞回到塗布儀器設備302以進行塗布製程。在操作步驟108之塗布製程類似於在操作步驟104之塗布製程。因此，塗布製程亦為旋轉塗布製程。在一些例子中，將含矽的液體前驅物引導至基板201之表面以進行第二塗布製程。如前所述，含矽的液體前驅物包括全氫聚矽氮烷(PHPS)。全氫聚矽氮烷化合物的化學式為-(SiH2NH)n-，其中n為正整數。全氫聚矽氮烷化合物含有作為重複單元之Si-N鍵且係為由Si、N與H所組成之含矽高分子。全氫聚矽氮烷化合物具有分子中之線性結構、鏈結構、交聯結構或環狀結構。
在一些例子中，全氫聚矽氮烷化合物包括在所欲範圍內的分子量。舉例而言，全氫聚矽氮烷化合物之平均分子量可大於約300g/mol，例如：為約5000g/mol至約8000g/mol。
通常以溶液的形式提供全氫聚矽氮烷化合物，其中上述溶液包括約5至約50重量百分比之全氫聚矽氮烷、以及約30至約95重量百分比之溶劑。適當之溶劑包括二甲苯、二丁醚、三酚、乙二醇、甲苯、啶、己烷、或類似之溶劑。由於全氫聚矽氮烷化合物包括由Si、N及H所組成的含矽高分子，形成於基板201上之介電材料210之第二部分206係為含有矽與氮的材料，且於後續將經由熱退火製程被轉化成含有矽與氧的材料。
在一些實施例中，可將全氫聚矽氮烷化合物塗布至基板201上以形 成介電材料210之第二部分206，其厚度為約50nm至約250nm，例如：為約70nm至約150nm，例如：為約100nm。
於操作步驟112，於在基板201之上形成介電材料210之第二部分206之後，進行熱退火製程以將包括第一固相部分204與第二部分206的介電材料210轉變成經退火的介電材料208(如第2E圖所示)。由熱退火製程所提供之熱能可密化並強化介電材料210之接合結構。由於操作步驟112之熱退火製程係於旋轉塗布第二部分206之後進行，第二部分206係直接暴露於由操作步驟112之熱退火製程所提供之熱能，因此在操作步驟106被用來固化第一部分202之固化製程可被省略。
在熱退火製程中，供給退火氣體，其包括至少一含氧的氣體。來自於含氧氣體的氧與來自於聚矽氮烷化合物之矽原子反應，而將含有氮化矽之膜層轉化成氧化矽。由熱退火製程所提供之熱能將Si-N鍵打斷，使得氧原子接合並附著至矽原子，而使所形成之經退火的介電材料208為氧化矽。因此，熱退火製程期間之溫度通常被預先決定，以經由熱退火製程提供足以將來自全氫聚矽氮烷之Si-N鍵轉化成Si-O鍵之熱能，藉此形成所欲之氧化矽材料。
在一些實施例中，如第3圖所示，可於退火儀器設備306中進行熱退火製程。於在塗布儀器設備302中形成介電材料210之第二部分206之後，如箭頭310所示，可將基板201轉置至用於熱退火製程之退火儀器設備306。於退火期間，供給退火氣體。可被供給於退火氣體混合物中之氣體可包括含氧氣體，例如：O2、O3、N2O、水氣(steam，H2O)、H2O2、大氣(air)、CO2、CO、類似之氣體或上述之組合。在一些例子中，退火氣體混合物可包括水氣、大氣或O2。在製程中，製程溫度可大於約350℃，例如：為約400℃至約1200℃，例如：為約600℃。
在一些實施例中，熱退火製程之時間可為約10分鐘至約600分鐘，例如：為約60分鐘至約180分鐘，例如：為約120分鐘。腔體的壓力可為約0.1Torr至 約100Torr，例如：為約0.1至約50Torr，例如：為約0.5Torr。
於操作步驟112所進行之熱退火製程可有助於將介電材料210轉化成氧化矽材料並且密化經退火之介電材料208之薄膜結構。因此，可在所形成之經退火的介電材料208中形成強度較高之接合結構以及矽氧鍵。此外，熱退火製程亦可有助於打斷Si-N鍵並且自經退火的介電材料208將懸鍵(dangling bonds)或弱矽-氫鍵驅出。這可提供密化之薄膜結構且可增進薄膜品質。此外，由於熱退火製程中之熱膨脹，相較於未熱處理之介電材料210，經退火的介電材料208之厚度可增加約百分之十至約百分之三十之數量。
承前述，來自介電材料210之第一部分202之溶劑及/或水分已預先被驅出，於熱退火製程中來自退火氣體之氧元素可有效率地向下穿過介電材料210之整體厚度(例如：向下至介電材料210之第一部分202)，藉此使介電材料210之第一固相部分204與第二部分206兩者中之含有氮化矽的材料轉化成氧化矽材料。
在一些實施例中，經退火的介電材料208的厚度可為約300至約450nm。如前所述，將介電材料210之每一次塗布(例如：第一部分202與第二部分206)控制在約為50nm至約為250nm之厚度。藉此，在一些例子中，可發生於熱退火製程中之氧化轉化製程。相反地，當所欲之經退火的介電材料208為具有較大厚度(例如：大於兩次塗布(例如：於操作步驟104之第一部份202之第一塗布與於操作步驟108之第二部份206之第二塗布)所能提供的厚度)時，可重複地進行操作步驟104、106(如迴圈110與第1圖所示)，以在操作步驟112之熱退火製程之前塗布多過於兩個之介電材料210之部分。
舉例而言，當所欲之經退火的介電材料208之厚度為大於約400nm時，在將介電材料210之第一部分202固化而形成第一固相部分204之後，進行類似於操作步驟104之額外的塗布製程。上述之額外的塗布製程於第一固相部分 204之上塗布介電材料210之額外之部分260(如第4A圖所示)。介電材料210之額外之部分260類似於第一部分202，具有經由塗布全氫聚矽氮烷化合物而形成之含矽與氮的材料。類似地，在操作步驟104之塗布製程之後，再次進行操作步驟106之固化製程以固化額外之部分260，將額外之部分260轉化成第二固相部分262(如第4C圖所示)。
應注意的是，可根據需求進行多次之操作步驟104與106之循環以形成介電材料210之多個部分，直到形成介電材料210之最後部分(例如：第二部分206)。重複操作步驟104與106之間之塗布與固化製程對於使用相應之固化製程形成介電材料210之小部分是有幫助的，藉此於操作步驟112之熱退火製程之前提供具有極少溶劑與水分殘留於介電材料210中之薄膜結構。因此，當進行操作步驟112之熱退火製程時，所提供之熱能可順利地傳遞與傳導至介電材料210之整體，藉此，經由將含氮化矽之材料有利地轉化成含氧化矽之材料而形成經退火的介電材料208並殘留極少或未殘留氮含量。應注意的是，在一些例子中，於經退火的介電材料208中可殘留有極少的氮含量。在此些例子中，氮含量可小於約5原子百分比(atomic percent)，例如：為約0.005至約5原子百分比，且可於操作步驟112之熱退火製程之後於經退火的介電材料208中檢測氮含量。
第5A圖例示性地描繪半導體裝置之剖面圖，其中可使用由第1圖之製程所形成之經退火的介電材料208。在第5A圖所描繪的例子中，經退火的介電材料208(表示為208a、208b、208c)可被用來作為第一層間介電質(interlayer dielectric(ILD))208a、第二層間介電質208b與金屬間介電質(intermetal dielectric(IMD))208c之任一者。
基板201包括形成於基板201之上部之上的鰭片結構546。磊晶源極/汲極區556係形成於鰭片結構546中。閘極結構係形成於鰭片結構546之上。任一閘極結構包括介面介電質(interfacial dielectric)570、閘極介電層572、一或多個可 選的共形(conformal)層574、以及閘極導電填充材料576。閘極間隔物554係沿著閘極結構之側壁形成。介面介電質570係沿著各閘極間隔物554之間之鰭片結構546之表面。閘極介電層572係共形地位於介面介電質570上且沿著各閘極間隔物554之側壁並位於各閘極間隔物554之側壁之間。一或多個可選的共形層574係共形地位於閘極介電層572上且可包括一或多個阻障層及/或蓋層以及一或多個功函數調整層。閘極導電填充材料576係在一或多個可選的共形層574之上。接觸蝕刻停止層(contact etch stop layer(CESL))560係共形地位於磊晶源極/汲極區556之表面以及閘極間隔物554之側壁。
第一層間介電質208a係在接觸蝕刻停止層560之上。可經由描繪於第1圖以及第2A-2E圖中或第4A-4D圖中之製程100形成第一層間介電質208a，接觸蝕刻停止層560與閘極間隔物554則形成於其中。在一些例子中，在形成第一層間介電質208a時，虛設閘極結構係設置在閘極間隔物554之間，而在形成第一層間介電質208a之後(例如：經由第1圖中所描繪之製程100)，以第5A圖中所繪示之閘極結構取代虛設閘極結構。接著，於閘極結構與第一層間介電質208a之上形成第二層間介電質208b。可經由描繪於第1圖以及第2A-2E圖中或第4A-4D圖中之製程100形成第二層間介電質208b。所形成之導電特徵部件503、590係穿過第一層間介電質208a及/或第二層間介電質208b以各自電性連接閘極結構與磊晶源極/汲極區556。舉例而言，在所繪示的例子中，導電特徵部件590包括黏合層594、黏合層594上之阻障層596、磊晶源極/汲極區556上之矽化物區598、以及阻障層596上之導電填充材料501。舉例而言，在所繪示的例子中，導電特徵部件503包括黏合層594、黏合層594上之阻障層596、以及阻障層596上之導電填充材料501。
蝕刻停止層506係形成於第二層間介電質208b以及導電特徵部件590、503之上。金屬間介電質208c係形成於蝕刻停止層506之上。可經由描繪於 第1圖以及第2A-2E圖中或第4A-4D圖中之製程100形成金屬間介電質208c。所形成之導電特徵部件(包括阻障層514、阻障層514上之襯層516、以及襯層516上之導電填充材料553)係穿過金屬間介電質208c與蝕刻停止層506並且電性連接至導電特徵部件590、503。
在一些例子中，經由第1圖中所描繪之製程100所形成之經退火的介電材料208(於第5A圖中表示為208a、208b、208c)被用以形成第一層間介電質208a、第二層間介電質208b與金屬間介電質208c。由於在操作步驟104所使用之全氫聚矽氮烷化合物係為基於液體/溶液之化合物，全氫聚矽氮烷化合物可填充基板201上之溝槽、凹陷、孔、空隙、間隙、表面裂痕及/或段差。
此外，第5B圖描繪第5A圖之半導體裝置的另一個剖面圖，其具有形成於基板201之上的淺溝槽隔離208d。第5B圖之剖面圖平行於第5A圖之剖面圖且位於形成在基板201之上之鄰近之鰭片結構546之間。可以前文以第1圖以及第2A-2E圖或第4A-4D圖描繪之經退火的介電材料208形成淺溝槽隔離208d。由於淺溝槽隔離208d係在溝槽中，可以所欲之間隙填充能力將包括全氫聚矽氮烷化合物之基於液體/溶液之化合物填充於基板201上之鰭片結構546之間之溝槽，以形成具有所欲之輪廓及薄膜性質之淺溝槽隔離208d。第5B圖繪示於一剖面之磊晶源極/汲極區556，其中磊晶源極/汲極區556可合併於鄰近之鰭片結構546之間。在其他例子中，磊晶源極/汲極區556可能不會出現在類似的剖面中，這是因為磊晶源極/汲極區556未合併於鄰近之鰭片結構546之間。
第6圖繪示經退火的介電材料208之濕蝕刻速率軌跡線602。濕蝕刻速率軌跡線602係繪示為從經退火的介電材料208蝕刻掉之厚度(例如：蝕刻深度)的函數。由濕蝕刻速率軌跡線602可以看出經退火的介電材料208的薄膜性質大抵上類似且均勻，因此，在濕蝕刻製程之下，經退火的介電材料208係被以相對均勻且/或穩定的蝕刻速率蝕刻，其中蝕刻速率偏差(deviation)△R小於20Å/min。
本發明實施例之實施提供以多個旋轉塗布製程(例如：循環之旋轉塗布製程)及後續之熱退火製程形成介電材料之方法。在至少一旋轉塗布製程與紫外線熱固化製程之後，進行第二旋轉塗布製程與隨後之熱退火製程。經由在進行熱退火製程形成介電材料之前實施多個旋轉塗布製程，旋轉塗布層之溶劑與水分可被有效率地驅出，而可達成於後續熱退火製程之完全氧化製程。因此，可得到具有氧化矽材料且氮含量小於5原子百分比之經退火之介電材料。
在一實施例中，半導體製程方法包括旋轉塗布介電材料之第一部分於基板上、固化基板上之介電材料之第一部分、旋轉塗布介電材料之第二部分於基板上、以及熱退火介電材料以於基板上形成經退火之介電材料。
在另一實施例中，半導體製程方法包括旋轉塗布包括全氫聚矽氮烷化合物之第一溶液於基板上、固化第一溶液以於基板上形成介電材料之經固化之第一部分、旋轉塗布包括全氫聚矽氮烷化合物之第二溶液於基板上之介電材料之經固化之第一部分之上以於基板上形成介電材料之第二部分、以及退火介電材料之經固化之第一部分與第二部分。
在又一實施例中，結構包括位於基板上的淺溝槽隔離與主動區、位於主動區上的閘極結構、位於主動區與淺溝槽隔離上且從閘極結構橫向地設置的第一介電材料、以及位於閘極結構與第一介電材料上的第二介電材料。淺溝槽隔離鄰接(abut)主動區。源極/汲極區位於閘極結構附近的主動區中。第一介電材料、第二介電材料與淺溝槽隔離中之至少一者包括氮含量為約0.005原子百分比至約0.5原子百分比的氧化矽材料。
以上概述數個實施例之特徵部件，以使本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技 術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明實施例的精神與範圍，且他們能在不違背本發明實施例之精神和範圍下，做各式各樣的改變、取代和替換。因此，本發明實施例之保護範圍當視後附之申請專利範圍所界定為準。
100:製程
102、104、106、108、112:操作步驟
110:迴圈

Claims (9)

  1. 一種半導體製程方法，該方法包括：在一基板上提供一主動區與一淺溝槽隔離，其中該淺溝槽隔離鄰接該主動區；在該主動區上提供一閘極結構，其中一源極/汲極區域位於該閘極結構附近的該主動區中；提供相鄰於該閘極結構設置的一閘極間隔物；旋轉塗布一介電材料的一第一部分於該基板上；對該介電材料的該第一部分提供一紫外線能量以分解在該介電材料的該第一部分中的Si-N與Si-H鍵以形成氮化矽，來固化在該基板上的該介電材料的該第一部分；在固化該介電材料的該第一部分之後，接著旋轉塗布該介電材料的一第二部分於該介電材料的該第一部分上；熱退火該介電材料的該第一部分和該第二部分，以於該基板上形成一經退火的介電材料，其中該經退火的介電材料位於該主動區與該淺溝槽隔離上且從該閘極結構橫向地設置；以及在該閘極結構與該經退火的介電材料上提供第二介電材料，其中該經退火的介電材料與該第二介電材料的一接面的高度與該閘極間隔物的一頂表面的高度齊平。
  2. 如申請專利範圍第1項所述之方法，其中提供該紫外線能量的步驟更包括將一基板溫度控制在約50℃至約400℃。
  3. 如申請專利範圍第1項所述之方法，其中熱退火該介電材料的步驟更包括：在熱退火該介電材料的同時供給一含氧的氣體至該介電材料，其中該含氧 的氣體係選自由O2、O3、N2O、水氣(H2O)、H2O2、大氣、CO2、CO及上述之組合所組成的群組。
  4. 如申請專利範圍第3項所述之方法，其中熱退火該介電材料的步驟更包括：將該介電材料的第一部分及第二部分轉化成一含氧化矽的材料。
  5. 如申請專利範圍第1項所述之方法，其中旋轉塗布該介電材料的第一部分的步驟更包括：旋轉塗布全氫聚矽氮烷(perhydro-polysilazane)化合物至該基板上，其中來自該全氫聚矽氮烷化合物的溶劑和水分在固化該介電材料的第一部分之期間被驅出，其中形成及固化該介電材料的額外部分的步驟被重複地進行。
  6. 如申請專利範圍第1項所述之方法，更包括：於該第一部分上形成該介電材料的一額外部分；以及在形成該介電材料的第二部分之前固化該介電材料的額外部分。
  7. 如申請專利範圍第6項所述之方法，其中以一具有與形成該介電材料的第一部分相同的製程參數的製程形成該介電材料的額外部分。
  8. 一種半導體製程方法，該方法包括：在一基板上提供一主動區與一淺溝槽隔離，其中該淺溝槽隔離鄰接該主動區；在該主動區上提供一閘極結構，其中一源極/汲極區域位於該閘極結構附近的該主動區中；提供設置相鄰於該閘極結構的一閘極間隔物；旋轉塗布一包括全氫聚矽氮烷化合物的第一溶液於該基板上；對該第一溶液提供一紫外線能量以分解在該第一溶液的該全氫聚矽氮烷化合物中的Si-N與Si-H鍵以形成氮化矽，來固化該第一溶液以在該基板上形成一介 電材料的一經固化的第一部分；旋轉塗布一包括全氫聚矽氮烷化合物的第二溶液於該基板上的該介電材料經固化的第一部分上，以於該基板上形成該介電材料的一第二部分；退火該介電材料的該經固化的第一部分與該第二部分，其中退火後的該第二部分位於該主動區與該淺溝槽隔離上且從該閘極結構橫向地設置；以及在該閘極結構以及退火後的該第二部分上提供第二介電材料，其中退火後的該第二部分與該第二介電材料的一接面的高度與該閘極間隔物的一頂表面的高度齊平。
  9. 一種半導體裝置，包括：一主動區與一淺溝槽隔離，位於一基板上，其中該淺溝槽隔離鄰接該主動區；一閘極結構，位於該主動區上，其中一源極/汲極區域位於該閘極結構附近的該主動區中；一閘極間隔物，被設置相鄰於該閘極結構；一第一介電材料，位於該主動區與該淺溝槽隔離上且從該閘極結構橫向地設置；以及一第二介電材料，位於該閘極結構與該第一介電材料上，其中該淺溝槽隔離、該第一介電材料與該第二介電材料中之至少一者包括一氮含量為約0.005原子百分比至約0.5原子百分比的氧化矽材料，其中該第一介電材料與該第二介電材料的一接面的高度與該閘極間隔物的一頂表面的高度齊平。
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