CN110556340B - 半导体工艺方法与结构 - Google Patents

半导体工艺方法与结构 Download PDF

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Publication number
CN110556340B
CN110556340B CN201910181592.4A CN201910181592A CN110556340B CN 110556340 B CN110556340 B CN 110556340B CN 201910181592 A CN201910181592 A CN 201910181592A CN 110556340 B CN110556340 B CN 110556340B
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dielectric material
substrate
dielectric
annealing
cured
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CN110556340A (zh
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郭哲铭
黄彦钧
彭治棠
包天一
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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Abstract

本申请大抵上涉及半导体装置，且特别涉及形成于半导体装置中的介电材料。本申请提供以循环旋转涂布工艺形成介电材料层的方法。本申请提供半导体工艺方法与结构。在一实施例中，于基板上形成介电材料的方法包括旋转涂布介电材料的第一部分于基板上、固化在基板上的介电材料第一部分、旋转涂布介电材料的第二部分于基板上、以及热退火介电材料以于基板上形成经退火的介电材料。

Description

半导体工艺方法与结构
技术领域
本发明实施例涉及半导体装置，且特别涉及形成于半导体装置中的介电材料。
背景技术
半导体集成电路(IC)工业经历了快速地成长。集成电路材料与设计的技术上的进展造就了集成电路的世代，而每一世代相对于前一世代具有较小且更为复杂的电路。在集成电路发展的过程中，功能密度(functional density，例如：单位芯片面积的互连装置的数量)普遍地增加，而几何尺寸(geometry size，例如：使用一工艺可以形成的最小元件(或导线))则缩小。这种缩小化的过程通常会带来提高生产效率和降低相关成本的益处。然而，缩小化也带来了未出现于先前尺寸较大的世代的挑战。在制造介电材料时，对于沉积与退火工艺不准确与不适当的控制可能会不利地降低装置结构的电气性能。
发明内容
本发明的一些实施例提供一种半导体工艺方法。上述方法包括旋转涂布介电材料的第一部分于基板上、固化在基板上的介电材料的第一部分、旋转涂布介电材料的第二部分于基板上、以及热退火介电材料以于基板上形成经退火的介电材料。
本发明的一些实施例提供一种半导体工艺方法。上述方法包括旋转涂布包括全氢聚硅氮烷化合物的第一溶液于基板上、固化第一溶液以在基板上形成介电材料的经固化的第一部分、旋转涂布包括全氢聚硅氮烷化合物的第二溶液于基板上的介电材料经固化的第一部分上以于基板上形成介电材料的第二部分、以及退火介电材料经固化的第一部分与第二部分。
本发明的一些实施例提供一种结构。上述结构包括位于基板上的浅沟槽隔离(shallow trench isolation，STI)与有源区。浅沟槽隔离邻接有源区。上述结构也包括位于有源区上的栅极结构。源极/漏极区域位于栅极结构附近的有源区中。上述结构也包括第一介电材料。第一介电材料位于有源区与浅沟槽隔离上且从栅极结构横向地设置。上述结构也包括位于栅极结构与第一介电材料上的第二介电材料。浅沟槽隔离、第一介电材料与第二介电材料中的至少一者包括氮含量为约0.005原子百分比至约0.5原子百分比的氧化硅材料。
附图说明
通过以下的详细描述配合附图，可以更加理解本发明实施例的内容。需强调的是，根据产业上的标准惯例，许多特征部件(feature)并未按照比例绘制。事实上，为了能清楚地讨论，各种特征部件的尺寸可能被任意地放大或缩小。
图1为一流程图，其根据一些实施例绘示出制造半导体装置的介电材料的工艺的例子。
图2A至图2E根据一些实施例示出于例示性的制造介电材料的工艺的期间各中间结构的剖面图。
图3为一流程图，其根据一些实施例示出在不同仪器设备之间转移基板的顺序的例子。
图4A至图4D根据一些实施例示出于例示性的制造介电材料的工艺期间各中间结构的剖面图。
图5A与图5B根据一些实施例示出一半导体装置的剖面图，且其介电材料以图1所例示的工艺形成。
图6根据一些实施例绘示出介电材料的湿法蚀刻速率轨迹线(wet etching ratetrace line)，其中介电材料以图1所例示的工艺形成。
附图标记说明：
100～工艺；
102、104、106、108、112～操作步骤；
110～回圈；
201～基板；
202～介电材料的第一部分；
204～介电材料的第一固相部分；
206～介电材料的第二部分；
208～经退火的介电材料；
210～介电材料；
250～介电材料的第一部分的上表面；
252～介电材料的第一部分的下表面；
260～介电材料的额外的部分；
262～介电材料的第二固相部分；
302～涂布仪器设备；
304～固化仪器设备；
306～退火仪器设备；
308～回圈；
310～箭头；
208a～第一层间介电质；
208b～第二层间介电质；
208c～金属间介电质；
208d～浅沟槽隔离；
501～导电填充材料；
503～导电特征部件；
506～蚀刻停止层；
514～阻障层；
516～衬层；
546～鳍片结构；
553～导电填充材料；
554～栅极间隔物；
556～外延源极/漏极区；
560～接触蚀刻停止层；
570～介面介电质；
572～栅极介电层；
574～共形层；
576～导电填充材料；
590～导电特征部件；
594～粘合层；
596～阻障层；
598～硅化物区；
602～湿法蚀刻速率轨迹线。
具体实施方式
以下内容提供了很多不同的实施例或范例，用于实施本发明实施例的不同特征部件。组件和配置的具体范例描述如下，以简化本发明实施例。当然，这些仅仅是范例，并非用以限定本发明实施例。举例来说，本说明书的描述中若提及第一特征部件形成于第二特征部件之上(over或on)，可能包含第一和第二特征部件直接接触的实施例，也可能包含额外的特征部件形成于第一和第二特征部件之间，而使得第一和第二特征部件不直接接触的实施例。另外，本发明实施例可能在许多范例中重复元件符号及/或字母。这些重复是为了简化和清楚的目的，其本身并非代表所讨论各种实施例及/或配置之间有特定的关系。
此外，此处可能使用空间上的相关用语，例如“在…之下”、“在…下方”、“下方的”、“在…上方”、“上方的”和其他类似的用语可用于本说明书中，以便描述如图所示的一元件或特征部件与其他元件或特征部件之间的关系。这种空间上的相关用语除了包含图示的方位外，也包含使用或操作中的装置的不同方位。装置可以被转至其他方位(旋转90度或其他方位)，则在此所使用的空间相对描述可同样依旋转后的方位来解读。
本发明实施例大抵上关于半导体装置，且特别关于形成于半导体装置中的介电材料。本发明实施例提供以旋转涂布工艺(spin-on coating process)形成介电材料的方法。以循环涂布工艺(cyclic coating process)形成介电材料。以各涂布工艺形成介电材料的一部分。于各涂布工艺之后进行固化工艺(curing process)以固化介电材料。固化工艺有助于将水分/溶剂(moisture/solvent)自介电材料驱出。在循环涂布与固化工艺之后，进行退火工艺以密化(densifying)介电材料的薄膜结构并氧化介电材料。
于此所描述的例示性的实施例于在前段工艺(Front End Of the Line(FEOL))中形成介电材料的脉络下进行描述。本发明实施例一些层面的实施可被用于其他工艺。举例而言，可于后段工艺(Back End Of the Line(BEOL)processing)中及/或中段工艺(MiddleEnd Of the Line(MEOL)processing)中形成导电特征部件。例示性的方法与结构的一些变化被描述。所属领域普通技术人员可轻易地理解其他可能的修饰改变于其他实施例的范围中被考虑到。虽然可以特定的顺序描述方法实施例，各种其他方法实施例可以任何合理的顺序进行且可包括较少或较多的步骤。在一些附图中，一些被示出的元件或特征部件的标号可能被省略，以避免造成其他元件或特征部件不清楚的情形，这是为了便于描绘这些附图。
图1为一流程图，其根据一些实施例例示性地示出制造半导体装置的介电材料的工艺100。图2A至图2E为根据图1的流程图示出于各制造阶段的介电材料的剖面图。所属领域中普通技术人员应理解，于图示或于此的叙述中并未描绘于半导体装置中形成介电材料的全部的工艺以及相关的结构，尽管图5A与图5B中示出一例示性的结构。
流程图以于操作步骤102提供基板201至涂布仪器设备作为开始(如图2A所示)，将以图1的工艺100于基板201上形成介电材料。基板201为半导体基板，且为或包括块状(bulk)半导体基板(例如：晶圆)、绝缘层上半导体(semiconductor-on-insulator(SOI))基板或其他基板。基板201的半导体材料可包括或可为选自硅(例如：结晶硅，如Si<100>或Si<111>)、硅锗、锗、砷化镓、或其他半导体材料中的至少一者的材料。半导体材料可被p型或n型杂质所掺杂或未被掺杂。在一些实施例中，绝缘层上半导体结构被用于基板201，基板201可包括设置于绝缘层上的半导体材料，上述绝缘层可为设置于半导体基板中的埋藏绝缘体，或者为玻璃或蓝宝石(sapphire)基板。在此所述的实施例中，基板201为含硅的材料，例如：结晶硅基板。此外，基板201不限定为任何特定的尺寸、形状或材料。基板201可为圆形(round/circular)基板，其直径可为200mm、300mm、或其他大小(例如：450mm等)。视需求，基板201也可为任何多边形、正方形、矩形、曲形、或其他非圆形的工作件，例如：多边形基板。
基板201可包括或不包括形成于其上的结构。在一些实施例中，基板201可包括于集成电路的制造的各步骤中事先形成于基板201上的多层结构。举例而言，上述结构可包括于前段工艺中所形成的结构，例如包括浅沟槽隔离结构、栅极结构、接触结构及/或其他适当的结构。举例而言，基板201可包括场效应晶体管(Field Effect Transistors(FETs))，例如：鳍式场效应晶体管(FinFETs)、平面场效应晶体管、垂直式环绕式栅极晶体管(vertical gate all around FETs(VGAA FETs))、或类似的场效应晶体管)、二极管、电容器、电感器及其他装置的部分。在一些例子中，上述结构可还包括于后段工艺中所形成的结构的部分，其中各个装置或元件以例如金属线、导孔(vias)及/或形成于介电材料中的导电填充材料互连。应注意的是，在形成一材料层于基板201之上之前，可于基板201之上形成额外的结构、其他材料层、或装置结构。各种装置可在基板201之上。
于操作步骤104，进行第一涂布工艺，以于基板201上形成介电材料210的第一部分202(如图2B所示)。如图3所示，基板201可被移置至涂布仪器设备302以进行涂布工艺。涂布工艺可为旋转涂布工艺、喷墨工艺(inkjet process)、急骤蒸发器(flash evaporator)工艺、喷涂披覆(spray coating)、喷涂涂布(aerosol coating)或类似的工艺。在一些例子中，将含硅的液体前体引导至基板201的表面以进行第一涂布工艺。使用旋转涂布工艺将含硅的液体前体涂布至基板201上。进行旋转涂布工艺，以于基板201的表面上全域地形成介电材料210的第一部分202，其可包括填充可能形成于基板201中的沟槽(trenches)、凹陷(recesses)、孔(apertures)、空隙(voids)、间隙(gaps)、表面裂痕(surfacediscontinuities)及/或段差(steps)。在一些例子中，含硅的液体前体包括全氢聚硅氮烷(perhydro-polysilazane(PHPS))。全氢聚硅氮烷化合物具有—(SiH2NH)n—的化学式，n为正整数。全氢聚硅氮烷化合物包含Si—N键作为重复单元且为由Si、N以及H所组成的含硅高分子。全氢聚硅氮烷化合物具有分子中的线性结构、链结构、交联结构或环状结构。
在一些例子中，全氢聚硅氮烷化合物包括在所需要范围内的分子量。举例而言，全氢聚硅氮烷化合物的平均分子量可大于约300g/mol，例如：为约5000g/mol至约8000g/mol。分子量在上述范围的全氢聚硅氮烷化合物于在基板上形成介电层时提供足够的Si比率，以于后续的退火工艺之后提供较佳的薄膜品质。
通常以溶液的形式提供全氢聚硅氮烷化合物，其中上述溶液包括约5至约50重量百分比的全氢聚硅氮烷、以及约30至约95重量百分比的溶剂。适当的溶剂包括二甲苯(xylene)、二丁醚(dibutyl ether)、三酚(trihydroxy benzene)、乙二醇(ethyleneglycol)、甲苯(toluene)、啶(pyridine)、己烷(hexane)、或类似的溶剂。
由于全氢聚硅氮烷化合物包括由Si、N及H所组成的含硅高分子，形成于基板201上的介电材料210的第一部分202为含有硅与氮的材料，且于后续将在操作步骤112的热处理工艺中经由氧化被转化成含有硅与氧的材料。
在一些实施例中，可将全氢聚硅氮烷化合物涂布至基板201之上以形成介电材料210的第一部分202，其厚度为约50nm至约250nm，例如：为约70nm至约150nm(例如：为约100nm)。
于约5℃至约80℃(例如：为约10℃至约30℃(例如：约为室温或为约25℃))的温度下进行涂布工艺。
于操作步骤106，在将介电材料210的第一部分202涂布至基板201上之后，固化介电材料210的第一部分202。将基板201与其上的第一部分202从涂布仪器设备302转置至固化仪器设备304(如图3所示)，以进行固化工艺。固化工艺将水分/溶剂从介电材料210的第一部分202移除，以形成介电材料210的第一固相部分204(如图2C所示)。由于介电材料210的第一部分202被固化，介电材料210的第一部分202中的水分与溶剂被驱出，而形成了介电材料210的第一固相部分204。在一些实施例中，固化仪器设备304(于其中可进行操作步骤104的固化工艺)包括加热板、烘箱、受热腔体或适当的仪器。紫外光光源可提供辐射线，以产生热能而使介电材料210的第一部分202的水气或溶剂汽化(evaporate)、分解(decompose)或“被烧除(burn out)”。由紫外光辐射线所提供的热能提供了用以将介电材料210的第一部分202分解的热能，因而形成了可被轻易地从固化仪器设备304泵出(pumpedout)及移除的挥发性气相副产物。
在一些实施例中，固化工艺为紫外线热固化工艺，且将基板暴露至紫外线热能(可使用或不使用固化气体)以进行固化工艺。在一些实施例中，于紫外线热固化工艺中使用固化气体，固化气体的形式可为气体或是汽化液体蒸汽(vaporized liquid vapor)，其可有助于将介电材料210的第一部分202的水分及/或溶剂反应并移除。在固化仪器设备304中开启紫外光光源单元(例如：固化仪器设备304中的紫外光灯)的情况下进行紫外线热固化工艺而有助于解离(dissociation)及分解(decomposition)化学键，以从介电材料210的第一部分202移除水分及/或溶剂。当使用固化气体时，可在使固化气体流入固化仪器设备304的同时、之前或之后开启紫外光光源单元。
由紫外光辐射线所提供的紫外线热能可有效率地将介电材料210的第一部分202的水分及/或溶剂汽化成气体或气相，而可轻易地使其从基板表面被移除并从固化仪器设备304被泵出。由于在第一部分202中的溶剂通常具有相对较低的汽化点(例如：低于150℃)，因此经由使用来自于紫外光辐射线的紫外线热能可将溶剂汽化并促进介电材料210的第一部分202中的全氢聚硅氮烷化合物的持续分解。在一些实施例中，可选择来自于紫外光光源的辐射线的波长来放射(activate)特定的能量模式(energy modes)，以促进第一部分202中的全氢聚硅氮烷化合物的分解并将水分与溶剂驱出。此外，紫外光功率水平(powerlevel)也被控制在相对较低的范围，以确保由紫外光所提供的热能均匀地传递通过介电材料210的第一部分202的整体厚度(bulk thickness)。据信，慢的热固化工艺有助于使高分子全氢聚硅氮烷化合物的分解工艺相对较为全面。因此，横跨第一部分202的Si-N与Si-H键被分解以形成第一部分202的含有氮化硅的材料，其横跨第一部分202具有相对较强的键结。第一部分202的均匀的接合结构有助于在后续所进行的氧化工艺中使氧接合至结构中。因此，介电材料210的含有氮化硅的材料可横跨介电材料210的块状结构被有效率且均匀地转化成含有硅与氧的材料。
在一些例子中，紫外光的波长为约100nm至约300nm。紫外光可为广谱(broadspectrum)紫外光，或可具有单一波长。紫外线热固化工艺的处理时间可为约15秒至约900秒，例如：为约60秒。在热固化工艺的期间，基板温度被加热至为约20℃至约400℃，例如：为约200℃至约350℃(例如：为约300℃)。于固化工艺中经由控制其上设置有基板的基板支撑台的温度装置加热至基板温度。紫外光功率可为约500mJ/cm2至约6000mJ/cm2，例如：为约2500mJ/cm2。于工艺中，腔体压力可为约5milliTorr至约200Torr，例如：为约80Torr。在一些特定的实施例中，紫外光光源提供波长约为200nm的辐射线，以自基板201上的介电材料210的第一部分202移除水分/溶剂。将紫外光功率控制在约为4000mJ/cm2。
将介电材料210的第一部分202的厚度维持在所需要的范围可促进相对均匀的热固化工艺。过厚的介电材料210的第一部分202的厚度(例如：大于200nm)可能会影响热能传导(propagation)或传递(transmission)横跨第一部分202。因此，第一部分202的上表面250与下表面252之间可能会出现热梯度而造成不均匀的薄膜性质与接合结构，这最终可能导致装置性能不良。不均匀的薄膜性质通常会造成薄膜品质控制不良以及横跨介电材料210的不相等的湿法蚀刻速率，这可能造成不期望的装置性能控制不良。因此，将介电材料210的第一部分202的厚度控制为小于200nm，例如：为约100nm至约150nm。因此，来自热固化工艺的热能可被慢慢地且均匀地传递横跨介电材料210的第一部分202，借此将溶剂与水分驱出，形成第一固相部分204。
于操作步骤108，进行第二涂布工艺，以于基板201上形成介电材料210的第二部分206(如图2D所示)。在此操作步骤中，如图3与回圈308所示，可将基板201传递回到涂布仪器设备302以进行涂布工艺。在操作步骤108的涂布工艺类似于在操作步骤104的涂布工艺。因此，涂布工艺也为旋转涂布工艺。在一些例子中，将含硅的液体前体引导至基板201的表面以进行第二涂布工艺。如前所述，含硅的液体前体包括全氢聚硅氮烷(PHPS)。全氢聚硅氮烷化合物的化学式为—(SiH2NH)n—，其中n为正整数。全氢聚硅氮烷化合物含有作为重复单元的Si—N键且为由Si、N与H所组成的含硅高分子。全氢聚硅氮烷化合物具有分子中的线性结构、链结构、交联结构或环状结构。
在一些例子中，全氢聚硅氮烷化合物包括在所需要范围内的分子量。举例而言，全氢聚硅氮烷化合物的平均分子量可大于约300g/mol，例如：为约5000g/mol至约8000g/mol。
通常以溶液的形式提供全氢聚硅氮烷化合物，其中上述溶液包括约5至约50重量百分比的全氢聚硅氮烷、以及约30至约95重量百分比的溶剂。适当的溶剂包括二甲苯、二丁醚、三酚、乙二醇、甲苯、啶、己烷、或类似的溶剂。由于全氢聚硅氮烷化合物包括由Si、N及H所组成的含硅高分子，形成于基板201上的介电材料210的第二部分206为含有硅与氮的材料，且于后续将经由热退火工艺被转化成含有硅与氧的材料。
在一些实施例中，可将全氢聚硅氮烷化合物涂布至基板201上以形成介电材料210的第二部分206，其厚度为约50nm至约250nm，例如：为约70nm至约150nm，例如：为约100nm。
于操作步骤112，于在基板201之上形成介电材料210的第二部分206之后，进行热退火工艺以将包括第一固相部分204与第二部分206的介电材料210转变成经退火的介电材料208(如图2E所示)。由热退火工艺所提供的热能可密化并强化介电材料210的接合结构。由于操作步骤112的热退火工艺于旋转涂布第二部分206之后进行，第二部分206为直接暴露于由操作步骤112的热退火工艺所提供的热能，因此在操作步骤106被用来固化第一部分202的固化工艺可被省略。
在热退火工艺中，供给退火气体，其包括至少一含氧的气体。来自于含氧气体的氧与来自于聚硅氮烷化合物的硅原子反应，而将含有氮化硅的膜层转化成氧化硅。由热退火工艺所提供的热能将Si-N键打断，使得氧原子接合并附着至硅原子，而使所形成的经退火的介电材料208为氧化硅。因此，热退火工艺期间的温度通常被预先决定，以经由热退火工艺提供足以将来自全氢聚硅氮烷的Si-N键转化成Si-O键的热能，借此形成所需要的氧化硅材料。
在一些实施例中，如图3所示，可于退火仪器设备306中进行热退火工艺。于在涂布仪器设备302中形成介电材料210的第二部分206之后，如箭头310所示，可将基板201转置至用于热退火工艺的退火仪器设备306。于退火期间，供给退火气体。可被供给于退火气体混合物中的气体可包括含氧气体，例如：O2、O3、N2O、水气(steam，H2O)、H2O2、大气(air)、CO2、CO、类似的气体或上述的组合。在一些例子中，退火气体混合物可包括水气、大气或O2。在工艺中，工艺温度可大于约350℃，例如：为约400℃至约1200℃，例如：为约600℃。
在一些实施例中，热退火工艺的时间可为约10分钟至约600分钟，例如：为约60分钟至约180分钟，例如：为约120分钟。腔体的压力可为约0.1Torr至约100Torr，例如：为约0.1至约50Torr，例如：为约0.5Torr。
于操作步骤112所进行的热退火工艺可有助于将介电材料210转化成氧化硅材料并且密化经退火的介电材料208的薄膜结构。因此，可在所形成的经退火的介电材料208中形成强度较高的接合结构以及硅氧键。此外，热退火工艺也可有助于打断Si-N键并且自经退火的介电材料208将悬键(dangling bonds)或弱硅-氢键驱出。这可提供密化的薄膜结构且可增进薄膜品质。此外，由于热退火工艺中的热膨胀，相较于未热处理的介电材料210，经退火的介电材料208的厚度可增加约百分之十至约百分之三十的数量。
承前述，来自介电材料210的第一部分202的溶剂及/或水分已预先被驱出，于热退火工艺中来自退火气体的氧元素可有效率地向下穿过介电材料210的整体厚度(例如：向下至介电材料210的第一部分202)，借此使介电材料210的第一固相部分204与第二部分206两者中的含有氮化硅的材料转化成氧化硅材料。
在一些实施例中，经退火的介电材料208的厚度可为约300至约450nm。如前所述，将介电材料210的每一次涂布(例如：第一部分202与第二部分206)控制在约为50nm至约为250nm的厚度。借此，在一些例子中，可发生于热退火工艺中的氧化转化工艺。相反地，当所需要的经退火的介电材料208为具有较大厚度(例如：大于两次涂布(例如：于操作步骤104的第一部分202的第一涂布与于操作步骤108的第二部分206的第二涂布)所能提供的厚度)时，可重复地进行操作步骤104、106(如回圈110与图1所示)，以在操作步骤112的热退火工艺之前涂布多过于两个部分的介电材料210。
举例而言，当所需要的经退火的介电材料208的厚度为大于约400nm时，在将介电材料210的第一部分202固化而形成第一固相部分204之后，进行类似于操作步骤104的额外的涂布工艺。上述的额外的涂布工艺于第一固相部分204之上涂布介电材料210的额外的部分260(如图4A所示)。介电材料210的额外的部分260类似于第一部分202，具有经由涂布全氢聚硅氮烷化合物而形成的含硅与氮的材料。类似地，在操作步骤104的涂布工艺之后，再次进行操作步骤106的固化工艺以固化额外的部分260，将额外的部分260转化成第二固相部分262(如图4C所示)。
应注意的是，可根据需求进行多次的操作步骤104与106的循环以形成介电材料210的多个部分，直到形成介电材料210的最后部分(例如：第二部分206)。重复操作步骤104与106之间的涂布与固化工艺对于使用相应的固化工艺形成介电材料210的小部分是有帮助的，借此于操作步骤112的热退火工艺之前提供具有极少溶剂与水分残留于介电材料210中的薄膜结构。因此，当进行操作步骤112的热退火工艺时，所提供的热能可顺利地传递与传导至介电材料210的整体，借此，经由将含氮化硅的材料有利地转化成含氧化硅的材料而形成经退火的介电材料208并残留极少或未残留氮含量。应注意的是，在一些例子中，于经退火的介电材料208中可残留有极少的氮含量。在此些例子中，氮含量可小于约5原子百分比(atomic percent)，例如：为约0.005至约5原子百分比，且可于操作步骤112的热退火工艺之后于经退火的介电材料208中检测氮含量。
图5A为例示性地示出半导体装置的剖面图，其中可使用由图1的工艺所形成的经退火的介电材料208。在图5A所示的例子中，经退火的介电材料208(表示为208a、208b、208c)可被用来作为第一层间介电质(interlayer dielectric(ILD))208a、第二层间介电质208b与金属间介电质(intermetal dielectric(IMD))208c的任一者。
基板201包括形成于基板201的上部之上的鳍片结构546。外延源极/漏极区556形成于鳍片结构546中。栅极结构形成于鳍片结构546之上。任一栅极结构包括介面介电质(interfacial dielectric)570、栅极介电层572、一或多个可选的共形(conformal)层574、以及栅极导电填充材料576。栅极间隔物554沿着栅极结构的侧壁形成。介面介电质570为沿着各栅极间隔物554之间的鳍片结构546的表面。栅极介电层572共形地位于介面介电质570上且沿着各栅极间隔物554的侧壁并位于各栅极间隔物554的侧壁之间。一或多个可选的共形层574共形地位于栅极介电层572上且可包括一或多个阻障层及/或盖层以及一或多个功函数调整层。栅极导电填充材料576在一或多个可选的共形层574之上。接触蚀刻停止层(contact etch stop layer(CESL))560共形地位于外延源极/漏极区556的表面以及栅极间隔物554的侧壁。
第一层间介电质208a在接触蚀刻停止层560之上。可经由图1以及图2A-图2E中或图4A-图4D中示出的工艺100形成第一层间介电质208a，接触蚀刻停止层560与栅极间隔物554则形成于其中。在一些例子中，在形成第一层间介电质208a时，虚设栅极结构设置在栅极间隔物554之间，而在形成第一层间介电质208a之后(例如：经由图1中所示的工艺100)，以图5A中所示的栅极结构取代虚设栅极结构。接着，于栅极结构与第一层间介电质208a之上形成第二层间介电质208b。可经由图1以及图2A-图2E中或图4A-图4D中示出的工艺100形成第二层间介电质208b。所形成的导电特征部件503、590穿过第一层间介电质208a及/或第二层间介电质208b以各自电性连接栅极结构与外延源极/漏极区556。举例而言，在所绘示的例子中，导电特征部件590包括粘合层594、粘合层594上的阻障层596、外延源极/漏极区556上的硅化物区598、以及阻障层596上的导电填充材料501。举例而言，在所绘示的例子中，导电特征部件503包括粘合层594、粘合层594上的阻障层596、以及阻障层596上的导电填充材料501。
蚀刻停止层506形成于第二层间介电质208b以及导电特征部件590、503之上。金属间介电质208c形成于蚀刻停止层506之上。可经由图1以及图2A-图2E中或图4A-图4D中示出的工艺100形成金属间介电质208c。所形成的导电特征部件(包括阻障层514、阻障层514上的衬层516、以及衬层516上的导电填充材料553)穿过金属间介电质208c与蚀刻停止层506并且电性连接至导电特征部件590、503。
在一些例子中，经由图1中所示工艺100形成的经退火的介电材料208(于图5A中表示为208a、208b、208c)被用以形成第一层间介电质208a、第二层间介电质208b与金属间介电质208c。由于在操作步骤104所使用的全氢聚硅氮烷化合物为基于液体/溶液的化合物，全氢聚硅氮烷化合物可填充基板201上的沟槽、凹陷、孔、空隙、间隙、表面裂痕及/或段差。
此外，图5B为图5A的半导体装置的另一个剖面图，其具有形成于基板201之上的浅沟槽隔离208d。图5B的剖面图平行于图5A的剖面图且位于形成在基板201之上的邻近的鳍片结构546之间。可以前文以图1以及图2A-图2E或图4A-图4D示出的经退火的介电材料208来形成浅沟槽隔离208d。由于浅沟槽隔离208d在沟槽中，可以所需要的间隙填充能力将包括全氢聚硅氮烷化合物的基于液体/溶液的化合物填充于基板201上的鳍片结构546之间的沟槽，以形成具有所需要的轮廓及薄膜性质的浅沟槽隔离208d。图5B示出一剖面的外延源极/漏极区556，其中外延源极/漏极区556可合并于邻近的鳍片结构546之间。在其他例子中，外延源极/漏极区556可能不会出现在类似的剖面中，这是因为外延源极/漏极区556未合并于邻近的鳍片结构546之间。
图6示出经退火的介电材料208的湿法蚀刻速率轨迹线602。湿法蚀刻速率轨迹线602被示为从经退火的介电材料208蚀刻掉的厚度(例如：蚀刻深度)的函数。由湿法蚀刻速率轨迹线602可以看出经退火的介电材料208的薄膜性质大抵上类似且均匀，因此，在湿法蚀刻工艺之下，经退火的介电材料208被以相对均匀且/或稳定的蚀刻速率蚀刻，其中蚀刻速率偏差(deviation)ΔR小于
Figure BDA0001991397470000141
本发明实施例的实施提供以多个旋转涂布工艺(例如：循环的旋转涂布工艺)及后续的热退火工艺形成介电材料的方法。在至少一旋转涂布工艺与紫外线热固化工艺之后，进行第二旋转涂布工艺与随后的热退火工艺。经由在进行热退火工艺形成介电材料之前实施多个旋转涂布工艺，旋转涂布层的溶剂与水分可被有效率地驱出，而可达成于后续热退火工艺的完全氧化工艺。因此，可得到具有氧化硅材料且氮含量小于5原子百分比的经退火的介电材料。
在一实施例中，半导体工艺方法包括旋转涂布介电材料的第一部分于基板上、固化基板上的介电材料的第一部分、旋转涂布介电材料的第二部分于基板上、以及热退火介电材料以于基板上形成经退火的介电材料。
在另一实施例中，半导体工艺方法包括旋转涂布包括全氢聚硅氮烷化合物的第一溶液于基板上、固化第一溶液以于基板上形成介电材料的经固化的第一部分、旋转涂布包括全氢聚硅氮烷化合物的第二溶液于基板上的介电材料的经固化的第一部分之上以于基板上形成介电材料的第二部分、以及退火介电材料的经固化的第一部分与第二部分。
在又一实施例中，结构包括位于基板上的浅沟槽隔离与有源区、位于有源区上的栅极结构、位于有源区与浅沟槽隔离上且从栅极结构横向地设置的第一介电材料、以及位于栅极结构与第一介电材料上的第二介电材料。浅沟槽隔离邻接(abut)有源区。源极/漏极区位于栅极结构附近的有源区中。第一介电材料、第二介电材料与浅沟槽隔离中的至少一者包括氮含量为约0.005原子百分比至约0.5原子百分比的氧化硅材料。
在再一实施例中，本发明的半导体工艺方法中的热退火介电材料的步骤还可包括：将一基板温度控制在约400℃至约1200℃，其中含氧的气体可选自由O2、O3、N2O、水气(H2O)、H2O2、大气、CO2、CO及上述的组合所组成的群组，其中经退火的介电材料可具有一小于5原子百分比(atomic percent)的氮含量，其中来自全氢聚硅氮烷化合物的溶剂和水分可在固化该介电材料的第一部分的期间被驱出，其中介电材料的第一部分可具有一为约50nm至约250nm的厚度，其中经退火的介电材料可为形成于该基板上的一半导体装置中的一层间介电质(ILD)、金属间介电质(IMD)、或浅沟槽隔离(STI)。
在进一步的实施例中，本发明的半导体工艺方法中的固化第一溶液的步骤还可包括：提供一紫外线热能至该第一溶液；退火介电材料经固化的第一部分与第二部分的步骤还可包括：供给一含氧的气体至该基板；退火介电材料经固化的第一部分与第二部分的步骤还可包括：将一退火温度控制在约400℃至约1200℃，以及将该介电材料的第一部分与第二部分转化成一含氧化硅的材料。
以上概述数个实施例的特征部件，以使本发明所属技术领域中普通技术人员可以更加理解本发明实施例的观点。本发明所属技术领域中普通技术人员应理解，他们能轻易地以本发明实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中普通技术人员也应理解，此类等效的结构并无悖离本发明实施例的精神与范围，且他们能在不违背本发明实施例的精神和范围下，做各式各样的改变、取代和替换。因此，本发明实施例的保护范围应以随附的权利要求范围所界定为准。

Claims (18)

1.一种半导体工艺方法，该方法包括：
旋转涂布一介电材料的一第一部分于一基板上；
对该介电材料的该第一部分提供一紫外线能量以分解在该介电材料的该第一部分中的Si-N与Si-H键以形成氮化硅，来固化在该基板上的该介电材料的第一部分；
旋转涂布该介电材料的一第二部分于该基板上的该介电材料经固化的第一部分上；以及
热退火该介电材料以于该基板上形成氧化硅材料，其中热退火步骤将该介电材料的该第一部分中的该氮化硅中的Si-N键打断以将该介电材料的该第一部分中的该氮化硅转化成该氧化硅材料。
2.如权利要求1所述的方法，其中提供该紫外线能量的步骤还包括：
将一基板温度控制在50℃至400℃。
3.如权利要求1所述的方法，其中热退火该介电材料的步骤还包括：
在热退火该介电材料的同时供给一含氧的气体至该介电材料。
4.如权利要求3所述的方法，其中热退火该介电材料的步骤还包括：
将一基板温度控制在400℃至1200℃。
5.如权利要求3所述的方法，其中该含氧的气体选自由O2、O3、N2O、水气、H2O2、大气、CO2、CO及上述的组合所组成的群组。
6.如权利要求1所述的方法，其中该氧化硅材料具有一小于5原子百分比的氮含量。
7.如权利要求1所述的方法，其中旋转涂布该介电材料的第一部分的步骤还包括：
旋转涂布全氢聚硅氮烷化合物至该基板上。
8.如权利要求7所述的方法，其中来自该全氢聚硅氮烷化合物的溶剂和水分在固化该介电材料的第一部分的期间被驱出。
9.如权利要求1所述的方法，还包括：
于该第一部分上形成该介电材料的一额外部分；以及
在形成该介电材料的第二部分之前固化该介电材料的额外部分。
10.如权利要求9所述的方法，其中以一具有与形成该介电材料的第一部分相同的工艺参数的工艺形成该介电材料的额外部分。
11.如权利要求9所述的方法，其中形成及固化该介电材料的额外部分的步骤被重复地进行。
12.如权利要求1所述的方法，其中该介电材料的第一部分具有一为50nm至250nm的厚度。
13.如权利要求1所述的方法，其中该氧化硅材料为形成于该基板上的一半导体装置中的一层间介电质、金属间介电质、或浅沟槽隔离。
14.一种半导体工艺方法，该方法包括：
旋转涂布一包括全氢聚硅氮烷化合物的第一溶液于一基板上；
对该第一溶液提供一紫外线能量以分解在该第一溶液的该全氢聚硅氮烷化合物中的Si-N与Si-H键以形成氮化硅，来固化该第一溶液以在该基板上形成一介电材料的一经固化的第一部分；
旋转涂布一包括全氢聚硅氮烷化合物的第二溶液于该基板上的该介电材料经固化的第一部分上，以于该基板上形成该介电材料的一第二部分；以及
退火该介电材料经固化的第一部分与第二部分以形成一氧化硅材料，其中退火步骤将该介电材料经固化的第一部分中的该氮化硅中的Si-N键打断以将该介电材料经固化的第一部分中的该氮化硅转化成该氧化硅材料。
15.如权利要求14所述的方法，其中固化该第一溶液的步骤还包括：
提供一紫外线热能至该第一溶液。
16.如权利要求14所述的方法，其中退火该介电材料经固化的第一部分与第二部分的步骤还包括：
供给一含氧的气体至该基板。
17.如权利要求14所述的方法，其中退火该介电材料经固化的第一部分与第二部分的步骤还包括：
将一退火温度控制在400℃至1200℃。
18.一种半导体结构，包括：
一有源区与一浅沟槽隔离，位于一基板上，其中该浅沟槽隔离邻接该有源区；
一栅极结构，位于该有源区上，其中一源极/漏极区域位于该栅极结构附近的该有源区中；
一栅极间隔物，被设置相邻于该栅极结构；
一第一介电材料，位于该有源区与该浅沟槽隔离上且从该栅极结构横向地设置；
一第二介电材料，位于该栅极结构与该第一介电材料上，其中该浅沟槽隔离、该第一介电材料与该第二介电材料中的至少一者包括一氮含量为0.005原子百分比至0.5原子百分比的氧化硅材料，其中该第一介电材料与该第二介电材料的一接面的高度与该栅极间隔物的一顶表面的高度齐平；以及
一第三介电材料，位于该第二介电材料上方，其中该第三介电材料包括一氮含量为0.005原子百分比至0.5原子百分比的氧化硅材料。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6849083B2 (ja) 2017-09-11 2021-03-24 東京エレクトロン株式会社 絶縁膜の成膜方法、基板処理装置及び基板処理システム
US11164954B2 (en) * 2019-06-10 2021-11-02 Globalfoundries U.S. Inc. Gate capping layers of semiconductor devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1757105A (zh) * 2003-03-05 2006-04-05 Az电子材料（日本）株式会社 形成沟槽隔离结构的方法
CN101635270A (zh) * 2008-07-25 2010-01-27 台湾积体电路制造股份有限公司 集成电路结构的制造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6448655B1 (en) * 1998-04-28 2002-09-10 International Business Machines Corporation Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation
US6756085B2 (en) * 2001-09-14 2004-06-29 Axcelis Technologies, Inc. Ultraviolet curing processes for advanced low-k materials
US6727184B1 (en) * 2002-10-29 2004-04-27 Taiwan Semiconductor Manufacturing Co., Ltd Method for coating a thick spin-on-glass layer on a semiconductor structure
US7081673B2 (en) * 2003-04-17 2006-07-25 International Business Machines Corporation Multilayered cap barrier in microelectronic interconnect structures
US7557035B1 (en) 2004-04-06 2009-07-07 Advanced Micro Devices, Inc. Method of forming semiconductor devices by microwave curing of low-k dielectric films
US20050272220A1 (en) * 2004-06-07 2005-12-08 Carlo Waldfried Ultraviolet curing process for spin-on dielectric materials used in pre-metal and/or shallow trench isolation applications
JP2006054353A (ja) * 2004-08-13 2006-02-23 Az Electronic Materials Kk フラットバンドシフトの少ないシリカ質膜およびその製造法
US9659769B1 (en) * 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
US7790633B1 (en) * 2004-10-26 2010-09-07 Novellus Systems, Inc. Sequential deposition/anneal film densification method
JP4607613B2 (ja) * 2005-02-09 2011-01-05 株式会社東芝 半導体装置の製造方法
JP5231028B2 (ja) * 2008-01-21 2013-07-10 東京エレクトロン株式会社 塗布液供給装置
JP5306669B2 (ja) 2008-02-29 2013-10-02 ＡｚエレクトロニックマテリアルズＩｐ株式会社 シリカ質膜の形成方法およびそれにより形成されたシリカ質膜
JP4886021B2 (ja) * 2008-12-16 2012-02-29 エルピーダメモリ株式会社 半導体装置及びその製造方法
US8449942B2 (en) * 2009-11-12 2013-05-28 Applied Materials, Inc. Methods of curing non-carbon flowable CVD films
US8541053B2 (en) * 2010-07-08 2013-09-24 Molecular Imprints, Inc. Enhanced densification of silicon oxide layers
JP5405437B2 (ja) * 2010-11-05 2014-02-05 ＡｚエレクトロニックマテリアルズＩｐ株式会社 アイソレーション構造の形成方法
US20140004358A1 (en) * 2012-06-28 2014-01-02 James M. Blackwell Low k carbosilane films
US20150357232A1 (en) * 2013-01-22 2015-12-10 Ps4 Luxco S.A.R.L. Method for manufacturing semiconductor device
JP6274213B2 (ja) * 2013-08-07 2018-02-07 コニカミノルタ株式会社 ガスバリア性フィルム
US9799567B2 (en) 2014-10-23 2017-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming source/drain contact
US9634141B1 (en) * 2015-10-14 2017-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Interlayer dielectric film in semiconductor devices
US9837267B2 (en) * 2016-04-29 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Optical filtering for integrated dielectrics UV curing processes
US20180145131A1 (en) * 2016-11-18 2018-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US10647578B2 (en) * 2016-12-11 2020-05-12 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude N—H free and SI-rich per-hydridopolysilzane compositions, their synthesis, and applications
US10204905B2 (en) * 2017-04-25 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
TWI793262B (zh) * 2018-02-21 2023-02-21 法商液態空氣喬治斯克勞帝方法研究開發股份有限公司 全氫聚矽氮烷組成物和用於使用其形成氮化物膜之方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1757105A (zh) * 2003-03-05 2006-04-05 Az电子材料（日本）株式会社 形成沟槽隔离结构的方法
CN101635270A (zh) * 2008-07-25 2010-01-27 台湾积体电路制造股份有限公司 集成电路结构的制造方法

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