TWI733412B - 具有氣隙之半導體元件及其製造方法 - Google Patents

具有氣隙之半導體元件及其製造方法 Download PDF

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TWI733412B
TWI733412B TW109112335A TW109112335A TWI733412B TW I733412 B TWI733412 B TW I733412B TW 109112335 A TW109112335 A TW 109112335A TW 109112335 A TW109112335 A TW 109112335A TW I733412 B TWI733412 B TW I733412B
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dielectric layer
layer
air gap
gate stacks
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余秉隆
邵柏竣
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華邦電子股份有限公司
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Abstract

一種具有氣隙之半導體元件，包括多個閘極堆疊、襯層以及介電堆疊。所述多個閘極堆疊，設置於基底上。所述襯層共形覆蓋所述多個閘極堆疊與所述基底。所述介電堆疊，位於所述多個閘極堆疊上的所述襯層上。在相鄰兩個閘極堆疊上的所述襯層與所述介電堆疊之間具有氣隙，所述氣隙的高度大於所述相鄰兩個閘極堆疊的高度。所述氣隙包括下部、中部與上部。下部位於所述相鄰兩個閘極堆疊之間，所述下部的側壁與底部裸露出所述襯層。所述中部的側壁裸露出所述介電堆疊。所述上部的側壁裸露出所述介電堆疊，所述上部的頂面被所述介電堆疊覆蓋。

Description

具有氣隙之半導體元件及其製造方法
本發明是有關於一種積體電路及其製造方法，且特別是有關於一種具有氣隙之半導體元件及其製造方法。
非揮發性儲存元件（non-volatile memory）由於可進行多次資料的存入、讀取、抹除等操作，且具有當電源供應中斷時，所儲存的資料不會消失、資料存取時間短、低消耗功率等優點，所以已成為個人電腦和電子設備所廣泛採用的一種記憶體。
在目前提高記憶體元件積集度的趨勢下，會依據設計規則縮小元件的尺寸。在此情況下，為了防止浮置閘極間的耦合干擾升高，進而提高閘極耦合率，會藉由在堆疊閘極堆疊之間形成氣隙來解決上述問題。然而，目前在堆疊閘極堆疊之間形成的氣隙的體積相當小，且其製程的方法無法有效控制氣隙的形狀與高度。
本發明提出一種可以不需要額外經由微影製程，可形成高度與形狀均勻且體積相當大的氣隙。
本發明實施例提出一種具有氣隙之半導體元件，包括多個閘極堆疊、襯層以及介電堆疊。所述多個閘極堆疊，設置於基底上。所述襯層共形覆蓋所述多個閘極堆疊與所述基底。所述介電堆疊，位於所述多個閘極堆疊上的所述襯層上。在相鄰兩個閘極堆疊上的所述襯層與所述介電堆疊之間具有氣隙，所述氣隙的高度大於所述相鄰兩個閘極堆疊的高度。所述氣隙包括下部、中部與上部。下部位於所述相鄰兩個閘極堆疊之間，所述下部的側壁與底部裸露出所述襯層。所述上部的側壁裸露出所述介電堆疊，所述上部的頂面被所述介電堆疊覆蓋。
本發明實施例還提出一種具有氣隙之半導體元件的製造方法，包括以下步驟。於基底上形成多個閘極堆疊；在所述多個閘極堆疊與所述基底上共形形成襯層；於所述基底上形成第一介電層，所述第一介電層覆蓋所述多個閘極堆疊上的所述襯層，並且覆蓋所述多個閘極堆疊之間的部分所述襯層；於所述第一介電層上形成第二介電層，其中在所述多個閘極堆疊之間的間隙上的所述第二介電層與所述第一介電層的厚度小於在所述多個閘極堆疊上的所述第二介電層與所述第一介電層的厚度；進行無圖案化的罩幕的蝕刻製程，以移除在所述間隙上方的所述第二介電層與所述第一介電層，並且移除所述多個閘極堆疊之間的所述第一介電層，以裸露出所述襯層；以及在所述第二介電層上形成第三介電層，以在所述多個閘極堆疊、所述第一介電層、所述第二介電層與所述第三介電層之間形成氣隙。
本發明實施例之方法，可以不需要額外經由微影製程而形成高度與形狀均勻且體積相當大的氣隙。因此，本發明是一種可以節約製程步驟，節省製造成本，且具有高可靠度的製程方法。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。
參照圖1A，本實施例提供一種半導體元件的製造方法，其步驟如下。首先，提供基底100，基底100例如是矽基底。接著，在基底100上形成多個閘極堆疊110。多個閘極堆疊110包括多個閘極堆疊110A與110B分別位於基底100的區域100A與100B上。閘極堆疊110A例如是非揮發性儲存元件的字元線，其包括依序堆疊在基底100上的穿隧介電層111、導體層112、閘間介電層113、導體層114以及金屬層（或是金屬矽化物層）115。穿隧介電層111的材料例如是氧化矽。導體層112做為浮置閘極（floating gate），其材料例如是摻雜多晶矽。閘間介電層113例如是氧化矽、氮化矽以及氧化矽（Oxide-Nitride-Oxide，ONO）複合層。導體層114做為控制閘極（control gate），其材料例如是摻雜多晶矽。金屬層（或是金屬矽化物層）115的材料可以是鎢、矽化鎳或矽化鈷。導體層114與金屬層（或是金屬矽化物層）115可以是沿著穿入紙面方向的條狀結構。閘極堆疊110B可以與閘極堆疊110A具有相似或是不同的結構。閘極堆疊110A之間的間隙G1較小，而閘極堆疊110B之間的間隙G2較大。
接著，在基底100上形成襯層120，以覆蓋多個閘極堆疊110的上表面與側壁以及穿隧介電層111的表面上。襯層120例如是共形氮化矽層或氧化矽層。
參照圖1B，在基底100上形成第一介電層122與第二介電層124。第一介電層122覆蓋多個閘極堆疊110以及間隙G2上的上的襯層120，並且覆蓋間隙G1上的部分襯層120，因此具有彎曲的上表面。第二介電層124，覆蓋第一介電層122，具有彎曲的上表面與下表面。第一介電層122的材料與襯層120不同。第二介電層124與第一介電層122的材料可以相同，但具有不同的蝕刻特性。第一介電層122與第二介電層124可以是以不同方法沉積的氧化矽，例如第一介電層122是結構較為鬆散的氧化矽，而第二介電層124是結構較為緻密的氧化矽。舉例來說，第一介電層122是以四乙氧基矽烷（TEOS）做為氣體源形成的TEOS系氧化矽；第二介電層124是甲烷做為氣體源形成的甲烷系氧化矽。在第一介電層122為TEOS系氧化物的示例中，第一介電層122可以在攝氏200 ~600度，壓力1~10torr，射頻功率50~2000瓦，以0.1~10gm的TEOS，500~15000sccm的O 2，100~15000sccm的N 2O，100~30000sccm的N 2以及100~15000sccm的He做為反應氣體以及輸送氣體，經由化學氣相沉積法形成。在第二介電層124為甲烷系氧化物的示例中，第二介電層124是在攝氏200~600度，壓力1~10torr，射頻功率50~2000瓦，以10~1000sccm的甲烷，100~15000sccm的N 2O以及100~30000sccm的N 2以及100~15000sccm的He做為反應氣體以及輸送氣體，經由化學氣相沉積法形成。
或者，第二介電層124的材料也可以與第一介電層122相異。舉例來說，第一介電層122為氧化矽，而第二介電層124可以是氮化矽或是氮氧化矽。在第一介電層122為氧化矽的示例中，第一介電層122可以是TEOS系氧化物或甲烷系氧化物。在第二介電層124為氮化矽或是氮氧化矽的示例中，第二介電層124可以在攝氏200~600度，壓力1~10torr，射頻功率100~2000瓦，以10~1000sccm的甲烷，10~500sccm的NH 3，500~30000sccm的N 2以及100~15000sccm的N 2O做為反應氣體以及輸送氣體，經由化學氣相沉積法形成。
由於多個閘極堆疊110之間具有間隙G1與G2，因此第一介電層122與第二介電層124會隨著基底100表面的輪廓而有高低起伏。而且第一介電層122與第二介電層124為非共形層。由於多個閘極堆疊110A之間的間隙G1較小，因此間隙G1的頂端會被第一介電層122的懸突封住，且第二介電層124的厚度T2g與第一介電層122的厚度T1g分別會小於在多個閘極堆疊110上的第二介電層124的厚度T2s與第一介電層122的厚度T1s。舉例來說，T1s例如是10nm至200nm；T1g例如是1nm至100nm。T1s/T1g的比例例如是200:1~1.5:1。T2s例如是10nm至200nm；T2g例如是1nm至100nm。T2s/T2g的比例例如是200:1~1.5:1。T1s/T2s的比例例如是0.1:1~20:1。T1g/T2g的比例例如是0.1:1~20:1。由於多個閘極堆疊110B之間的間隙G2大，因此第二介電層124與第一介電層122則未將間隙G2填滿。
參照圖1C，對第二介電層124進行第一蝕刻製程E1。由於在多個閘極堆疊110A之間的間隙G1上的第二介電層124的厚度T2g小於在多個閘極堆疊110A上的第二介電層124的厚度T2s，因此，在多個閘極堆疊110A之間的間隙G1上的第二介電層124的厚度T2g會先被蝕刻殆盡，而形成裸露出第一介電層122的凹槽R，而在多個閘極堆疊110A上的第一介電層122仍被第二介電層124覆蓋。藉由第二介電層124在閘極堆疊110A與間隙G1之間的厚度差異，即可直接藉由乾式蝕刻製程在間隙G1上方形成裸露出第一介電層122的凹槽R，而不需要額外經由微影製程定義凹槽R的位置。
參照圖1D，對凹槽R裸露的第一介電層124進行第二蝕刻製程E2。此蝕刻製程可以是等向性蝕刻製程，例如是濕式蝕刻製程。在此第二蝕刻製程中，第二介電層124具有較低的蝕刻速率，因此可以做為硬罩幕層。再者，在此第二蝕刻製程中，第一介電層122具有較高的蝕刻速率，且由於蝕刻的負載效應（loading effect），因此縱使凹槽R僅裸露出小面積的第一介電層122，第一介電層122也可以被快速蝕刻，而形成比凹槽Ｒ更大的氣隙AG。在進行第二蝕刻製程時，由於襯層120與第一介電層122具有足夠的蝕刻選擇比，因此，襯層120可以做為閘極堆疊110的保護層，並且確保在間隙G1之中的第一介電層122可以移除殆盡。舉例來說，第二介電層124與第一介電層122的蝕刻選擇比例如是1:1.5~1:100。
參照圖1E，在第二介電層124上形成第三介電層126，以封合氣隙AG。第三介電層126例如是氧化矽、氮化矽或氮氧化矽。第一、第二、第三介電層122、124、126可合稱為介電堆疊130。
多個氣隙AG具有大致相同的高度與形狀。氣隙AG的高度Ht大於閘極堆疊110A的高度Hs。氣隙AG可以包括下部P1、中部P2與上部P3。下部P1位於相鄰兩個閘極堆疊110之間，下部P1的側壁與底部裸露出襯層120，且襯層120完全沒有被介電堆疊130的第一介電層122覆蓋。中部P2位於下部P1之上，中部P2的側壁裸露出介電堆疊130的第一介電層122。中部P2的側壁可以是呈弧形。上部P3位於中部P2之上，上部P3的頂面被介電堆疊130的第三介電層126覆蓋，上部P3的側壁裸露出介電堆疊130的第二介電層124。上部P3的側壁可以是呈垂直或是傾斜。
氣隙AG的下部P1、中部P2以及上部P3的高度可以依據閘極堆疊110A、第一介電層122以及第二介電層124的高度與厚度來決定。中部P2以及上部P3的高度和（H2+H3）可以是小於、等於或是大於下部P1的高度H1。舉例來說，中部P2以及上部P3的高度和（H2+H3）與下部P1的高度H1的比例如是0.01:1~1:1.2。
氣隙AG的下部P1、中部P2以及上部P3的寬度可以依據閘極堆疊110A之間的間隙G1的寬度、襯層120的厚度、第一蝕刻與第二蝕刻製程的條件來控制。中部P2的寬度（最大寬度）W2可以大於上部P3的寬度W3且大於或等於下部P1的寬度W1。上部P3的寬度W3可以小於中部P2的寬度W2且小於下部P1的寬度W1。舉例來說，W2/W1的比例例如是0.01:1~2:1，W3/W1的比例例如是0.001:1~0.5:1。
參照圖1F，以化學機械研磨製程對第三介電層126進行平坦化，使第三介電層126具有彎曲輪廓的下表面以及平坦的上表面。然後，在第三介電層126上形成頂蓋硬罩幕層132。頂蓋硬罩幕層132的材料例如是氮化矽、氧化矽或氮氧化矽。其後，可以再於區域100B的頂蓋硬罩幕層132以及介電堆疊130之中形成裸露出基底100的接觸窗開口134以及第二介電層124，並於接觸窗開口134中形成導體插塞136等後續製程。
圖2A至圖2G是繪示本發明的實施例的一種具有氣隙之半導體元件的製造方法的剖面示意圖。
參照圖2A，在另一實施例中，也可以在基底100上形成襯層120之後，先形成填充材料層140。填充材料層140為非共形層，其無法填入閘極堆疊110A之間的間隙G1，但可以填滿閘極堆疊110B之間的間隙G2。
參照圖2B，以化學機械研磨製程對填充材料層140進行平坦化，以移除在區域100A中的填充材料層140，並在區域100B中的間隙G2之中形成填充層140a。
參照圖2C至圖2G，依照上述的方法進行後續的製程，直至形成導體插塞136。
在本發明實施例中，利用具有不同蝕刻速率的介電層的沉積、閘極堆疊上以及間隙上之介電層的厚度差異以及乾濕蝕刻製程的使用，即可形成高度與形狀均勻且體積相當大的氣隙，而不需要額外經由微影製程。因此，本發明是一種可以節約製程步驟，節省製造成本，且具有高可靠度的製程方法。
100:基底 100A、100B:區域 110、110A、110B:閘極堆疊 111:穿隧介電層 112:導體層 113:閘間介電層 114:導體層 115:金屬層/金屬矽化物層 120:襯層 122:第一介電層 124:第二介電層 126:第三介電層 130:介電堆疊 132:硬罩幕層 134:接觸窗開口 136:導體插塞 140:填充材料層 140a:填充層 G1、G2:間隙 AG:氣隙 P1:下部 P2:中部 P3:上部 T1g、T1s、T2g、T2s:厚度 H1、H2、H3、Hs、Ht:高度 W1、W2、W3:寬度 R:凹槽 E1:第一蝕刻製程 E2:第二蝕刻製程
圖1A至圖1F是繪示本發明的實施例的一種具有氣隙之半導體元件的製造方法的剖面示意圖。 圖2A至圖2G是繪示本發明的實施例的一種具有氣隙之半導體元件的製造方法的剖面示意圖。
100:基底
100A、100B:區域
110、110A、110B:閘極堆疊
111:穿隧介電層
112:導體層
113:閘間介電層
114:導體層
115:金屬層/金屬矽化物層
120:襯層
122:第一介電層
124:第二介電層
G1、G2:間隙
T1g、T1s、T2g、T2s:厚度

Claims (10)

  1. 一種具有氣隙之半導體元件，包括：多個閘極堆疊，設置於基底上；襯層，共形覆蓋所述多個閘極堆疊與所述基底；以及介電堆疊，位於所述多個閘極堆疊上的所述襯層上，其中在相鄰兩個閘極堆疊的所述襯層與所述介電堆疊之間具有氣隙，所述氣隙的高度大於所述相鄰兩個閘極堆疊的高度，所述氣隙包括下部，位於所述相鄰兩個閘極堆疊之間，所述下部的側壁與底部裸露出所述襯層；中部，位於所述下部之上；以及上部，位於所述中部之上，所述上部的側壁裸露出所述介電堆疊，所述上部的頂面被所述介電堆疊覆蓋，且所述上部的寬度小於所述下部的所述寬度。
  2. 如申請專利範圍第1項所述的具有氣隙之半導體元件，其中所述氣隙的所述下部的所述襯層未被所述介電堆疊覆蓋。
  3. 如申請專利範圍第1項所述的具有氣隙之半導體元件，其中所述介電堆疊包括：第一介電層，位於所述多個閘極堆疊上，且具有彎曲的上表面；第二介電層，位於所述第一介電層上，且具有彎曲的上表面與下表面；以及 第三介電層，位於所述第二介電層上，且具有彎曲輪廓的下表面以及平坦的上表面；
  4. 如申請專利範圍第3項所述的具有氣隙之半導體元件，其中所述第二介電層的材料與第一介電層的材料不同。
  5. 如申請專利範圍第1項所述的具有氣隙之半導體元件，其中所述下部的深度與所述多個閘極堆疊的高度大致相等。
  6. 如申請專利範圍第1項所述的具有氣隙之半導體元件，其中所述中部的深度大於所述上部的深度。
  7. 如申請專利範圍第1項所述的具有氣隙之半導體元件，其中所述中部的寬度大於所述下部的深度。
  8. 一種具有氣隙之半導體元件的製造方法，包括：於基底上形成多個閘極堆疊；在所述多個閘極堆疊與所述基底上共形形成襯層；於所述基底上形成第一介電層，所述第一介電層覆蓋所述多個閘極堆疊上的所述襯層，並且覆蓋所述多個閘極堆疊之間的部分所述襯層；於所述第一介電層上形成第二介電層，其中在所述多個閘極堆疊之間的間隙上的所述第二介電層與所述第一介電層的厚度小於在所述多個閘極堆疊上的所述第二介電層與所述第一介電層的厚度；進行無圖案化的罩幕的蝕刻製程，以移除在所述間隙上方的所述第二介電層與所述第一介電層，並且移除所述多個閘極堆疊 之間的所述第一介電層，以裸露出所述襯層；以及在所述第二介電層上形成第三介電層，以在所述多個閘極堆疊、所述第一介電層、所述第二介電層與所述第三介電層之間形成氣隙。
  9. 如申請專利範圍第8項所述的具有氣隙之半導體元件的製造方法，其中所述無圖案化的罩幕的蝕刻製程包括：進行乾式蝕刻製程，移除部分所述第二介電層，以在所述間隙上方形成裸露出所述第一介電層的凹槽；以及進行溼式蝕刻製程，以移除所述凹槽下方的所述第一介電層，其中所述第二介電層的蝕刻速率低於所述第一介電層的蝕刻速率。
  10. 如申請專利範圍第8項所述的具有氣隙之半導體元件的製造方法，更包括對第三介電層進行平坦化製程。
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