TW202307965A - 半導體記憶體元件及其製作方法 - Google Patents
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Abstract
一種半導體記憶體元件,包含半導體基底、選擇閘極,設置於所述半導體基底上,其中所述選擇閘極包含第一側壁和與所述第一側壁相對的第二側壁、控制閘極,設置於所述半導體基底上且靠近所述選擇閘極的所述第二側壁,以及電荷存儲層,設置於所述控制閘極與所述半導體基底之間。所述控制閘極包含靠近所述第二側壁的第三側壁、與所述第三側壁相對的第四側壁以及在所述第三側壁和所述第四側壁之間的非平坦頂面。所述非平坦頂面包含從所述第三側壁下降到所述第四側壁的第一表面區域。所述電荷存儲層延伸至所述第二側壁上。
Description
本發明涉及半導體技術領域,特別是涉及一種改良的半導體非揮發性記憶體元件。
非揮發性記憶體(例如快閃記憶體)在記憶體斷電時仍會保留存儲的數據。非揮發性記憶單元存儲數據是通過將電荷存儲在電隔離的存儲閘極或場效電晶體(FET)的控制閘極下方的電荷俘獲層中。存儲的電荷控制場效電晶體的閾值,從而控制記憶單元的存儲狀態。
編程非揮發性記憶單元使用例如熱載子注入以將電荷置於存儲層中。高汲極和閘極電壓用於促進編程過程,並且存儲單元在編程期間傳導相對高的電流,這在低電壓或低功率應用中可能是不合需要的。
分裂閘極(split gate)記憶單元是一種非揮發性記憶單元,其中選擇閘極與控制閘極相鄰放置。在分裂閘極記憶單元的編程期間,選擇閘極被偏置在相對低的電壓,並且只有控制閘極被偏置在高電壓以提供熱載子注入所需的垂直電場。由於載子的加速主要發生在選擇閘極下方的通道區,與傳統快閃記憶體單元相比,選擇閘極上相對較低的電壓導致水平方向上更有效的載子加速。這使得在編程操作期間熱載子注入效率更高,電流更低,功耗更低。
現有技術的缺點在於,分裂閘極記憶單元的選擇閘極與控制閘極需分別以微影及蝕刻製程定義,容易導致疊對偏移(overlay shift)和記
本發明的主要目的在提供一種改良的半導體記憶體元件,以解決現有技術的不足和缺點。
本發明一方面提供一種半導體記憶體元件,包含:一半導體基底;一選擇閘極,設置於所述半導體基底上,其中所述選擇閘極包含第一側壁和與所述第一側壁相對的第二側壁;一控制閘極,設置於所述半導體基底上且靠近所述選擇閘極的所述第二側壁,其中所述控制閘極包含靠近所述第二側壁的第三側壁、與所述第三側壁相對的第四側壁以及在所述第三側壁和所述第四側壁之間的非平坦頂面,其中所述非平坦頂面包含從所述第三側壁下降到所述第四側壁的第一表面區域;以及一電荷存儲層,設置於所述控制閘極與所述半導體基底之間,其中所述電荷存儲層延伸至所述第二側壁上。
根據本發明實施例,所述半導體基底包含沿第一方向延伸的鰭結構。
根據本發明實施例,所述選擇閘極沿第二方向延伸並跨越所述鰭結構。
根據本發明實施例,所述控制閘極沿所述第二方向延伸並跨越所述鰭結構。
根據本發明實施例,所述非平坦頂面還包含位於所述第一表面區域與所述第四側壁之間的第二表面區域,其中所述第二表面區域的斜率大於所述第一表面區域的斜率。
根據本發明實施例,所述非平坦頂面還包含連接所述第二表面區域與所述第四側壁的第三表面區域,其中所述第二表面區域、所述第三表面區域和所述第四側壁構成一階梯結構。
根據本發明實施例,所述第三表面區域低於所述第一表面區域和所述第二表面區域。
根據本發明實施例,所述選擇閘極是多晶矽電極。
根據本發明實施例,所述控制閘極是多晶矽電極。
根據本發明實施例,所述電荷存儲層是氧化物-氮化物-氧化物(ONO)層。
本發明另一方面提供一種形成半導體記憶體元件的方法,包含:提供一半導體基底;在所述半導體基底上形成一選擇閘極,其中所述選擇閘極包含第一側壁以及與所述第一側壁相對的第二側壁;在所述半導體基底上且靠近所述選擇閘極的第二側壁處以自對準方式形成一控制閘極,其中所述控制閘極包含靠近所述第二側壁的第三側壁、與所述第三側壁相對的第四側壁,以及位於所述第三側壁和所述第四側壁之間的非平坦頂面,其中所述非平坦頂面包含從所述第三側壁下降到所述第四側壁的第一表面區域;以及在所述控制閘極與所述半導體基底之間形成一電荷存儲層,其中所述電荷存儲層延伸到所述第二側壁上。
根據本發明實施例,所述半導體基底包含沿第一方向延伸的鰭結構。
根據本發明實施例,所述選擇閘極沿第二方向延伸並跨越所述鰭結構。
根據本發明實施例,所述控制閘極沿所述第二方向延伸並跨越所述鰭結構。
根據本發明實施例,所述非平坦頂面還包含位於所述第一表面區域與所述第四側壁之間的第二表面區域,其中所述第二表面區域的斜率大於所述第一表面區域的斜率。
根據本發明實施例,所述非平坦頂面還包含連接所述第二表面區域與所述第四側壁的第三表面區域,其中所述第二表面區域、所述第三表面區域和所述第四側壁構成一階梯結構。
根據本發明實施例,所述第三表面區域低於所述第一表面區域和所述第二表面區域。
根據本發明實施例,所述選擇閘極是多晶矽電極。
根據本發明實施例,所述控制閘極是多晶矽電極。
根據本發明實施例,所述電荷存儲層是氧化物-氮化物-氧化物(ONO)層。
本發明的主要技術特徵在於,先形成選擇閘極,再形成電荷存儲層,然後才以自對準方式形成控制閘極,如此,可以節省一道光罩,降低成本,而且以自對準方式形成控制閘極可以解決疊對偏移(overlay shift)和記憶體讀寫操作餘裕(read/write operation margin)不足等問題。
在下文中,將參照附圖說明細節,該些附圖中之內容亦構成說明書細節描述的一部份,並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。
當然,亦可採行其他的實施例,或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此,下文之細節描述不應被視為是限制,反之,其中所包含的實施例將由隨附的申請專利範圍來加以界定。
請參閱圖1和圖2,其中圖1是根據本發明實施例所繪示的半導體記憶體元件1的部分布局示意圖,圖2是沿著圖1中切線I-I’方向的剖面示意圖。半導體記憶體元件1可以是非揮發性記憶體,例如,分裂閘極記憶體。如圖1所示,半導體記憶體元件1包含半導體基底100,例如,矽基底,但不限於此。在半導體基底100上設置有沿著第一方向D1延伸的鰭結構F。在第二方向D2上,選擇閘極SG和控制閘極CG延伸跨越鰭結構F。選擇閘極SG緊鄰控制閘極CG,且在選擇閘極SG和控制閘極CG之間設有至少一絕緣層。
根據本發明實施例,選擇閘極SG是多晶矽電極。根據本發明實施例,控制閘極CG是多晶矽電極。
如圖1和圖2所示,半導體記憶體元件1包含選擇閘極SG,設置於半導體基底100的鰭結構F上,其中選擇閘極SG包含第一側壁SW1和與第一側壁SW1相對的第二側壁SW2,在第一側壁SW1和第二側壁SW2之間是平坦頂面PS。根據本發明實施例,選擇閘極SG的平坦頂面PS上形成有矽化金屬層SAS。
如圖1和圖2所示,半導體記憶體元件1還包含控制閘極CG,設置於半導體基底100的鰭結構F上且靠近選擇閘極SG的第二側壁SW2。控制閘極CG包含靠近第二側壁SW2的第三側壁SW3、與第三側壁SW3相對的第四側壁SW4,以及在第三側壁SW3和第四側壁SW4之間的非平坦頂面NPS。
根據本發明實施例,非平坦頂面NPS包含從第三側壁SW3下降到第四側壁SW4的第一表面區域S1,和位於第一表面區域S1與第四側壁SW4之間的第二表面區域S2,其中第二表面區域S2的斜率大於第一表面區域S1的斜率。
根據本發明實施例,非平坦頂面NPS還包含連接第二表面區域S2與第四側壁SW4的第三表面區域S3。根據本發明實施例,第三表面區域S3低於第一表面區域S1和第二表面區域S2。根據本發明實施例,第二表面區域S2、第三表面區域S3和第四側壁SW4構成一階梯結構SS。根據本發明實施例,控制閘極CG的非平坦頂面NPS上形成有矽化金屬層SAC。
根據本發明實施例,半導體記憶體元件1還包含電荷存儲層120,設置於控制閘極CG與半導體基底100的鰭結構F之間,其中,電荷存儲層120延伸至第二側壁SW2上,並且突出控制閘極CG的非平坦頂面NPS。根據本發明實施例,電荷存儲層120直接接觸到選擇閘極SG的平坦頂面PS的矽化金屬層SAS。根據本發明實施例,電荷存儲層120是氧化物-氮化物-氧化物(ONO)層。
根據本發明實施例,半導體記憶體元件1還包含設置在選擇閘極SG的第一側壁SW1上的側壁子SP1和設置在控制閘極CG的第四側壁SW4上的側壁子SP4。側壁子SP1和側壁子SP4可以包含氮化矽、氧化矽或氮氧化矽等,但不限於此。此外,在靠近側壁子SP1的鰭結構F中可以形成汲極區域102,在靠近側壁子SP4的鰭結構F中可以形成源極區域104。
請參閱圖3至圖15,其例示一種形成半導體記憶體元件的方法,其中,相同的區域、元件、層或材料仍沿用相同的符號來表示。如圖3所示,在基底100上的記憶體區MR和邏輯電路區LR內先沉積多晶矽層210、氧化矽層211和硬遮罩層220,再以微影和蝕刻製程,在記憶體區MR形成跨越鰭結構F的選擇閘極SG,其中,選擇閘極SG此時包括圖案化的多晶矽層210a、圖案化的氧化矽層211a和圖案化的硬遮罩層220a。根據本發明實施例,選擇閘極SG的多晶矽層210a的厚度小於邏輯電路區LR內的多晶矽層210。接著,在記憶體區MR和邏輯電路區LR均勻地沉積電荷存儲層120,例如,氧化物-氮化物-氧化物(ONO)層。
如圖4所示,接著,在電荷存儲層120上順形地沉積多晶矽層230和氧化矽層240。根據本發明實施例,多晶矽層230和氧化矽層240覆蓋記憶體區MR和邏輯電路區LR。根據本發明實施例,多晶矽層230不會填滿兩相鄰的選擇閘極SG之間的空間。根據本發明實施例,氧化矽層240的厚度可以約為80-120埃,例如,100埃。
如圖5所示,進行第一次的自對準非等向性乾蝕刻製程,先選擇性地將氧化矽層240蝕刻成在多晶矽層230上的側壁子,然後進行第二次的自對準非等向性乾蝕刻製程,繼續蝕刻多晶矽層230,最後在記憶體區MR內的選擇閘極SG旁邊形成自對準的多晶矽圖案240a和240b,其中,多晶矽圖案240a作為半導體記憶體元件的控制閘極CG。上述第二次的自對準非等向性乾蝕刻製程停止在電荷存儲層120的表面上。
根據本發明實施例,控制閘極CG包含非平坦頂面NPS,包括第一表面區域S1和第二表面區域S2,其中第二表面區域S2的斜率大於第一表面區域S1的斜率。根據本發明實施例,非平坦頂面NPS還包含連接第二表面區域S2的第三表面區域S3。根據本發明實施例,第三表面區域S3低於第一表面區域S1和第二表面區域S2。根據本發明實施例,第二表面區域S2、第三表面區域S3和控制閘極CG的側壁構成一階梯結構SS。
如圖6所示,接著,在記憶體區MR和邏輯電路區LR上形成圖案化光阻層PR,使圖案化光阻層PR覆蓋控制閘極CG,但是圖案化光阻層PR的開口OP顯露出與控制閘極CG相對的多晶矽圖案240b。根據本發明實施例,圖案化光阻層PR可以部分覆蓋住選擇閘極SG。接著,進行非等向性乾蝕刻製程,以圖案化光阻層PR和硬遮罩層220a作為蝕刻抵擋遮罩,向下蝕刻掉顯露出的多晶矽圖案240b,直到下方的電荷存儲層120被顯露出來。
如圖7所示,接著,將剩餘的圖案化光阻層PR去除,然後,以化學氣相沉積製程在記憶體區MR和邏輯電路區LR上順形地形成側壁子層,例如,氧化物-氮化物-氧化物(ONO)層,再以非等向性乾蝕刻製程蝕刻側壁子層,在選擇閘極SG和控制閘極CG的側壁上形成側壁子310。然後,可以進行離子佈植製程,在側壁子310旁的鰭結構F中形成汲極區域102和源極區域104。
如圖8所示,接著,選擇性地將記憶體區MR內的選擇閘極SG的硬遮罩層220a和邏輯電路區LR的硬遮罩層220一併去除,顯露出記憶體區MR內的氧化矽層211a和邏輯電路區LR內的氧化矽層211。然後,再次以化學氣相沉積製程在記憶體區MR和邏輯電路區LR上順形地形成側壁子層,例如,氧化物-氮化物(ON)層,再以非等向性乾蝕刻製程蝕刻側壁子層,在選擇閘極SG和控制閘極CG的側壁上形成另一側壁子410。
如圖9所示,接著,進行邏輯電路區LR內的閘極圖案化製程,利用微影和蝕刻製程,將邏輯電路區LR內的氧化矽層211和多晶矽層210圖案化成為虛設閘極結構DP。
如圖10所示,接著,以化學氣相沉積製程在記憶體區MR和邏輯電路區LR上順形地形成側壁子層,例如,氮化矽層,再以非等向性乾蝕刻製程蝕刻側壁子層,在記憶體區MR內的選擇閘極SG和控制閘極CG的側壁上分別形成側壁子SP1和SP4,同時在邏輯電路區LR內的虛設閘極結構DP側壁上形成側壁子SP。根據本發明實施例,接著,可以進行離子佈植製程,在邏輯電路區LR內的基底100內形成摻雜區502和504。
如圖11所示,接著,進行矽化金屬製程,在記憶體區MR內的選擇閘極SG上形成矽化金屬層SAS,在控制閘極CG的非平坦頂面NPS上形成矽化金屬層SAC。根據本發明實施例,矽化金屬層SAS和矽化金屬層SAC可以包含矽化鎳、矽化鈦、矽化鈷、矽化鎢等,但不限於此。根據本發明實施例,在不需要形成矽化金屬層的部分,例如,邏輯電路區LR內的虛設閘極結構DP上,可以形成矽化金屬阻擋層SAB。
如圖12至圖15所示,後續可以進行置換金屬閘極(replacement metal gate,RMG)製程,例如,如圖12所示,先以化學氣相沉積製程在記憶體區MR和邏輯電路區LR上順形地形成接觸蝕刻停止層610。例如,接觸蝕刻停止層610可以是氮化矽層。根據本發明實施例,接觸蝕刻停止層610可以具有伸張應力(tensile stress)。然後,如圖13所示,以化學氣相沉積製程在接觸蝕刻停止層610上沉積介電層620,然後,以化學機械研磨(CMP)製程進行介電層620的平坦化。後續,如圖14所示,將邏輯電路區LR內的虛設閘極結構DP去除,形成閘極溝渠GT。最後,如圖15所示,在閘極溝渠GT依序形成高介電常數層HK、阻障層BL和低阻值金屬層MG等閘極金屬材料。
本發明的主要技術特徵在於,先形成選擇閘極SG,再形成電荷存儲層120,然後才以自對準方式形成控制閘極CG,如此,可以節省一道光罩,降低成本,而且以自對準方式形成控制閘極CG可以解決疊對偏移(overlay shift)和記憶體讀寫操作餘裕(read/write operation margin)不足等問題。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
1:半導體記憶體元件
100:半導體基底
102:汲極區域
104:源極區域
120:電荷存儲層
210:多晶矽層
210a:圖案化的多晶矽層
211:氧化矽層
211a:圖案化的氧化矽層
220:硬遮罩層
220a:圖案化的硬遮罩層
230:多晶矽層
240:氧化矽層
240a、240b:多晶矽圖案
310、410:側壁子
610:接觸蝕刻停止層
620:介電層
D1:第一方向
D2:第二方向
F:鰭結構
SG:選擇閘極
CG:控制閘極
SW1:第一側壁
SW2:第二側壁
SW3:第三側壁
SW4:第四側壁
PS:平坦頂面
NPS:非平坦頂面
S1:第一表面區域
S2:第二表面區域
S3:第三表面區域
SS:階梯結構
SAS:矽化金屬層
SAC:矽化金屬層
SP1、SP4:側壁子
MR:記憶體區
LR:邏輯電路區
PR:圖案化光阻層
OP:開口
DP:虛設閘極
SAB:矽化金屬阻擋層
GT:閘極溝渠
HK:高介電常數層
BL:阻障層
MG:阻值金屬層
圖1是根據本發明實施例所繪示的半導體記憶體元件的部分布局示意圖。
圖2是沿著圖1中切線I-I’方向的剖面示意圖。
圖3至圖15例示一種形成半導體記憶體元件的方法。
1:半導體記憶體元件
100:半導體基底
102:汲極區域
104:源極區域
120:電荷存儲層
D1:第一方向
D2:第二方向
F:鰭結構
SG:選擇閘極
CG:控制閘極
SW1:第一側壁
SW2:第二側壁
SW3:第三側壁
SW4:第四側壁
PS:平坦頂面
NPS:非平坦頂面
S1:第一表面區域
S2:第二表面區域
S3:第三表面區域
SS:階梯結構
SAS:矽化金屬層
SAC:矽化金屬層
SP1、SP4:側壁子
Claims (20)
- 一種半導體記憶體元件,包含: 一半導體基底; 一選擇閘極,設置於所述半導體基底上,其中所述選擇閘極包含第一側壁和與所述第一側壁相對的第二側壁; 一控制閘極,設置於所述半導體基底上且靠近所述選擇閘極的所述第二側壁,其中所述控制閘極包含靠近所述第二側壁的第三側壁、與所述第三側壁相對的第四側壁以及在所述第三側壁和所述第四側壁之間的非平坦頂面,其中所述非平坦頂面包含從所述第三側壁下降到所述第四側壁的第一表面區域;以及 一電荷存儲層,設置於所述控制閘極與所述半導體基底之間,其中所述電荷存儲層延伸至所述第二側壁上。
- 根據請求項1所述的半導體記憶體元件,其中所述半導體基底包含沿第一方向延伸的鰭結構。
- 根據請求項2所述的半導體記憶體元件,其中所述選擇閘極沿第二方向延伸並跨越所述鰭結構。
- 根據請求項3所述的半導體記憶體元件,其中所述控制閘極沿所述第二方向延伸並跨越所述鰭結構。
- 根據請求項1所述的半導體記憶體元件,其中所述非平坦頂面還包含位於所述第一表面區域與所述第四側壁之間的第二表面區域,其中所述第二表面區域的斜率大於所述第一表面區域的斜率。
- 根據請求項5所述的半導體記憶體元件,其中所述非平坦頂面還包含連接所述第二表面區域與所述第四側壁的第三表面區域,其中所述第二表面區域、所述第三表面區域和所述第四側壁構成一階梯結構。
- 根據請求項6所述的半導體記憶體元件,其中所述第三表面區域低於所述第一表面區域和所述第二表面區域。
- 根據請求項1所述的半導體記憶體元件,其中所述選擇閘極是多晶矽電極。
- 根據請求項1所述的半導體記憶體元件,其中所述控制閘極是多晶矽電極。
- 根據請求項1所述的半導體記憶體元件,其中所述電荷存儲層是氧化物-氮化物-氧化物(ONO)層。
- 一種形成半導體記憶體元件的方法,包含: 提供一半導體基底; 在所述半導體基底上形成一選擇閘極,其中所述選擇閘極包含第一側壁以及與所述第一側壁相對的第二側壁; 在所述半導體基底上且靠近所述選擇閘極的第二側壁處以自對準方式形成一控制閘極,其中所述控制閘極包含靠近所述第二側壁的第三側壁、與所述第三側壁相對的第四側壁,以及位於所述第三側壁和所述第四側壁之間的非平坦頂面,其中所述非平坦頂面包含從所述第三側壁下降到所述第四側壁的第一表面區域;以及 在所述控制閘極與所述半導體基底之間形成一電荷存儲層,其中所述電荷存儲層延伸到所述第二側壁上。
- 根據請求項11所述的方法,其中所述半導體基底包含沿第一方向延伸的鰭結構。
- 根據請求項12所述的方法,其中所述選擇閘極沿第二方向延伸並跨越所述鰭結構。
- 根據請求項13所述的方法,其中所述控制閘極沿所述第二方向延伸並跨越所述鰭結構。
- 根據請求項11所述的方法,其中所述非平坦頂面還包含位於所述第一表面區域與所述第四側壁之間的第二表面區域,其中所述第二表面區域的斜率大於所述第一表面區域的斜率。
- 根據請求項15所述的方法,其中所述非平坦頂面還包含連接所述第二表面區域與所述第四側壁的第三表面區域,其中所述第二表面區域、所述第三表面區域和所述第四側壁構成一階梯結構。
- 根據請求項16所述的方法,其中所述第三表面區域低於所述第一表面區域和所述第二表面區域。
- 根據請求項11所述的方法,其中所述選擇閘極是多晶矽電極。
- 根據請求項11所述的方法,其中所述控制閘極是多晶矽電極。
- 根據請求項11所述的方法,其中所述電荷存儲層是氧化物-氮化物-氧化物(ONO)層。
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