TWI733046B - 積體半導體組件及其製造方法 - Google Patents

積體半導體組件及其製造方法 Download PDF

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TWI733046B
TWI733046B TW107128696A TW107128696A TWI733046B TW I733046 B TWI733046 B TW I733046B TW 107128696 A TW107128696 A TW 107128696A TW 107128696 A TW107128696 A TW 107128696A TW I733046 B TWI733046 B TW I733046B
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die
cavity
attached
peripheral area
base substrate
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TW107128696A
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TW201921609A (zh
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湯瑪士 H 金斯利
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美商美光科技公司
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Abstract

本文中揭示積體半導體組件及相關聯之製造方法。在一項實施例中，一半導體裝置組件包括一基底基板，該基底基板具有一腔及至少部分圍繞該腔之一周邊區域。該腔係由至少部分延伸通過該基板之側壁界定。該組件進一步包括經附接至該腔處之該基底基板之一第一晶粒，及在該第一晶粒之至少一部分上方並經附接至該周邊區域處之該基底基板之一第二晶粒。在一些實施例中，該第一晶粒及該第二晶粒可係經由該基板之電路而彼此電耦合。

Description

積體半導體組件及其製造方法
本發明技術係關於封裝半導體裝置(諸如記憶體及處理器)，且若干實施例係關於包含具有腔之基板之積體半導體組件。
經封裝半導體晶粒(包含記憶體晶粒、微處理器晶粒及介面晶粒)通常包含安裝於一基板上並被圍封於一塑膠保護覆蓋物中之一半導體晶粒。晶粒包含功能特徵件(諸如記憶體胞、處理器電路及互連電路)以及電連接至功能特徵件之接合墊。接合墊通常經電連接至保護覆蓋物之外部延伸之端子，以允許晶粒連接至匯流排、電路或其他更高階電路。
半導體晶粒製造商在增加壓力下，以持續地減少晶粒封裝之尺寸，以適配於電子裝置之空間約束內，而亦增加各封裝之功能容量，以滿足操作參數。一種用於增加一半導體封裝之處理能力而不實質上增加由封裝覆蓋之表面積(即，封裝之「佔據面積」)之方法係在一單一封裝中將多個半導體晶粒垂直地堆疊於彼此之頂部上。然而，堆疊多個晶粒增加裝置之垂直輪廓，需要使個別晶粒實質上薄化以達成一垂直緊湊尺寸。另外，多個晶粒之堆疊可增加裝置故障之可能性，並導致與較長製造及測試時間相關聯之較高成本。
在一些實施例中，一種半導體裝置組件包括：一基底基板，其具有一腔及至少部分圍繞該腔之一周邊區域，其中該腔至少部分延伸通過該基底基板；一第一晶粒，其在該腔中並附接至該腔處之該基底基板；及一第二晶粒，其在該第一晶粒之至少一部分上方並附接至該周邊區域處之該基底基板。
在一些實施例中，一種堆疊封裝系統包括：一基板，其具有一腔區域及至少部分在該腔區域周圍之一周邊區域，其中該腔區域係由至少部分延伸通過該基板之側壁界定；一第一晶粒，其經附接至該基板並定位於該腔區域之該等側壁之間；及一第二晶粒，其在該第一晶粒上方並附接至該周邊區域處之該基底基板。
在一些實施例中，一種形成一半導體裝置組件之方法，該方法包括：提供一基底基板，該基底基板具有一腔及至少部分圍繞該腔之一周邊區域，其中該腔至少部分延伸通過該基底基板；將一第一晶粒安裝至該腔處之該基底基板；及將一第二晶粒安裝於該第一晶粒之至少一部分上方並至該周邊區域處之該基底基板。
下文描述堆疊半導體晶粒封裝之若干實施例之具體細節及製造此等晶粒封裝之方法。術語「半導體裝置」通常係指包含半導體材料之一固態裝置。一半導體裝置可包含(舉例而言)一半導體基板、晶圓或自一晶圓或基板單體化之晶粒。貫穿本發明，大致在半導體晶粒之上下文中描述半導體裝置；然而，半導體裝置並非限於半導體晶粒。
術語「半導體裝置封裝」可係指具有併入於一共同封裝中之一或多個半導體裝置之一配置。一半導體封裝可包含部分地或全部地囊封至少一個半導體裝置之一外殼或殼體(casing)。一半導體裝置封裝亦可包含承載一或多個半導體裝置且附接至或以其他方式併入於殼體中之一插入器基板。術語「堆疊封裝組件」可係指堆疊於彼此上之一或多個個別半導體裝置封裝之一組件或一堆疊封裝組件。
如本文中所使用，術語「垂直」、「橫向」、「頂部」、「底部」、「上」及「下」可係指圖中所示之定向之半導體裝置或封裝視圖中之特徵件之相對方向或位置。例如，「上」或「最外」可係指定位為比另一特徵件更接近一頁面之頂部之一特徵件。然而，此等術語應廣泛地解釋為包含具有其他定向(諸如其中可取決於定向而互換頂部/底部、上方/下方、之上/之下、上/下、水平/垂直及左/右之顛倒或傾斜定向)之半導體裝置。
圖1A係根據本技術之一實施例構形之一半導體裝置組件100(「組件100」)之一示意性截面圖，且圖1B係沿著線1B-1B截取之圖1A中所示之組件100之一示意性俯視圖。圖1A中所示之組件100係沿著圖1B之線1A-1A截取。一起參考圖1A及圖1B，組件100包含一基底基板110、安裝至基板110之一第一晶粒120及安裝至基板110之一第二晶粒130。基板110包含一第一側111a、與第一側111a相對之一第二側111b、第一側111a處之一腔115及具有用於將第一半導體晶粒120及第二半導體晶粒130彼此電耦合之電路(例如，銅跡線及通路)、其他電子裝置及/或電連接器116(例如，焊球、金指狀物或其他互連件)之一或多個電源及/或信號層117。例如，基板110可為一印刷電路板(PCB)或通常用於半導體裝置封裝中之其他類型之基板。在一些實施例中，基板110可至少部分由矽形成。基板110包含一腔區域(C)及至少部分圍繞腔區域(C)之一周邊區域(P)。因而，基板110包含一連續最外表面，該連續最外表面包含周邊區域(P)之至少一上表面112a、腔區域(C)之一下表面112b及側壁128。在所繪示之實施例中，周邊區域(P)完全圍繞腔區域(C)。
腔115經定位於基板之腔區域(C)中，並由側壁128及下表面112b界定。側壁128至少部分延伸通過基板110至一中間深度或一第二距離(D2 )。在一些實施例中，側壁128可自第一側111a延伸通過基板110至第二側111b。在圖1B之所繪示之實施例中，腔115經完全定位於基板110內，且因此包含四個側壁128。在其他實施例中，腔115可延伸至或超過基板110之一長度或寬度，且因此可僅包含兩個側壁128(例如，圖3)。儘管圖1A及圖1B中所繪示之腔115具有含四個側壁之一直線平面，但在其他實施例中，一腔可具有數個其他形狀之任一者，包含具有任何數目之邊之規則多邊形、不規則多邊形、橢圓或曲線形狀等。
第一晶粒120經定位於腔115內，並包含一頂部表面121a及與頂部表面121a相對之一底部表面121b。第一晶粒120經由底側121b處之複數個電連接器122(例如，焊球、接合墊等)而附接至基底基板110。頂部表面121a與腔115之下表面112b分離一第一距離(D1 )。在所繪示之實施例中，第一距離(D1 )小於先前描述之第二距離(D2 )。因此，第一晶粒120經完全定位於腔115內，使得第一晶粒120之頂部表面121a處於基板110之周邊區域(P)之上表面112a下方。在其他實施例中，第一距離(D1 )可等於(例如，圖2A至圖2C)或略大於第二距離(D2 )。第一晶粒120可包含一記憶體裝置或記憶體模組(例如，DRAM、LPDRAM、SRAM、DIMM、NVDIMM、RDIMM、LRDIMM、快閃記憶體等)。在一些實施例中，第一晶粒120可包含一邏輯裝置及/或處理器。
圖1A之所繪示之實施例包含僅一單一晶粒。在一些實施例中，額外晶粒可經包含於腔115中。例如，腔115中之晶粒之一堆疊可經構形為一混合記憶體立方體(HMC)，其中最下晶粒係提供記憶體控制(例如，DRAM控制)之一邏輯晶粒，且在最下晶粒上方之堆疊晶粒係DRAM或提供資料儲存之其他記憶體晶粒。在此一實施例中，堆疊之最外晶粒之一頂部表面處於第二晶粒130之一底部表面下方。
第二晶粒130經定位於第一晶粒120之一部分上方，並包含一頂部表面137a及一底部表面137b。因而，第二晶粒130橫越第一晶粒120及腔區域115。第二晶粒130經由電連接器132(例如，焊球、接合墊等)而附接至周邊區域(P)處之基板110。電連接器132可經由基板110而將第二晶粒130電耦合至(i)基板110及/或(ii)第一晶粒120。在所繪示之實施例中，第二晶粒130包含大於腔115及第一晶粒120之尺寸之一橫向尺寸。第二晶粒130之底部表面137b與腔區域(C)之下表面112b間隔開一第三距離(D3 )。第三距離(D3 )大於第一距離(D1 )及第二距離(D2 )之各者。第二晶粒130可為一邏輯裝置、處理器或另一記憶體裝置。視情況，組件100亦可包含第一晶粒120與第二晶粒130之間之電連接器140(例如，焊球、接合墊等)。在此一實施例中，電連接器140將第一晶粒120直接電耦合至第二晶粒130。
本技術之一個益處係藉由將第一晶粒120安裝於腔115內及/或第二晶粒130下方而達成組件100之減少厚度。因為第一晶粒120經安裝於腔115內，所以第二晶粒130可經安裝於第一晶粒120上方並靠近基板之上表面112a，藉此減少總組件之厚度。如先前所提及，堆疊裝置具有較高裝置故障之機率及與較長製造及測試時間相關聯之較高成本。因此，包含本技術之組件可導致較高產率、更有效製造及減少的成本。
本技術之另一益處係能夠更有效地自第一晶粒120及/或第二晶粒130消散熱量。與其中多個晶粒經直接堆疊於彼此上方之習知堆疊裝置不同，本技術包含第一晶粒120與第二晶粒130之間的氣隙，藉此允許兩個晶粒經由對流冷卻至周圍環境。因此，與一堆疊裝置相比，組件100可維持一較低平均操作溫度，導致更有效操作及更長運行時間。
本技術之又另一益處係第二晶粒130相對於第一晶粒120的定位。在習知堆疊組件中，處理器通常係主要產熱源，並且通常係定位於堆疊之底部處的基板附近。此部分係因為處理器通常包含相對於堆疊之其他晶粒之最大橫向尺寸。此類型之配置導致熱量被捕獲於堆疊之底部處，並導致組件之一總體增加的操作溫度。與習知堆疊組件不同，本技術之第二晶粒130可包含一處理器且經定位於第一晶粒120上方。因而，自處理器產生之任何熱量向上朝向周圍環境釋放，並對腔115內之第一晶粒120具有較小熱效應。因此，本技術可導致一較低操作溫度及更有效率裝置。
圖2A至圖2C係繪示根據本技術之一實施例之形成一半導體裝置組件(諸如或類似於組件100)之一方法之示意性截面圖。圖2A繪示在腔115已經形成於基板110中且第一晶粒120已經安置於側壁128之間之腔115內之後的方法。腔115可係藉由研磨、乾式蝕刻、化學蝕刻、化學拋光、化學機械拋光或本技術中已知之其他適合製程形成。可預判定腔之橫向尺寸或寬度，以確保第一晶粒120可適配於腔115內。類似地，可基於在迴流之前及/或之後第一晶粒120及電連接器122的組合高度來預判定腔115的深度。在所繪示之實施例中，第一晶粒120之頂部表面121a通常係與基板110之周邊區域(P)之上表面112a共面。
圖2B繪示在一模具材料220(例如，一底部填充材料、囊封件等)已經沈積於腔115中以囊封第一晶粒120之後之方法之一實施例。在所繪示之實施例中，模具材料220之一外表面與基板110之周邊區域(P)之上表面112a齊平。因此，在所繪示之實施例中，模具材料220僅部分囊封第一晶粒120，因為第一晶粒120之頂部表面121a通常與周邊區域(P)之上表面112a共面並因此通過模具材料220暴露。在其他實施例中，第一晶粒120之頂部表面121a處於上表面112a下方(例如，圖1A及圖1B)。在此一實施例中，頂部表面121a不通過模具材料220暴露，且因此模具材料220完全囊封第一晶粒120。在其他實施例中，模具材料220可被省略。
圖2C繪示在第二晶粒130經安置於第一晶粒120及/或腔115之至少一部分上方並在周邊區域(P)處安裝至基板110之後之方法之一實施例。第二晶粒130可經由基板110之電路而電耦合至第一晶粒。如先前參考圖1A所描述，在一些實施例中，方法可進一步包含在將第二晶粒130安置於基板110之前將電連接器(未展示)沈積於第一晶粒120與第二晶粒130之間。在此一實施例中，電連接器將第一晶粒120直接耦合至第二晶粒130。如下文參考圖3及圖4所進一步詳細描述，方法可進一步包含將一第三晶粒安置於基板110上，該第三晶粒經堆疊於第二晶粒130上或與第二晶粒130間隔開。
圖3係根據本技術之另一實施例構形之一半導體裝置組件(「組件300」)之一示意性俯視圖。組件300通常類似於先前描述之組件100。例如，組件300包含基板110，基板110具有含定位於其中之第一晶粒120之一腔315。組件300包含一腔區域(C)及僅部分圍繞腔區域(C)之一周邊區域(P)。組件300進一步包含一第二晶粒330及一第三晶粒335，第二晶粒330及第三晶粒335各自附接至周邊區域(P)處之基板110。第二晶粒330包含一頂部表面331a及與頂部表面331a相對之一底部表面331b。底部表面331b經由電連接器132而附接至基板110。第三晶粒335包含一頂部表面336a及與頂部表面336a相對之一底部表面336b。底部表面336b經由電連接器132而附接至基板110。第二晶粒330及第三晶粒335各自橫越第一晶粒120之一不同部分。
圖4係根據本技術之另一實施例構形之一半導體裝置組件400(「組件400」)之一示意性截面圖。組件400通常類似於先前描述之組件100。例如，組件400包含具有腔115之基板110、定位於腔115中之第一晶粒120、及第一晶粒120上方並附接至周邊區域(P)處之基板110之第二晶粒130。組件400包含堆疊於第二晶粒130上並附接至第二晶粒130之一第三晶粒430。第三晶粒430可經由複數個電連接器(例如，焊球、接線等)而電耦合至第二晶粒130。在其他實施例中，第三晶粒430可經由包含互連件、晶粒附接膜、TSV及/或本技術中之其他已知方法之其他構件而經附接並電耦合至第二晶粒130。熟習此項技術者將瞭解，可在第三晶粒430及/或基板110上方堆疊額外晶粒。
圖5係根據本技術之另一實施例構形之一半導體裝置組件500(「組件500」)之一示意性截面圖。組件500通常類似於先前描述之組件100。例如，組件500包含具有腔115之基板110、定位於腔115中之第一晶粒120、及第一晶粒120上方並附接至周邊區域(P)處之基板110之第二晶粒130。組件500包含基板110之第二側111b處之一第二腔515、定位於腔515中並附接至基板110之一第三晶粒520、及橫越第三晶粒520並經由接合墊532而附接至周邊區域(P)處之基板110之一第四晶粒530。與用焊球或類似者附接至基板之一晶粒相比，接合墊532可進一步減少組件500之厚度。第三晶粒520及/或第四晶粒530可經由基板110之電路而電耦合至第一晶粒120及/或第二晶粒130。第二側111b處之第二腔515、第三晶粒520及第四晶粒530之配置可與第一側111a處之第一腔115、第一晶粒120及第二晶粒130之配置類似或相同。因此，先前參考組件100及圖1A至圖1B描述之特徵及益處亦適於組件500。在一些實施例中，可自組件500省略第四晶粒530。在此一實施例中，組件500可包含在基板110之第二側111b處之周邊區域(P)上方之電連接器(例如，來自圖1A之電連接器116)。組件500亦可包含電連接(諸如邊緣指狀物、互連插座及通常在PCB上可見之其他類似結構)。
圖6係根據本技術之另一實施例構形之一半導體裝置組件600(「組件600」)之一示意性截面圖。組件600包含通常類似於先前描述之組件100之特徵件。例如，組件600包含具有腔115之基板110，及在周邊區域(P)處附接至基板110之第二晶粒130。組件600包含一第一晶粒620，第一晶粒620包含面向第二晶粒130之一第一表面627a，及與第一表面627a相對並面向基板110之一第二表面627b。第一晶粒620可經由一膠帶、晶粒附接膜、接合墊或本技術中已知之其他方法而附接至第二晶粒130。第一晶粒620至少部分處於腔115內，使得第一晶粒620之一部分處於側壁128之間及/或上表面112a下方。在所繪示之實施例中，例如，第二表面627b低於上表面112a。第一晶粒620可經電耦合至第二晶粒130並經由第二晶粒130及電連接器132而電耦合至基板110。第一晶粒620可包含與先前描述之第一晶粒120類似或相同之特徵件。組件600可視情況包含附接至頂側137a處之第二晶粒130之一第三晶粒650。第三晶粒650可包含與先前描述之第一晶粒120或第二晶粒130類似或相同之特徵件。組件600可經由如參考圖2A及圖2C所描述之一類似方法而形成，除了在第二晶粒經附接至基板110之前第一晶粒620經附接至第二晶粒130之外。在第一晶粒620經附接至第二晶粒130之前或之後，第三晶粒650可經附接至第二晶粒130。
圖7係根據本技術之另一實施例構形之一半導體裝置組件700(「組件700」)之一示意性截面圖。組件700包含一第一晶粒720a及一第二晶粒720b，第一晶粒720a及第二晶粒720b處於側壁128之間並經由電連接器122而附接至腔115處之基板110。第一晶粒720a及第二晶粒720b可各自包含類似於先前描述之第一晶粒120之特徵件之特徵件。組件700進一步包含第一晶粒720a及/或第二晶粒720b之至少一部分上方之一第三晶粒730a、一第四晶粒730b及一第五晶粒730c。第三晶粒730a、第四晶粒730b及第五晶粒730c可各自包含通常類似於先前描述之第二晶粒130之特徵件之特徵件。第三晶粒730a及第五晶粒730c經由電連接器132而各自附接至基底基板，其中電連接器132之一第一部分經直接附接至基板110之上表面112a處之周邊區域(P)，且電連接器132之一第二部分經直接附接至第一晶粒720a之一頂部表面721a。因而，第三晶粒730a及第五晶粒730c各別地延伸於(a)腔115及(b)第一晶粒720a或第二晶粒720b之僅一部分上方。第四晶粒730b經由電連接器132直接附接至第一晶粒720a及第二晶粒720b，其中電連接器132之一第一部分附接至第一晶粒720a之頂部表面721a，且電連接器132之一第二部分附接至第二晶粒720b之一頂部表面721b。因而，第四晶粒730b經定位於腔115上方並在側壁128之間。在一些實施例中，第三晶粒730a、第四晶粒730b及/或第五晶粒730c可被省略。例如，組件700可包含僅第四晶粒730b或僅第三晶粒730a及第五晶粒730c。
上文參考圖1A至圖7描述之半導體裝置及/或組件之任一者可經併入於無數較大及/或較複雜系統之任一者中，該等系統之一代表實例係圖8中示意性展示之系統890。系統890可包含一半導體裝置組件800(「組件800」)、一電源892、一驅動器897、一處理器896及/或其他子系統或組件898。組件800可包含通常類似於上文所描述之此等組件之特徵件。所得系統890可執行多種功能(諸如記憶體儲存、資料處理及/或其他適合功能)之任一者。因此，代表性系統890可包含(不限於)手持式裝置(例如，行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦及器具。系統890之組件可容納於一單一單元中或(例如，透過一通訊網路)分佈遍及多個互連單元。系統890之組件亦可包含遠端裝置及多種電腦可讀媒體之任一者。
本發明不意欲為詳盡性或將本技術限制於本文中所揭示之精確形式。儘管本文為闡釋性目的揭示特定實施例，然而相關技術之一般技術者將認知各種等效修改在不脫離本技術之情況下係可能的。例如，圖4之所繪示的實施例(包含堆疊裝置)及圖5(包含多個腔及定位於其中之晶粒)可經組合或併入於其他實施例(諸如圖6之所繪示之實施例)中。在一些情況下，未詳細展示或描述熟知的結構及功能以避免不必要模糊本技術之實施例的描述。例如，熟習此項技術者將瞭解，先前描述之晶粒可包含複數個被動組件(諸如電阻器、電容器及/或併入於其中之其他類型的電子裝置)。雖然本文中以特定順序呈現方法之步驟，但是替代實施例可以一不同順序執行步驟。類似地，在其他實施例中，可組合或排除特定實施例之內容中揭示之本技術的某些態樣。此外，儘管可能已在該等實施例之內容中揭示與本技術之某些實施例相關聯的優點，然而其他實施例亦可展現此等優點，且並非所有實施例必須展現此等優點或本文中揭示之其他優點以落在本技術的範疇內。因此，本發明及相關聯技術可涵蓋本文中未明確展示或描述之其他實施例，且除了隨附申請專利範圍之外，本發明不受限制。
貫穿本發明，單數術語「一」、「一個」及「該」包含複數個參考物，除非內容另有清楚指示。類似地，除非單詞「或」明確限於意謂排除相對於具有兩個或兩個以上物體之一清單中之其他物體之僅一單個物體，則此一清單中使用「或」應解釋為包含(a)清單中之任一單個物體、(b)清單中之所有物體，或(c)清單中之物體之任何組合。此外，貫穿全文，術語「包括」、「包含」及「具有」係用以意謂包含至少(該等)所敘述特徵件，使得不會排除相同特徵部之任何更大數目及/或其他特徵部之額外類型。本文中參考「一個實施例」、「一實施例」或類似陳述意謂本技術之至少一實施例可包含結合實施例描述之一特定特徵部、結構、操作或特徵。因此，本文中存在之此等片語或陳述不一定全部指代相同實施例。此外，各種特定特徵件、結構、操作或特徵可係以任何合適方式組合在一或多項實施例中。
100‧‧‧半導體裝置組件110‧‧‧基底基板111a‧‧‧第一側111b‧‧‧第二側112a‧‧‧上表面112b‧‧‧下表面115‧‧‧腔116‧‧‧電連接器117‧‧‧信號層120‧‧‧第一半導體晶粒121a‧‧‧頂部表面121b‧‧‧底部表面122‧‧‧電連接器128‧‧‧側壁130‧‧‧第二半導體晶粒132‧‧‧電連接器137a‧‧‧頂部表面137b‧‧‧底部表面140‧‧‧電連接器220‧‧‧模具材料300‧‧‧組件315‧‧‧腔330‧‧‧第二晶粒331a‧‧‧頂部表面331b‧‧‧底部表面335‧‧‧第三晶粒336a‧‧‧頂部表面336b‧‧‧底部表面400‧‧‧半導體裝置組件430‧‧‧半導體裝置組件515‧‧‧第二腔520‧‧‧第三晶粒530‧‧‧第四晶粒532‧‧‧接合墊600‧‧‧半導體裝置組件620‧‧‧第一晶粒627a‧‧‧第一表面627b‧‧‧第二表面650‧‧‧第三晶粒700‧‧‧半導體裝置組件720a‧‧‧第一晶粒720b‧‧‧第二晶粒721a‧‧‧頂部表面721b‧‧‧頂部表面730a‧‧‧第三晶粒730b‧‧‧第四晶粒730c‧‧‧第五晶粒800‧‧‧半導體裝置組件890‧‧‧系統892‧‧‧電源896‧‧‧處理器897‧‧‧驅動器898‧‧‧其他子系統或組件1B-1B‧‧‧線C‧‧‧腔區域D1‧‧‧第一距離D2‧‧‧第二距離D3‧‧‧第三距離P‧‧‧周邊區域
圖1A係根據本技術之一實施例構形之一半導體裝置組件之一示意性截面圖。
圖1B係沿著線1B-1B截取之圖1A中所示之半導體裝置組件之一示意性俯視圖。
圖2A至圖2C係繪示根據本技術之一實施例之形成一半導體裝置組件之一方法之示意性截面圖。
圖3係根據本技術之另一實施例構形之一半導體裝置組件之一示意性俯視圖。
圖4至圖7係根據本技術之其他實施例構形之半導體裝置組件之示意性截面圖。
圖8係包含根據本技術之實施例構形之一半導體晶粒組件之一系統之一示意圖。
100‧‧‧半導體裝置組件
110‧‧‧基底基板
111a‧‧‧第一側
111b‧‧‧第二側
112a‧‧‧上表面
112b‧‧‧下表面
115‧‧‧腔
116‧‧‧電連接器
117‧‧‧信號層
120‧‧‧第一半導體晶粒
121a‧‧‧頂部表面
121b‧‧‧底部表面
122‧‧‧電連接器
128‧‧‧側壁
130‧‧‧第二半導體晶粒
132‧‧‧電連接器
137a‧‧‧頂部表面
137b‧‧‧底部表面
140‧‧‧電連接器
1B-1B‧‧‧線
C‧‧‧腔區域
D1‧‧‧第一距離
D2‧‧‧第二距離
D3‧‧‧第三距離
P‧‧‧周邊區域

Claims (29)

  1. 一種半導體裝置組件，其包括：一基底基板，其具有一腔及至少部分圍繞該腔之一周邊區域，其中該腔至少部分延伸通過該基底基板並具有跨越該周邊區域之相對邊緣所測量之一開口寬度；一第一晶粒，其在該腔中，並經附接至該腔處之該基底基板，其中該第一晶粒具有沿與該開口寬度正交之一第一橫向方向所測量之一第一長度；及一第二晶粒，其在該第一晶粒之至少一部分上方，延伸跨越該周邊區域之該等相對邊緣，並經附接至該周邊區域處之該基底基板，其中該第二晶粒具有(1)大於該腔之該開口寬度的一晶粒寬度及(2)沿與該第一橫向方向平行之一第二橫向方向所測量的一第二晶粒長度，該第二晶粒長度小於該第一長度；其中該第一晶粒之一頂部表面及該第二晶粒之一底部表面係由一距離分離，該距離對應於用於經由對流冷卻該第一晶粒及該第二晶粒的一空氣通道。
  2. 如請求項1之組件，其中該基底基板包含沿著該腔之一下表面及該周邊區域之一上表面跨越之一連續最外表面。
  3. 如請求項1之組件，其中該周邊區域包含一上表面，且該腔包含與該上表面分離一第一距離之一下表面，且其中該第一晶粒包含與該腔之該下 表面分離小於該第一距離之一第二距離之一頂部表面。
  4. 如請求項1之組件，其中該第一晶粒及該第二晶粒經附接至具有複數個焊球之該基底基板。
  5. 如請求項1之組件，其中該第一晶粒及該第二晶粒經附接至具有複數個接合墊之該基底基板。
  6. 如請求項1之組件，進一步包括該第一晶粒與該第二晶粒之間及經附接至該第一晶粒及該第二晶粒之複數個焊球。
  7. 如請求項6之組件，其中該複數個焊球接觸該第一晶粒之該頂部表面及該第二晶粒之該底部表面。
  8. 如請求項1之組件，其中該周邊區域完全圍繞該腔。
  9. 如請求項1之組件，進一步包括至少部分囊封該第一晶粒及/或該第二晶粒之一囊封件，其中該囊封件之一頂部表面係低於該第二晶粒之該底部表面。
  10. 如請求項1之組件，其中該第一晶粒包含一記憶體晶片，且該第二晶粒包含一處理器晶片。
  11. 如請求項1之組件，進一步包括經附接至該第二晶粒之一第三晶粒，其中該第三晶粒處於該第一晶粒及該第二晶粒上方。
  12. 如請求項1之組件，其中該第一晶粒之該部分係一第一部分，該組件進一步包括經附接至該周邊區域處之該基底基板並與該第二晶粒間隔開之一第三晶粒，其中該第三晶粒處於該第一晶粒之至少一第二部分上方。
  13. 如請求項1之組件，其中該基底基板包含一第一側及與該第一側相對之一第二側，其中該周邊區域係一第一周邊區域，且該腔係一第一腔，且其中該第一腔及該第一周邊區域處於該基底基板之該第一側，該組件進一步包括：一第二腔，其處於該基板之該第二側，並至少部分延伸通過該基板朝向該基板之該第一側；一第二周邊區域，其至少部分圍繞該第二腔；一第三晶粒，其在該第二腔中，並經附接至該第二腔處之該基底基板；及一第四晶粒，其在該第三晶粒上方，並經附接至該第二周邊區域處之該基底基板。
  14. 一種堆疊封裝系統，其包括：一基板，其具有一腔區域及至少部分在該腔區域周圍之一周邊區域，其中該腔區域係由至少部分延伸通過該基板之側壁界定，且該腔區域由橫跨該等側壁之相對部分所測量之一開口寬度分離。； 一第一晶粒，其經附接至該基板，並經定位於該腔區域之該等側壁之間，其中該第一晶粒具有沿與該開口寬度正交之一第一橫向方向所測量之一第一長度；及一第二晶粒，其在該第一晶粒上方，延伸跨越該開口寬度以及在該周邊區域之該等相對部分上方延伸，並經附接至該周邊區域處之該基底基板，其中該第二晶粒具有(1)大於該腔區域之該開口寬度的一晶粒寬度及(2)沿與該第一橫向方向平行之一第二橫向方向所測量的一第二晶粒長度，該第二晶粒長度小於該第一長度；其中該第一晶粒之一頂部表面及該第二晶粒之一底部表面係由一距離分離，該距離對應於用於經由對流冷卻該第一晶粒及該第二晶粒的一空氣通道。
  15. 如請求項14之系統，其中該腔區域包含該等側壁之間之一下表面，且其中該第一晶粒係經由複數個連接器而附接至該下表面。
  16. 如請求項15之系統，其中該複數個連接器包含接合墊。
  17. 如請求項14之系統，其中該第二晶粒包含至少部分面向該基板之一底側及與該底側相對之一頂側，且其中該第一晶粒經附接至該底側處之該第二晶粒。
  18. 如請求項17之系統，進一步包括經附接至該第二晶粒之一第三晶粒，其中該第三晶粒經堆疊於該第二晶粒之該頂側上。
  19. 如請求項14之系統，其中該第一晶粒之至少一部分延伸於該基板之該腔區域中。
  20. 如請求項14之系統，進一步包括與該第一晶粒間隔開並經附接至該腔區域處之該基板之一第三晶粒。
  21. 如請求項14之系統，其中經附接至該周邊區域處之該基底基板之該第二晶粒係一第一部分，且其中該第二晶粒包含經附接至該腔區域之該等側壁之間之該第一晶粒之一第二部分。
  22. 一種形成一半導體裝置組件之方法，該方法包括：提供一基底基板，該基底基板具有一腔及至少部分圍繞該腔之一周邊區域，其中該腔至少部分延伸通過該基底基板並具有跨越該周邊區域之相對邊緣所測量之一開口寬度；將一第一晶粒安裝至該腔處之該基底基板，其中該第一晶粒具有沿與該開口寬度正交之一第一橫向方向所測量之一第一長度；及將一第二晶粒安裝於該第一晶粒之至少一部分上方，延伸跨越該周邊區域之該等相對邊緣，並至該周邊區域處之該基底基板，其中該第二晶粒具有(1)大於該腔之該開口寬度的一晶粒寬度及(2)沿與該第一橫向方向平行之一第二橫向方向所測量的一第二晶粒長度，該第二晶粒長度小於該第一長度，其中該第二晶粒係經安裝使得該第一晶粒之一頂部表面及該第二晶粒之一底部表面係由一距離分離，該距離對應於用於經由對流冷卻該 第一晶粒及該第二晶粒的一空氣通道。
  23. 如請求項22之方法，其中安裝一第一晶粒包含將該第一晶粒附接至具有焊球之該腔內之該基底基板。
  24. 如請求項23之方法，其中安裝一第二晶粒包含將該第二晶粒附接至具有接合墊之該周邊區域。
  25. 如請求項22之方法，其中該第一晶粒係一記憶體晶片，且該第二晶粒係一處理器晶片，該方法進一步包括將該記憶體晶片電耦合至該處理器晶片。
  26. 如請求項22之方法，進一步包括：在安裝該第二晶粒之前，將複數個焊球沈積於該第一晶粒之一頂部表面上；及經由該複數個焊球，將該第二晶粒附接至該第一晶粒。
  27. 如請求項22之方法，進一步包括將一第三晶粒安裝於該第一晶粒上方，其中該第三晶粒經附接至該基底基板。
  28. 如請求項22之方法，其進一步包括將一第三晶粒安裝於該第二晶粒上方，其中安裝該第三晶粒包含將該第三晶粒堆疊於該第二晶粒上。
  29. 如請求項27之方法，其中安裝一第三晶粒包含經由焊球將該第三晶粒附接至該周邊區域。
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