TWI727454B - 積體電路封裝件及其形成方法 - Google Patents

積體電路封裝件及其形成方法 Download PDF

Info

Publication number
TWI727454B
TWI727454B TW108136454A TW108136454A TWI727454B TW I727454 B TWI727454 B TW I727454B TW 108136454 A TW108136454 A TW 108136454A TW 108136454 A TW108136454 A TW 108136454A TW I727454 B TWI727454 B TW I727454B
Authority
TW
Taiwan
Prior art keywords
dies
die
level
memory
dielectric
Prior art date
Application number
TW108136454A
Other languages
English (en)
Other versions
TW202018831A (zh
Inventor
余振華
余國寵
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202018831A publication Critical patent/TW202018831A/zh
Application granted granted Critical
Publication of TWI727454B publication Critical patent/TWI727454B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H01L2224/25171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

一種方法，包含將多個第一晶粒置放在載體上方。多個 第一晶粒至少包含第一邏輯晶粒及第一記憶體晶粒，將多個第二晶粒置放在多個第一晶粒上方。多個第二晶粒電耦接至多個第一晶粒且至少包含第二邏輯晶粒及第二記憶體晶粒。多個第三晶粒置放在多個第二晶粒的上方且電耦接至多個第一晶粒及多個第二晶粒。多個第三晶粒至少包含第三邏輯晶粒及第三記憶體晶粒。所述方法更包含將電連接件形成於多個第一晶粒、多個第二晶粒以及多個第三晶粒上方並電耦接至多個第一晶粒、多個第二晶粒以及多個第三晶粒。

Description

積體電路封裝件及其形成方法
本發明實施例是有關於一種積體電路封裝件及其形成方法。
積體電路的封裝件已變得愈發複雜，其中將更多元件晶粒整合於同一封裝件中以達成更多功能。舉例而言，系統整合晶片(System-on-Integrated-Chip；SoIC)已被開發成在同一封裝件中包含諸如處理器及記憶立方體的多個元件晶粒。在SoIC中，使用不同的技術形成且具有不同的功能的元件晶粒可以2D並列及3D堆疊方式兩者接合以形成具有較高的運算效率、較高的頻寬、較高的功能封裝密度、較低的通信延遲以及較低的每位元資料能量消耗的系統。
本發明實施例提供一種形成積體電路封裝件的方法，包括：將多個第一晶粒置放在載體上方，其中多個第一晶粒至少包括第一邏輯晶粒及第一記憶體晶粒；將多個第二晶粒置放在多個第一晶粒上方，其中多個第二晶粒電耦接至多個第一晶粒，且其 中多個第二晶粒至少包括第二邏輯晶粒及第二記憶體晶粒；將多個第三晶粒置放在多個第二晶粒上方，其中多個第三晶粒電耦接至多個第一晶粒及多個第二晶粒，且其中多個第三晶粒至少包括第三邏輯晶粒及第三記憶體晶粒；以及將電連接件形成於多個第一晶粒、多個第二晶粒以及多個第三晶粒上方並電耦接至多個第一晶粒、多個第二晶粒以及多個第三晶粒。
本發明實施例提供一種形成積體電路封裝件的方法，包括：置放多個第一層級晶粒；將多個第二層級晶粒接合至多個第一層級晶粒；填充第一間隙填充介電材料，其中第一間隙填充介電材料填充至多個第一層級晶粒之間的間隙及多個第二層級晶粒之間的間隙兩者中；形成穿透多個第二層級晶粒的多個第一穿孔，其中多個第一穿孔將多個第二層級晶粒電耦接至多個第一層級晶粒；將多個金屬接墊形成於第一間隙填充介電材料上方且電耦接至多個第一穿孔；形成覆蓋多個金屬接墊的介電層；將多個第三層級晶粒接合至介電層，其中多個第一層級晶粒、多個第二層級晶粒以及多個第三層級晶粒中的各層級至少包括邏輯晶粒及記憶體晶粒；以及形成穿透多個第三層級晶粒以電耦接至多個金屬接墊的多個第二穿孔。
本發明實施例提供一種積體電路封裝件，包括：多個第一晶粒、多個第二晶粒、第一介電層、多個第一穿孔、多個第一金屬接墊、第二介電層、多個第三晶粒以及多個第二穿孔。多個第一晶粒位於載體上方，其中多個第一晶粒至少包括第一邏輯晶粒及第一記憶體晶粒。多個第二晶粒位於多個第一晶粒上方，其中多個第二晶粒電耦接至多個第一晶粒，且其中多個第二晶粒至 少包括第二邏輯晶粒及第二記憶體晶粒。第一介電層位於多個第二晶粒上方。多個第一穿孔穿透第一介電層及多個第二晶粒，以電耦接至多個第一晶粒。多個第一金屬接墊位於多個第一穿孔上方且接觸多個第一穿孔。第二介電層覆蓋多個第一金屬接墊。多個第三晶粒位於第二介電層上方且接合至第二介電層。多個第二穿孔穿透第二介電層及多個第三晶粒，以電耦接至多個第一金屬接墊
20:半導體基底
22:內連線結構
24、24A、24B、24C、25、76、80:金屬接墊
26、26A、26B、26C:介電層
30、30-1、30-2、30-3、32、56、72、81:穿孔
38、38A、38B:介電區域
40、51、52:RDL
42、54:焊料區域
44:金屬柱
41、46、53:介電層
48:底膠
49:晶粒貼合膜
50、50A、50B:包封體
58:封裝基底
60:記憶體堆疊
62:記憶體晶粒
64:散熱特徵
66:金屬蓋
68:中介層
70:基底
74:載體
78、79、82:介電層
100、100A、100B、102、102'、104A、104B:記憶體內運算封裝件
202、203、204、206、208、210、212、214、216、218、220:製程
L、L1、L1'、L2、L2'、L3、L3A、L3B、L3C、L3D、L3E、L3F、L4、L4A、L4B、L4C、L4D、L4E、L4F:邏輯晶粒
M、M1、M2、M2'、M3、M3'、M4、M4'、M1A、M1B、M1C、M1D、M1E、M1F:記憶體晶粒
結合隨附圖式閱讀以下具體實施方式時會最佳地理解本發明的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，為論述清楚起見，可任意增加或減小各種特徵的尺寸。
圖1示出根據一些實施例的封裝件的橫截面視圖。
圖2、圖3以及圖4示出根據一些實施例的封裝件的三個層級的俯視圖。
圖5至圖12示出根據一些實施例的一些封裝件的橫截面視圖。
圖13至圖24示出根據一些實施例的併入有封裝件的系統的橫截面視圖。
圖25至圖31示出根據一些實施例的封裝件的形成中的中間階段的橫截面視圖。
圖32至圖39示出根據一些實施例的封裝件的形成中的中間階段的橫截面視圖。
圖40至圖44示出根據一些實施例的封裝件的形成中的中間階段的橫截面圖。
圖45示出根據一些實施例的用於形成的封裝件的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件以及配置的具體實例以簡化本揭露內容。當然，這些組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上之形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不指示所論述各種實施例及/或組態之間的關係。
另外，為易於描述，空間相對術語，諸如「在......下方」、「低於」、「在......下部」、「高於」、「在......上部」及其類似者，在本文中可用於描述如圖式中所示出的一個元件或特徵與另一元件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據各種實施例提供封裝件及其形成方法。根據一些實施例示出封裝件的形成的中間階段。論述一些實施例的一些變化。貫穿各種視圖及說明性實施例，相同的附圖標號用以指定相 同元件。根據本發明的一些實施例，形成記憶體內運算的封裝件。記憶體內運算的封裝件包含多個層級，其中所述多個層級中的每一者包含邏輯晶粒及記憶體晶粒兩者。層級中的邏輯晶粒可浸沒(immersed)在相同層或所述層級上方及/或下方的其他層級中的記憶體晶粒(且可為其他邏輯晶粒)中。類似地，層級中的記憶體晶粒可浸沒在相同層級或所述層級上方及/或下方的其他層級中的邏輯晶粒(且可為其他記憶體晶粒)中。藉由此設置，可提高運算效率，可增加系統的頻寬，且由於晶粒緊密靠近及高效的佈局可減少延遲。
圖1示出記憶體內運算封裝件100的橫截面視圖。根據本發明之的一些實施例，術語「記憶體內運算(compute-in-memory)」是指執行運算功能的邏輯晶粒浸沒在邏輯晶粒存取的記憶體晶粒中的結構。記憶體內運算封裝件100有時亦被稱作系統整合晶片(SoIC)封裝件。在圖1及後續圖式中，字母「L」用以表示對應的晶粒為邏輯晶粒，且字母「M」用以表示對應的晶粒為記憶體晶粒。邏輯晶粒L及記憶體晶粒M可後接數字以用於識別目的。應理解，圖1示出實例，且如圖1(及圖2至圖12)中所示的晶粒中的每一者在其他實施例中可為邏輯晶粒或記憶體晶粒。此外，取決於設計要求，在層級中的每一者中，邏輯晶粒的數目及記憶體晶粒的數目可為等於或大於1的任何數字。應理解，儘管將三個層級封裝件繪示為實例，但記憶體內運算封裝件可包含超過三個層級，諸如四個層級、五個層級或更多層級。
根據本發明的一些實施例，邏輯晶粒包含單核晶粒或多 核邏輯晶粒。邏輯晶粒可為應用程式處理器(Application Processor；AP)晶粒、圖形處理單元(Graphics Processing Unit；GPU)晶粒、現場可程式化邏輯閘陣列(Field Programmable Gate Array；FPGA)晶粒、特殊應用積體電路(Application Specific Integrated Circuit；ASIC)晶粒、輸入輸出(Input-Output；IO)晶粒、網路處理單元(Network Processing Unit；NPU)晶粒、張量處理單元(Tensor Processing Unit；TPU)晶粒、人工智慧(Artificial Intelligence；AI)引擎晶粒或類似晶粒。在記憶體內運算封裝件100中，及可能在層級中的每一者中，可混合不同類型的邏輯晶粒。
根據本發明的一些實施例，記憶體晶粒可包含靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)晶粒、寬I/O記憶體晶粒、NAND記憶體晶粒、電阻性隨機存取記憶體(Resistive Random Access Memory；RRAM)晶粒、磁阻式隨機存取記憶體(Magneto-resistive Random Access Memory；MRAM)晶粒或類似晶粒。記憶體晶粒中可包含或可不含控制器。記憶體晶粒亦可呈單個記憶體晶粒或預堆疊記憶立方體形式。在記憶體內運算封裝件100中，及可能在層級中的每一者中，可混合不同類型的記憶體晶粒。
再次參照圖1，根據一些實例實施例，具有層級1、層級1上方的層級2以及層級2上方的層級3。經由直接介電質接合(有時亦被稱作介電質對介電質接合或融合接合)或混合接合將相鄰層級彼此接合。混合接合包含介電質對介電質接合及金屬對金屬 接合兩者。層級中的每一者可包含一或多個邏輯晶粒L及一或多個記憶體晶粒M。邏輯晶粒L及記憶體晶粒M可包含半導體基底20，其可為矽基底。內連線結構22形成在對應的半導體基底20上且用於將對應的晶粒中的元件互連。此外，接合墊24可形成於內連線結構22內部或與對應晶粒L或晶粒M的表面共面。
穿孔30(包含穿孔30-1、穿孔30-2以及穿孔30-3)形成為穿透半導體基底20，且用以將(在不同層級或相同層級中的)晶粒L及晶粒M電性地及訊號地耦接在一起。穿孔30可以不同的方式使用，以將不同層級中的晶粒互連。舉例而言，組合使用穿孔30-1及穿孔30-2，以藉由金屬接墊76將邏輯晶粒L2中的金屬接墊(襯墊24A)與記憶體M3的金屬接墊(襯墊24B)互連，其中金屬接墊76位於穿孔30-1及穿孔30-2上方且接觸穿孔30-1及穿孔30-2。另一方面，穿孔30-3用以將邏輯晶粒L2中的金屬接墊24A與記憶體M3中的金屬接墊24B連接。穿透介電區域38的穿孔32用以藉由金屬接墊76將(在層級1中)記憶體晶粒M1連接至頂部金屬接墊80。
圖2示出層級1的俯視圖，其中示出實例佈局。舉例而言，實例實施例包含被邏輯晶粒L1、邏輯晶粒L2、邏輯晶粒L1'及邏輯晶粒L2'所包圍(浸沒於其中)的記憶體晶粒M1。如前所述，層級1(及如圖3中的層級2或如圖4中的層級3)的所示出佈局為實例，且所示出晶粒L及晶粒M中的每一者在其他實施例中亦可為邏輯晶粒或記憶體晶粒。根據一些實施例，記憶體晶粒M1為單一個記憶體晶粒。根據替代性實施例，所示出的記憶體晶粒M1表示多個記憶體晶粒。舉例而言，根據一些實施例，記憶體 晶粒M1A及記憶體晶粒M1B可置放在記憶體晶粒M1的位置。記憶體晶粒M1A及記憶體晶粒M1B可為相同類型的記憶體晶粒或可為不同類型的記憶體晶粒。根據替代性實施例，記憶體晶粒M1C、記憶體晶粒M1D、記憶體晶粒M1E以及記憶體晶粒M1F可置放在記憶體晶粒M1的位置。
圖3示出層級2的俯視圖，所述俯視圖包含被記憶體晶粒M2、記憶體晶粒M3、記憶體晶粒M2'以及記憶體晶粒M3'所包圍的邏輯晶粒L3。根據一些實施例，邏輯晶粒L3為單一個邏輯晶粒。根據替代性實施例，所示出的邏輯晶粒L3表示多個邏輯晶粒。舉例而言，根據一些實施例，邏輯晶粒L3A及邏輯晶粒L3B可置放在邏輯晶粒L3的位置。邏輯晶粒L3A及邏輯晶粒L3B可為相同類型的邏輯晶粒或可為不同類型的邏輯晶粒。根據替代性實施例，邏輯晶粒L3C、邏輯晶粒L3D、邏輯晶粒L3E以及邏輯晶粒L3F可置放在邏輯晶粒L3的位置。
圖4示出層級3的俯視圖，所述俯視圖包含在記憶體晶粒M4及記憶體晶粒M4'的側面上的邏輯晶粒L4。根據一些實施例，邏輯晶粒L4為單一個邏輯晶粒。根據替代性實施例，所示出的邏輯晶粒L4表示多個邏輯晶粒。舉例而言，根據一些實施例，邏輯晶粒L4A及邏輯晶粒L4B可置放在邏輯晶粒L4的位置。邏輯晶粒L4A及邏輯晶粒L4B可為相同類型的邏輯晶粒或可為不同類型的邏輯晶粒。根據替代性實施例，邏輯晶粒L4C、邏輯晶粒L4D、邏輯晶粒L4E以及邏輯晶粒L4F可置放在邏輯晶粒L4的位置。
圖5至圖12示出根據一些實施例的記憶體內運算封裝件 的橫截面視圖。這些實施例包含邏輯晶粒L及記憶體晶粒M的配置的不同組合，其中不同層級中的晶粒L及晶粒M可以配置為面向上方或面向下方，且相鄰層級之間的接合可為面對背(face-to-back)接合或面對面(face-to-face)接合。這些實施例亦包含不同類型的接合方法，包含直接介電質接合及混合接合。此外，記憶體內運算封裝件的界面可包含重佈線(Redistribution Line；RDL)及焊料區域，或替代地包含金屬柱。RDL及焊料區域可以用於覆晶接合，且金屬柱可以用於形成整合扇出型(Integrated Fan-out；InFO)封裝件。應理解，圖5至圖12示出一些實施例組合，且本揭露涵蓋其他組合。圖5至圖12中繪示的實施例亦在如圖25至圖44中所繪示的製程中詳細論述。
參照圖5，記憶體內運算封裝件100包含在層級1中面向上方置放的晶粒。在整個實施方式中，當晶粒被稱為面向上方時，其意謂元件(例如，諸如電晶體的主動元件，或諸如電阻器、電容器或類似物的被動元件)朝向晶粒中的相應的半導體基底的上表面且面向上方。同樣地，當晶粒被稱為面向下方時，其意謂元件為朝向晶粒中的相應的基底的上表面且面向下方。層級2的晶粒(亦可稱為第二層級晶粒)，例如晶粒M2、晶粒L3以及晶粒M3面向下方置放，且經由直接介電質接合以及經由面對面接合接合至下方的層級1的晶粒(亦可稱為第一層級晶粒)。層級3的晶粒L4及晶粒M4(亦可稱為第三層級晶粒)面向下方置放，且經由直接介電質接合接合至層級2中的介電層78。層級3的晶粒L4及晶粒M4經由面對背接合接合至下方的層級2的晶粒。RDL 40形成於層級3晶粒的上方，且藉由穿孔及金屬接墊電連接至層級1 的晶粒、層級2的晶粒以及層級3的晶粒。焊料區域42形成於RDL 40上方且電耦接至RDL 40。焊料區域42可用於經由覆晶接合將記憶體內運算封裝件100接合至其他結構。
圖6示出根據一些實施例的記憶體內運算封裝件100。除了在層級3的晶粒L4及晶粒M4上方形成金屬柱44之外，這些實施例類似於圖5中的實施例。金屬柱44可由銅、銅合金或其他類似金屬形成。介電層46形成為嵌入有金屬柱44，且介電層46的上表面可與金屬柱44的上表面共面。介電層46可由諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene；BCB)或類似物的聚合物形成。介電層46亦可由諸如氧化物(例如，氧化矽或氮氧化矽)的無機介電材料形成。
圖7示出根據一些實施例的記憶體內運算封裝件100。除了相鄰層級之間的接合是混合接合而非直接介電質接合之外，這些實施例類似於圖5中的實施例。舉例而言，晶粒L1及晶粒M2經由混合接合彼此接合，所述接合包含金屬接墊24A與金屬接墊24B之間的金屬對金屬接合，及晶粒L1中的表面介電層26A與晶粒M2中的表面介電層26B之間的介電質對介電質接合。此外，晶粒M4經由混合接合接合至下方的介電層78及金屬接墊76，所述接合包含介電層78與晶粒M4中的表面介電層26C之間的接合，及晶粒M4中的金屬接墊24C與金屬接墊76之間的接合。在記憶體內運算封裝件100中，RDL 40及焊料區域42經形成用於將記憶體內運算封裝件100接合至其他封裝件組件。
圖8示出根據一些實施例的記憶體內運算封裝件100。除 了在層級3的晶粒L4及晶粒M4上方形成金屬柱44之外，這些實施例類似於圖7中的實施例。金屬柱44可由銅、銅合金或其他類似金屬形成。在記憶體內運算封裝件100中，金屬柱44出於接合目的形成於介電層46中，且金屬柱44的上表面與介電層46的上表面共面。
圖9示出根據一些實施例的記憶體內運算封裝件100。除了晶粒以反向順序置放，以使層級1包含晶粒L4及晶粒M4且層級3的晶粒包含晶粒L1、晶粒M2以及晶粒L2之外，這些實施例類似於圖5中的實施例。然而，應意識到，層級1的晶粒亦可包含如前述的實施例中所繪示的晶粒L1、晶粒M1以及晶粒L2(而非晶粒L4及晶粒M4)，且層級3的晶粒亦可包含晶粒L4及晶粒M4(而非晶粒L1、晶粒M1以及晶粒L2)。層級1的晶粒(例如邏輯晶粒L4及記憶體晶粒M4)面向下方置放，且層級2的晶粒(例如邏輯晶粒L3、記憶體晶粒M2以及記憶體晶粒M3)至層級1的晶粒L4及晶粒M4的接合是面對背接合，所述接合經由直接介電質接合實現。舉例而言，接合晶粒L3、晶粒M2以及晶粒M3經由直接介電質接合至下方的介電層38A。此外，層級3的晶粒L1、晶粒M1以及晶粒L2經由面對背接合且經由直接介電質接合接合至層級2的晶粒。在如圖9中所繪示的記憶體內運算封裝件100中，RDL 40及焊料區域42經形成用於將記憶體內運算封裝件100接合至其他封裝件組件。
圖10示出根據一些實施例的記憶體內運算封裝件100。除了在層級3的晶粒L1、晶粒M1以及晶粒L2上方，金屬柱44出於接合目的形成於介電層46中，且金屬柱44的上表面與介電 層46的上表面共面之外，這些實施例類似於圖9中的實施例。
圖11示出根據一些實施例的記憶體內運算封裝件100。除了層級1的晶粒(例如邏輯晶粒L4及記憶體晶粒M4)面向下方置放，且層級2的晶粒(例如邏輯晶粒L3、記憶體晶粒M2以及記憶體晶粒M3)至層級1的晶粒的接合是經由混合接合，所述接合根據一些實施例是面對背接合之外，這些實施例類似於圖9中的實施例。此外，層級3的晶粒(諸如晶粒L1、晶粒M1以及晶粒L2)亦經由面對背接合且經由混合接合接合至層級2的晶粒。在記憶體內運算封裝件100中，RDL 40及焊料區域42經形成用於將記憶體內運算封裝件100接合至其他封裝件組件。
圖12示出根據一些實施例的記憶體內運算封裝件100。除了在層級3的晶粒L1、晶粒M1以及晶粒L2上方，金屬柱44出於接合目的形成於介電層46中，且金屬柱44的上表面與介電層46的上表面共面之外，這些實施例類似於圖11中的實施例。
如圖5至圖12中所繪示封裝件100形成為重建構晶圓，所述重建構晶圓包含具有圖5至圖12中的一者繪示的結構的多個封裝件。對應的晶圓接著經切割以使如圖5至圖12中的一者所繪示的封裝件形成為離散的封裝件100。
圖13至圖24示出一些實例實施例，以繪示記憶體內運算封裝件100如何用於形成較大封裝件或系統。根據實施例中的一些，如圖5至圖12中所繪示的記憶體內運算封裝件100類似於元件晶粒的用途來使用。如圖13至圖24中所繪示的記憶體內運算封裝件100的細節未示出，則可參考繪示於圖5至圖12中的實施例得到。記憶體內運算封裝件100的表面接合結構，所述接合 結構取決於是否使用覆晶接合或InFO結構以指示是否採用焊料區域或金屬柱。此外，用於連接至焊料區域及/或金屬柱的一些接合墊及RDL未示出，然而這些接合墊及RDL確實存在於封裝件中。當多於一個記憶體內運算封裝件100存在於相同封裝件中時，字母「A」或字母「B」可添加至附圖標號「100」以識別個別封裝件100。
圖13示出記憶體內運算封裝件100A及記憶體內運算封裝件100B的面對背接合。接合是經由覆晶接合，其中底膠48安置於記憶體內運算封裝件100A與記憶體內運算封裝件100B之間。所得封裝件102具有金屬柱44位於其表面處。因此，封裝件102可用於形成InFO封裝件。
圖14示出封裝件102，所述封裝件包含經由覆晶接合接合至封裝件104B的兩個封裝件104A。封裝件104A及封裝件104B是InFO封裝件。根據本發明的一些實施例，InFO封裝件104A的形成包含經由晶粒貼合膜49(黏著膜)將對應的記憶體內運算封裝件100A置放在載體(未繪示)上方，將記憶體內運算封裝件100A包封在諸如模製化合物的包封體50A中，執行平坦化以使記憶體內運算封裝件100A中的金屬柱44的表面(所示出的底表面)與包封體50A的表面齊平，且接著形成RDL 52及焊料區域54。除了在使用包封體50B之前形成額外穿孔56之外，類似地形成封裝件104B。如圖14中所繪示的封裝件102可以用於覆晶接合。
圖15示出封裝件上晶片(chip-on-package)結構，其中首先將記憶體內運算封裝件100B用於形成InFO封裝件104B，隨後經由覆晶接合將記憶體內運算封裝件100A(用作晶片)接合至 InFO封裝件104B。接著點膠包封體50A以將記憶體內運算封裝件100A包封於其中。如圖15中所繪示的封裝件102可以用於覆晶接合。RDL 51形成為封裝件104B的一部分。RDL 51的細節未示出。
圖16示出封裝件102，所述封裝件是基於記憶體內運算封裝件100形成的InFO封裝件。形成製程已參照圖14中的封裝件104A描述，於此便不再贅述細節。用於形成如16圖中所繪示的封裝件102的封裝製程是RDL最後形成(RDL-last)製程，其中記憶體內運算封裝件100首先包封在包封體50中，且RDL 52及對應的介電層53的形成在將記憶體內運算封裝件100包封在包封體50中之後執行。
圖17示出封裝件102，所述封裝件是基於記憶體內運算封裝件100形成的覆晶封裝件。用於形成如16圖中所繪示的封裝件102的封裝製程是RDL優先形成(RDL-first)製程，其中首先形成RDL 52及對應的介電層53，且經由覆晶接合將記憶體內運算封裝件100接合至RDL 52。接著將記憶體內運算封裝件100包封在包封體50中。
圖18示出封裝件102'，所述封裝件包含如16圖中所繪示的接合至封裝基底58的封裝件102。封裝基底58可為無核心基底。替代地，封裝基底58包含核心，且RDL在所述核心的相對側上形成。底膠48安置於封裝件102與封裝基底58之間。
圖19示出封裝件102，所述封裝件是基於記憶體內運算封裝件100形成的InFO封裝件。形成製程已參照圖14中的封裝件104B描述，於此便不再贅述細節。用於形成如19圖中所繪示 的封裝件102的封裝製程亦是RDL最後形成製程。
圖20示出封裝件102'，所述封裝件包含記憶體內運算封裝件100及形成InFO封裝件的記憶體堆疊(立方體)60。記憶體堆疊60中的每一者包含互相堆疊且互相電耦接的多個記憶體晶粒62。記憶體堆疊60可為高頻寬記憶體(High Bandwidth Memory；HBM)立方體。記憶體堆疊60及記憶體內運算封裝件100是包封在包封體50中。RDL 52形成以連接至記憶體堆疊60及記憶體內運算封裝件100。根據本發明的一些實施例，對應的封裝件為高效能封裝件。因此，散熱特徵64及金屬蓋66可形成以連接至記憶體內運算封裝件100。散熱特徵64可為金屬棒、金屬鰭或類似物。InFO封裝件進一步接合至封裝基底58。
圖21示出根據本揭露的一些實施例的封裝件102'。除了示出兩個記憶體內運算封裝件100之外，這些實施例類似於如20圖中所繪示的實施例。應理解，儘管示出兩個記憶體內運算封裝件100，但可能存在更多(例如四個、六個、八個等)的記憶體內運算封裝件100。類似地，雖然在圖20及圖21中示出兩個記憶體堆疊60，但在對應封裝件102'中可能存在更多(例如四個、六個、八個等)記憶體堆疊60。
圖22示出根據本揭露的一些實施例的封裝件102'。除了記憶體內運算封裝件100接合至中介層68，而不是將RDL 52(圖20)形成於經包封記憶體內運算封裝件100上，這些實施例類似於如20圖中所繪示的實施例。中介層68包含基底70，所述基底可為半導體基底(例如矽基底)及穿透基底70的穿孔72。RDL形成於基底70的相對側上且經由穿孔72互連。
圖23示出根據本揭露的一些實施例的封裝件102'。除了示出兩個運算記憶體封裝件100之外，封裝件102'類似於圖22中所繪示的實施例。
圖24示出根據本發明的一些實施例的封裝件102'，其中記憶體內運算封裝件100經由覆晶接合接合至封裝基底58。底膠48安置於記憶體內運算封裝件100與封裝基底58之間的間隙中。包封體50包封在記憶體內運算封裝件100上。
圖25至圖31示出根據本發明的一些實施例的如圖5中所繪示的記憶體內運算封裝件100的形成中的中間階段的橫截面視圖。對應製程亦示意性地反映於圖45中所繪示的製程流程中。
參照圖25，諸如邏輯晶粒L1及邏輯晶粒L2以及記憶體晶粒M1的層級1的晶粒置放於載體74上，例如，經由晶粒貼合膜(未繪示)。相應的製程被示為圖45中所示的製程流程中的製程202。層級1的晶粒的前側面向上方。在層級1的晶粒中的金屬接墊24A被對應的介電層26A所覆蓋。根據本發明的一些實施例，介電層26A由諸如氧化矽、氮氧化矽、矽碳氮化物或類似物的氧化物形成。接著，藉由另外的表面平坦化製程將介電膜38A填充至層級1的晶粒L1、晶粒L2以及晶粒M1之間的間隙。介電膜可由氧化物(諸如氧化矽)、SiCN、SiN、SiOC或類似物形成。相應的製程被示為圖45中所示的製程流程中的製程203。
接著，如26圖中所繪示，層級2的晶粒(諸如邏輯晶粒L3及記憶體晶粒M2以及記憶體晶粒M3)經由直接介電質接合接合至層級1的晶粒L1、晶粒L2以及晶粒M1，其中介電層26B藉由融合接合接合至相應的介電層26A。相應的製程被示為圖45中 所示的製程流程中的製程204。一些晶粒(諸如晶粒M3)可接合至多於一個晶粒(諸如晶粒M1及晶粒L2)。根據一些實施例，晶粒M3及晶粒M1之間不存在直接電連接。然而，由於將晶粒M3接合至晶粒L2及晶粒M1兩者上，所以改善了接合穩定性。在接合之後，可薄化層級2的晶粒。
接著，如圖27中所繪示，執行間隙填充製程，且介電區域38B經形成以填充如圖26中所繪示的間隙。相應的製程被示為圖45中所示的製程流程中的製程206。間隙填充可使用可適用的方法執行，包含且不限於化學氣相沈積(Chemical Vapor Deposition；CVD)、旋轉塗佈、可流動化學氣相沈積(Flowable Chemical Vapor Deposition；FCVD)或類似方法。介電區域38B可由氧化物(諸如氧化矽)、SiCN、SiN、SiOC或類似物形成。平坦化製程，諸如化學機械研磨(Chemical Mechanical Polish；CMP)或機械研磨製程可經執行以使介電區域38B的上表面平整。根據替代性實施例，層級1的晶粒及層級2的晶粒在相同包封製程中被包封，其中介電區域38A及介電區域38B形成連續性介電區域，所述連續介電區域稱為介電區域38。
圖28進一步示出穿孔30(包含穿孔30-1、穿孔30-2以及穿孔30-3)的形成，所述穿孔穿透層級2的晶粒中的介電區域38及基底(諸如矽基底或其他類型的半導體基底)以電耦接至金屬接墊24A。相應的製程被示為圖45中所示的製程流程中的製程208。因此，層級1的晶粒電耦接至層級2的晶粒。金屬接墊24B至對應金屬接墊24A的電耦接可經由單一個穿孔30-3或經由兩個穿孔30-1及穿孔30-2。穿孔32亦形成為穿透介電區域38且連接 至金屬接墊24A。金屬接墊76形成於介電區38的上表面上，且電連接至層級1的晶粒及層級2的晶粒。相應的製程被示為圖45中所示的製程流程中的製程210。
圖29示出介電層78的沈積及平坦化，所述介電層可由諸如氧化矽、SiOC、SiCN、SiN或類似物的氧化物形成。相應的製程被示為圖45中所示的製程流程中的製程212。金屬接墊76因此由介電層78覆蓋。接著，如圖30中所繪示，諸如邏輯晶粒L4及記憶體晶粒M4的層級3的晶粒接合至介電層78。相應的製程被示為圖45中所示的製程流程中的製程214。層級3的晶粒的表面介電層26C經由直接介電質接合接合至介電層78。接著，層級3的晶粒L4及晶粒M4例如在CMP製程或機械研磨製程中變薄。接著沈積介電層79，以包封層級3的晶粒，繼之以平坦化製程。形成穿孔81以穿透層級3的晶粒中的基底及介電層79的頂部。接著形成金屬接墊80在介電層79的表面上且連接至穿孔81。相應的製程被示為圖45中所示的製程流程中的製程216。接著，沈積及平坦化介電層82。相應的製程被示為圖45中所示的製程流程中的製程218。在平坦化之後，金屬接墊80可外露於介電質82或繼續被介電質82覆蓋。
圖31示出RDL 40、介電層41以及焊料區域42的形成。相應的製程被示為圖45中所示的製程流程中的製程220。RDL 40及焊料區域42電連接至下方的層級1的晶粒、層級2的晶粒以及層級3的晶粒。圖5中亦繪示所得結構。接著剝離載體74(圖30)且執行單體化製程以形成多個彼此相同的封裝件100。除了形成金屬柱44及介電層46之外，圖6中所繪示的結構可形成於類似製 程中。
圖32至圖39示出根據本發明的一些實施例的如圖7中所繪示的記憶體內運算封裝件100的形成中的中間階段的橫截面視圖。除非另有說明，否則在圖32至圖39(且在圖40至圖44中)中的組件的材料及形成製程與圖25至圖31中所繪示實施例中的以相似附圖標號所表示的類似組件基本上相同。關於圖32至圖44中所繪示的組件的形成製程以及材料的細節可因此在對圖25至圖31中所繪示的實施例的論述中找到。
參照圖32，諸如邏輯晶粒L1及邏輯晶粒L2以及記憶體晶粒M1的層級1的晶粒置放於載體74上，例如，經由晶粒貼合膜(未繪示)。層級1的晶粒的前側面向上方。接著，使用另一表面平坦化製程，以介電膜38A填充層級1的晶粒L1、晶粒L2以及晶粒M1之間的間隙。介電膜可由氧化物(諸如氧化矽)、SiCN、SiN、SiOC或類似物形成。層級1的晶粒中的金屬接墊24A被暴露且與對應表面介電層26A共面。
接著，如圖33中所繪示，諸如邏輯晶粒L3及記憶體晶粒M2以及記憶體晶粒M3的層級2的晶粒經由混合接合接合至層級1的晶粒L1、晶粒M1以及晶粒L2，其中層級2的晶粒中的介電層26B接合至層級1晶粒中的介電層26A，且金屬接墊24B接合至金屬接墊24A。然後可薄化層級2的晶粒。接著，如圖34中所繪示，執行間隙填充製程，且形成介電區域38B以填充如圖34中所繪示的間隙。可執行諸如化學機械研磨或機械研磨製程的平坦化製程，以使介電區域38B的上表面平整。根據替代性實施例，層級1的晶粒及層級2的晶粒在相同包封製程中包封，其中介電 區域38A及介電區域38B形成連續性介電區域，所述連續介電區域稱為介電區域38。
圖35示出穿孔30及穿孔32的形成。穿孔30中的一些電連接至接合墊24B，所述穿孔30中的一些進一步連接至接合墊24A。穿孔30中的一些直接連接至接合墊24A。穿孔32亦形成為穿透介電區38且連接至金屬接墊24A。金屬接墊76形成於介電區域38的頂部上且電連接至層級1晶粒及層級2晶粒。
圖35進一步示出介電層78的沈積及平坦化。金屬接墊76顯示為平坦化的結果且具有與介電層78的上表面共面的頂表面。接著，如圖36中所繪示，諸如邏輯晶粒L4及記憶體晶粒M4的層級3的晶粒經由混合接合接合至介電層78及金屬接墊76。接著，層級3的晶粒L4及晶粒M4例如在CMP製程或機械研磨製程中變薄。
參照圖37，沈積且平坦化介電層82。如圖38中所繪示，接著形成穿孔81及金屬接墊80。接著，形成且平坦化介電層82。在所得結構中，在平坦化之後，金屬接墊80可外露於介電質82或繼續被介電質82覆蓋。
圖39示出RDL 40、介電層41以及焊料區域42的形成。RDL 40及焊料區域42電連接至下方的層級1的晶粒、層級2的晶粒以及層級3的晶粒。圖7中亦繪示所得結構。接著剝離載體74(圖38)，且執行單體化製程以形成多個與彼此相同的封裝件100。除了形成金屬柱44及介電層46之外，圖8中所繪示的結構可形成於類似製程中。
圖40至圖44示出根據本發明的一些實施例的如圖9中 所繪示的記憶體內運算封裝件100的形成中的中間階段的橫截面視圖。根據一些實施例，雖然層級1的晶粒為晶粒L4及晶粒M4，但根據替代性實施例，層級1的晶粒亦可為晶粒L1、晶粒M1以及晶粒L2。
參照圖40，諸如邏輯晶粒L4及記憶體晶粒M4的層級1的晶粒置放於載體74上，例如，經由晶粒貼合膜(未繪示)。層級1的晶粒的前側面向下方。金屬接墊25形成於對應半導體基底20的背面上，其中穿孔81使金屬接墊25及金屬接墊24C互連。為避免銅擴散至矽基底中，介電質絕緣薄膜(未繪示)沈積在金屬接墊25與矽基底之間且填充環繞穿孔81周圍。接著，如圖41中所繪示，形成介電區域38A以將層級1的晶粒包封於其中並接著平坦化。介電區域38A可由諸如氧化矽或SiON的氧化物形成。
接著，如42圖中所繪示，諸如邏輯晶粒L3及記憶體晶粒M2以及記憶體晶粒M3的層級2的晶粒經由直接介電質接合接合至介電區域38A，其中層級2的晶粒中的介電層26B接合至介電區域38A。可接著薄化層級2的晶粒，繼之以形成穿孔33。接著，亦如圖42中所繪示，執行間隙填充製程，且形成介電區域38B以填充在層級2的晶粒L3、晶粒M2以及晶粒M3之間的間隙，其中介電區域38B的一部分與層級2的晶粒L3、晶粒M2以及晶粒M3重疊。諸如化學機械研磨或機械研磨製程的平坦化製程可經執行以使介電區域38B的上表面平整。
圖42亦示出金屬接墊76形成在介電區域38B的上表面上並沈積及平坦化介電層78。金屬接墊76由介電層78覆蓋。
接著，如圖43中所繪示，諸如邏輯晶粒L1及邏輯晶粒 L2以及記憶體晶粒M1的層級3的晶粒經由直接介電質接合接合至介電層78。接著，例如在CMP製程或機械研磨製程中薄化層級3的晶粒。接著，沈積且平坦化介電層79。
進一步參照圖43，形成穿孔30，且形成金屬接墊80以連接至穿孔30。金屬接墊80形成於介電層79上且與穿孔30接觸。接著，形成且平坦化介電層82。在所得結構中，在平坦化之後，金屬接墊80可外露於介電質82或繼續被介電質82覆蓋。
圖44示出RDL 40、介電層41以及焊料區域42的形成。RDL 40及焊料區域42電連接至下方的層級1的晶粒、層級2的晶粒以及層級3的晶粒。圖9中亦繪示所得結構。接著剝離載體74(圖43)，且執行單體化製程以形成多個與彼此相同的封裝件100。除了形成金屬柱44及介電層46之外，圖10中所繪示的結構可形成於類似製程中。
用於形成繪示於圖11及圖12中的結構的製程流程可經由如圖25至圖44中所繪示的製程實現，且在本文中未示出。
在上文所示出的實施例中，一些製程及特徵根據本揭露內容的一些實施例來論述。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝件或3DIC元件的驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試襯墊，所述基底允許測試3D封裝件或3DIC、使用探針及/或探針卡以及其類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可與併入有對已知良好晶粒的中間驗證的測試方法結合使用，以提高產率及降低成本。
本揭露的實施例具有一些有利特徵。藉由將邏輯晶粒浸 沒在記憶體晶粒中且將記憶體晶粒浸沒在邏輯晶粒中，可提高運算效率，且可增加系統的頻寬，且由於晶粒緊密靠近及高效的佈局可減少延遲。
根據本揭露的一些實施例，形成積體電路封裝件的方法包含將多個第一晶粒置放在載體上方，其中多個第一晶粒至少包括第一邏輯晶粒及第一記憶體晶粒；將多個第二晶粒置放在多個第一晶粒上方，其中多個第二晶粒電耦接至多個第一晶粒，且其中多個第二晶粒至少包括第二邏輯晶粒及第二記憶體晶粒；將多個第三晶粒置放在多個第二晶粒上方，其中多個第三晶粒電耦接至多個第一晶粒及多個第二晶粒，且其中多個第三晶粒至少包括第三邏輯晶粒及第三記憶體晶粒；以及將電連接件形成於多個第一晶粒、多個第二晶粒以及多個第三晶粒上方且電耦接至多個第一晶粒、多個第二晶粒以及多個第三晶粒。在一實施例中，所述方法更包含經由直接介電質接合將多個第二晶粒接合至多個第一晶粒。在一實施例中，所述方法更包含經由混合接合將多個第二晶粒接合至多個第一晶粒。在一實施例中，所述方法更包含填充第一介電材料，其中第一介電材料連續延伸至多個第一晶粒之間的間隙及多個第二晶粒之間的間隙，其中第一介電材料的一部分覆蓋多個第二晶粒；在第一介電材料上方形成金屬接墊；形成第二介電材料以覆蓋金屬接墊；以及經由介電質至介電質接合將多個第三晶粒接合至第二介電材料。在一實施例中，多個第二晶粒中的一者以物理方式接合至多個第一晶粒中的第一者及第二者兩者。在一實施例中，所述方法更包含形成以物理方式將多個第二晶粒中的一者連接至多個第一晶粒中的第一者的穿孔，且多個第 二晶粒中的一者與多個第一晶粒中的第二者之間不存在直接的電連接。在一實施例中，形成電連接件包括形成焊料區域。在一實施例中，形成電連接件包括：在多個第三晶粒上方形成介電層；以及在介電層中形成金屬柱，其中金屬柱的上表面與所述介電層的頂表面共面。在一實施例中，所述方法更包含執行晶粒切割以形成多個封裝件，其中多個第一晶粒、多個第二晶粒以及多個第三晶粒在多個封裝件中的一者中。在一實施例中，所述方法更包含經由覆晶接合將多個封裝件中的一個接合至封裝件組件；以及將多個封裝件中的一者包封在包封體中。在一實施例中，所述方法更包含將多個封裝件中的一者包封在包封體中；以及形成上覆多個封裝件中的一者及包封體兩者的重佈線及介電層。
根據本發明的一些實施例，形成積體電路封裝件的方法包含置放第一層級晶粒；將第二層級晶粒接合至第一層級晶粒；填充第一間隙填充介電材料，其中第一間隙填充介電材料填充至第一層級晶粒之間的間隙及第二層級晶粒之間的間隙兩者中；形成穿透第二層級晶粒的第一穿孔，其中第一穿孔將第二層級晶粒電耦接至第一層級晶粒；將金屬接墊形成於第一間隙填充介電材料上方且電耦接至第一穿孔；形成覆蓋金屬接墊的介電層；將第三層級晶粒接合至所述介電層，其中第一層級晶粒、第二層級晶粒以及第三層級晶粒中的各層級包括至少邏輯晶粒及記憶體晶粒；以及形成穿透第三層級晶粒以電耦接至金屬接墊的第二穿孔。在一實施例中，第一穿孔包括終止於第二層級晶粒中的一者的第一穿孔，以及終止於第一層級晶粒中的一者的第二穿孔。在一實施例中，第二層級晶粒經由混合接合接合至第一層級晶粒。 在一實施例中，第一穿孔中的一者穿透在第二層級晶粒中的金屬接墊以著陸在第一層級晶粒中的一者上的金屬接墊上。
根據本發明的一些實施例，積體電路封裝件包含在載體上方的多個第一晶粒，其中多個第一晶粒至少包括第一邏輯晶粒及第一記憶體晶粒；在多個第一晶粒上方的多個第二晶粒，其中多個第二晶粒電耦接至多個第一晶粒，且其中多個第二晶粒至少包括第二晶粒及第二記憶體晶粒；在多個第二晶粒上方的第一介電層；第一穿孔穿透第一介電層及多個第二晶粒以電耦接至多個第一晶粒；第一金屬接墊位於第一穿孔上方且接觸第一穿孔；第二介電層覆蓋第一金屬接墊；多個第三晶粒位於第二介電層上方且接合至第二介電層；以及第二穿孔穿透第二介電層及多個第三晶粒以電耦接至第一金屬接墊。在一實施例中，積體電路封裝件更包含在第二穿孔的上方且以物理方式連接至第二穿孔的第二金屬接墊。在一實施例中，多個第二晶粒的表面介電層經由直接介電質接合接合至多個第一晶粒的表面介電層，其中多個第二晶粒經由第一穿孔電耦接至多個第一晶粒。在一實施例中，第一穿孔包括以物理方式接觸多個第二晶粒中的一者中的金屬接墊及多個第一晶粒中的一者中的金屬接墊的穿孔。在一實施例中，多個第二晶粒的表面介電層接合至多個第一晶粒的表面介電層，且多個第二晶粒的接合墊接合至多個第一晶粒的接合墊。
前文概述若干實施例的特徵，以使得在所屬領域的技術人員可較好地理解本揭露內容的態樣。所屬領域的技術人員應瞭解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優勢的其他製程及結構的 基礎。所屬領域的技術人員亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且所屬領域中的技術人員可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
20:半導體基底
22:內連線結構
24、24A、24B、76、80:金屬接墊
30、30-1、30-2、30-3、32:穿孔
38:介電區域
100:記憶體內運算封裝件
M、M1、M2、M3、M4:記憶體晶粒
L、L1、L2、L3、L4:邏輯晶粒

Claims (9)

  1. 一種形成積體電路封裝件的方法，所述方法包括：將多個第一晶粒置放在載體上方，其中所述多個第一晶粒至少包括第一邏輯晶粒及第一記憶體晶粒；將多個第二晶粒置放在所述多個第一晶粒上方，其中所述多個第二晶粒電耦接至所述多個第一晶粒，且其中所述多個第二晶粒至少包括第二邏輯晶粒及第二記憶體晶粒；填充第一介電材料，其中所述第一介電材料連續延伸至所述多個第一晶粒之間的間隙及所述多個第二晶粒之間的間隙中，其中所述第一介電材料的一部分覆蓋所述多個第二晶粒；在所述第一介電材料上方形成金屬接墊；形成第二介電材料以覆蓋所述金屬接墊；經由介電質對介電質接合將多個第三晶粒接合至所述第二介電材料，以使所述多個第三晶粒置放在所述多個第二晶粒上方，其中所述多個第三晶粒電耦接至所述多個第一晶粒及所述多個第二晶粒，且其中所述多個第三晶粒至少包括第三邏輯晶粒及第三記憶體晶粒；以及將電連接件形成於所述多個第一晶粒、所述多個第二晶粒以及所述多個第三晶粒上方並電耦接至所述多個第一晶粒、所述多個第二晶粒以及所述多個第三晶粒。
  2. 如申請專利範圍第1項所述的形成積體電路封裝件的方法，其中所述多個第二晶粒中的一者以物理方式接合至所述多個第一晶粒中的第一者及第二者兩者。
  3. 如申請專利範圍第2項所述的形成積體電路封裝件的 方法，更包括形成以物理方式將所述多個第二晶粒中的所述一者連接至所述多個第一晶粒中的所述第一者的穿孔，且所述多個第二晶粒中的所述一者與所述多個第一晶粒中的所述第二者之間不存在直接的電連接。
  4. 如申請專利範圍第1項所述的形成積體電路封裝件的方法，更包括：執行晶粒切割以形成多個封裝件，其中所述多個第一晶粒、所述多個第二晶粒以及所述多個第三晶粒位於所述多個封裝件中的一者中。
  5. 一種形成積體電路封裝件的方法，所述方法包括：置放多個第一層級晶粒；將多個第二層級晶粒接合至所述多個第一層級晶粒；填充第一間隙填充介電材料，其中所述第一間隙填充介電材料填充至所述多個第一層級晶粒之間的間隙及所述多個第二層級晶粒之間的間隙兩者中；形成穿透所述多個第二層級晶粒的多個第一穿孔，其中所述多個第一穿孔將所述多個第二層級晶粒電耦接至所述多個第一層級晶粒；將多個金屬接墊形成於所述第一間隙填充介電材料上方且電耦接至所述多個第一穿孔；形成覆蓋所述多個金屬接墊的介電層；將多個第三層級晶粒接合至所述介電層，其中所述多個第一層級晶粒、所述多個第二層級晶粒以及所述多個第三層級晶粒中的各層級至少包括邏輯晶粒及記憶體晶粒；以及 形成穿透所述多個第三層級晶粒以電耦接至所述多個金屬接墊的多個第二穿孔。
  6. 如申請專利範圍第5項所述的形成積體電路封裝件的方法，其中所述多個第一穿孔包括終止於所述多個第二層級晶粒中的一者的第一穿孔，以及終止於所述多個第一層級晶粒中的一者的第二穿孔。
  7. 如申請專利範圍第5項所述的形成積體電路封裝件的方法，其中所述多個第一穿孔中的一者穿透所述第二層級晶粒中的金屬接墊，以著陸在所述多個第一層級晶粒中的一者上的金屬接墊上。
  8. 一種積體電路封裝件，包括：多個第一晶粒位於載體上方，其中所述多個第一晶粒至少包括第一邏輯晶粒及第一記憶體晶粒；多個第二晶粒位於所述多個第一晶粒上方，其中所述多個第二晶粒的多個表面介電層經由直接介電質接合接合至所述多個第一晶粒的多個表面介電層，其中所述多個第二晶粒電耦接至所述多個第一晶粒，且其中所述多個第二晶粒至少包括第二邏輯晶粒及第二記憶體晶粒；第一介電層位於所述多個第二晶粒上方；多個第一穿孔穿透所述第一介電層及所述多個第二晶粒，以電耦接至所述多個第一晶粒；多個第一金屬接墊位於所述多個第一穿孔上方且接觸所述多個第一穿孔；第二介電層覆蓋所述多個第一金屬接墊； 多個第三晶粒位於所述第二介電層上方且接合至所述第二介電層；以及多個第二穿孔穿透所述第二介電層及所述多個第三晶粒，以電耦接至所述多個第一金屬接墊。
  9. 如申請專利範圍第8項所述的積體電路封裝件，其中所述多個第一穿孔包括以物理方式接觸所述多個第二晶粒中的一者中的金屬接墊及所述多個第一晶粒中的一者中的金屬接墊的穿孔。
TW108136454A 2018-10-10 2019-10-08 積體電路封裝件及其形成方法 TWI727454B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862743693P 2018-10-10 2018-10-10
US62/743,693 2018-10-10
US16/529,235 2019-08-01
US16/529,235 US11171076B2 (en) 2018-10-10 2019-08-01 Compute-in-memory packages and methods forming the same

Publications (2)

Publication Number Publication Date
TW202018831A TW202018831A (zh) 2020-05-16
TWI727454B true TWI727454B (zh) 2021-05-11

Family

ID=70159653

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108136454A TWI727454B (zh) 2018-10-10 2019-10-08 積體電路封裝件及其形成方法

Country Status (3)

Country Link
US (1) US11171076B2 (zh)
KR (1) KR102308487B1 (zh)
TW (1) TWI727454B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US11990449B2 (en) * 2019-01-14 2024-05-21 Intel Corporation Dual RDL stacked die package using vertical wire
US11101240B2 (en) 2019-06-28 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation bonding film for semiconductor packages and methods of forming the same
KR102673730B1 (ko) * 2019-11-07 2024-06-10 삼성전자주식회사 반도체 소자 및 이를 구비한 반도체 패키지
DE102020128855A1 (de) * 2020-05-21 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets-3d-soic-systemintegrations- und herstellungsverfahren
US11462495B2 (en) * 2020-05-21 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets 3D SoIC system integration and fabrication methods
US11462519B2 (en) 2020-06-01 2022-10-04 Nanya Technology Corporation Semiconductor device with active interposer and method for fabricating the same
US11862545B2 (en) * 2020-07-28 2024-01-02 Dyi-chung Hu Integrated substrate structure, electronic assembly, and manufacturing method thereof
KR20220028741A (ko) * 2020-08-31 2022-03-08 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
CN116457941A (zh) * 2020-10-28 2023-07-18 华为技术有限公司 多芯片封装结构、制造方法以及电子设备
US11769731B2 (en) 2021-01-14 2023-09-26 Taiwan Semiconductor Manufacturing Co., Ltd Architecture for computing system package
DE102021109879A1 (de) * 2021-02-12 2022-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Dielektrikum-durchkontaktierungen für direktverbindung und verfahren zu deren herstellung
KR20220142067A (ko) 2021-04-14 2022-10-21 에스케이하이닉스 주식회사 타원형 채널 플러그를 갖는 반도체 메모리 장치
KR20230010397A (ko) 2021-07-12 2023-01-19 에스케이하이닉스 주식회사 노출된 상면들을 가진 이종 반도체 칩들을 포함하는 반도체 패키지들 및 그 제조 방법
US11749534B1 (en) 2022-07-21 2023-09-05 Deca Technologies Usa, Inc. Quad flat no-lead (QFN) package without leadframe and direct contact interconnect build-up structure and method for making the same
US12062550B2 (en) 2022-05-31 2024-08-13 Deca Technologies Usa, Inc. Molded direct contact interconnect substrate and methods of making same
US11973051B2 (en) 2022-05-31 2024-04-30 Deca Technologies Usa, Inc. Molded direct contact interconnect structure without capture pads and method for the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140084456A1 (en) * 2012-09-27 2014-03-27 Myun-sung Kang Semiconductor packages, methods of manufacturing semiconductor packages, and systems including semiconductor packages
TW201714275A (zh) * 2015-07-30 2017-04-16 聯發科技股份有限公司 半導體封裝結構及其形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
CN101542701B (zh) 2008-06-05 2011-05-25 香港应用科技研究院有限公司 基于硅通孔的三维晶圆叠层的键合方法
CN102169845B (zh) 2011-02-22 2013-08-14 中国科学院微电子研究所 一种用于三维封装的多层混合同步键合结构及方法
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9620488B2 (en) 2015-08-19 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional integrated circuit structure and bonded structure
JP2018129412A (ja) 2017-02-09 2018-08-16 ソニーセミコンダクタソリューションズ株式会社 半導体装置、および半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140084456A1 (en) * 2012-09-27 2014-03-27 Myun-sung Kang Semiconductor packages, methods of manufacturing semiconductor packages, and systems including semiconductor packages
TW201714275A (zh) * 2015-07-30 2017-04-16 聯發科技股份有限公司 半導體封裝結構及其形成方法

Also Published As

Publication number Publication date
KR102308487B1 (ko) 2021-10-07
US20200118908A1 (en) 2020-04-16
KR20200041265A (ko) 2020-04-21
TW202018831A (zh) 2020-05-16
US11171076B2 (en) 2021-11-09

Similar Documents

Publication Publication Date Title
TWI727454B (zh) 積體電路封裝件及其形成方法
TWI735008B (zh) 積體電路裝置的封裝及其形成方法
TWI478314B (zh) 半導體裝置與半導體裝置的形成方法
US11462495B2 (en) Chiplets 3D SoIC system integration and fabrication methods
KR102318303B1 (ko) 다이 스택 및 그 형성 방법
US11855020B2 (en) Chiplets 3D SoIC system integration and fabrication methods
TWI795700B (zh) 積體電路封裝及其形成方法
CN111029303B (zh) 集成电路封装件及其形成方法
US20240038718A1 (en) Semiconductor Package and Method
US12125820B2 (en) Through-dielectric vias for direct connection and method forming same
US20240021576A1 (en) Through-dielectric vias for direct connection and method forming same
US20230395517A1 (en) 3D Stacking Architecture Through TSV and Methods Forming Same
US20230361048A1 (en) Semiconductor package and method of fabricating semiconductor package
US20240363590A1 (en) Die stacks and methods forming same
US20240072034A1 (en) 3DIC Package and Method Forming the Same