TWI724363B - 半導體晶粒結構及場板功率n通道場效電晶體晶粒 - Google Patents

半導體晶粒結構及場板功率n通道場效電晶體晶粒 Download PDF

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TWI724363B
TWI724363B TW108101429A TW108101429A TWI724363B TW I724363 B TWI724363 B TW I724363B TW 108101429 A TW108101429 A TW 108101429A TW 108101429 A TW108101429 A TW 108101429A TW I724363 B TWI724363 B TW I724363B
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deep trench
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floating
semiconductor
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TW201946272A (zh
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石京郁
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美商力特福斯股份有限公司
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明提供一種半導體晶粒結構及場板功率N通道場效電 晶體晶粒。場板功率N通道場效電晶體晶粒具有主動區域及邊緣區域。第一對平行延伸的深溝槽與場板功率N通道場效電晶體晶粒的側邊緣平行地延伸。第二對平行延伸的深溝槽垂直於側邊緣而朝向側邊緣延伸，使得第二對平行延伸的深溝槽中的每一溝槽終止於第一對平行延伸的深溝槽中的內側深溝槽中。嵌入式場板結構嵌入於該些溝槽中。多個浮置P型井區整個設置於第二對深溝槽之間、整個設置於主動區域與第一對平行延伸的深溝槽中的內側深溝槽之間。使用此邊緣區域結構，總體裝置的擊穿電壓BVDSS得以增大，此乃因邊緣區域的擊穿電壓較不具有浮置P型井區的相同結構而言增大。

Description

半導體晶粒結構及場板功率N通道場效電晶體晶 粒
所述實施例是有關於功率場效電晶體且是有關於方法。
為提高溝槽功率場效電晶體(trench power field effect transistor)(亦稱為功率溝槽金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor，MOSFET))首次遭受突崩擊穿的汲極-源極電壓，正愈來愈多地使用包括「埋入式場板」的一種溝槽功率MOSFET。此種溝槽功率MOSFET具有各種其他名稱。舉例而言，有時亦使用用語「埋入式源極」。用語「RESURF」亦與此種溝槽功率MOSFET結合使用。在典型結構中，埋入式場板電晶體是具有極深溝槽的溝槽MOSFET。在此深溝槽內，存在閘極以及垂直定向的埋入式導電場板。此埋入式場板通常設置於閘極下方，使得其沿著所述深溝槽的最深部分的內側面延伸。埋入式場板與位於其上方的閘極一樣皆是通過絕緣介電層與溝槽側 壁的半導體材料分隔開。由於其放置位置，埋入式場板沿著且鄰近於位於深溝槽最外側的N-型半導體材料中的漂移帶延伸。此漂移帶是設置於電晶體的P型主體區之下之一定量的N-型半導體材料。相較於不具有埋入式場板的相同的基本溝槽MOSFET結構而言，藉由將埋入式場板耦合至電晶體的源極電極，可針對給定的RDS(ON)及積體電路大小增大電晶體的擊穿電壓BVDSS。此一般性電晶體結構存在諸多變化形式。
溝槽功率N通道場效電晶體晶粒的半導體部分具有切入至其頂側半導體表面中的多個深溝槽。該些深溝槽中的第一者在與晶粒的側邊緣的平行的第一直線上延伸。該些深溝槽中的第二者在與第一直線平行的第二直線上延伸，使得第一深溝槽設置於第二深溝槽與晶粒的側邊緣之間。這兩個深溝槽彼此平行地且平行於晶粒的側邊緣延伸。可存在更多個該些平行延伸的深溝槽，但至少存在這兩個深溝槽。另外，第三深溝槽在垂直於晶粒的側邊緣的第三直線上延伸。此第三深溝槽終止於第二深溝槽中。第四深溝槽在垂直於晶粒的側邊緣的第四直線上延伸。所述第四深溝槽亦終止於第二深溝槽中。第三深溝槽與第四深溝槽彼此平行地延伸，且第三深溝槽與第四深溝槽之間不存在深溝槽。溝槽功率N通道場效電晶體晶粒亦具有嵌入式場板結構。在一個實例中，此嵌入式場板結構的第一部分至少部分地設置於第一深溝槽 中，此嵌入式場板結構的第二部分至少部分地設置於第二深溝槽中，此嵌入式場板結構的第三部分至少部分地設置於第三深溝槽中，且此嵌入式場板結構的第四部分至少部分地設置於第四深溝槽中。
當自俯視角度觀察時，溝槽功率N通道場效電晶體晶粒具有邊緣區域及主動區域。所述邊緣區域被設置成鄰近晶粒的側邊緣。此邊緣區域中不存在閘極或N+型源極區。另一方面，主動區域具有閘極及N+型源極區。邊緣區域設置於晶粒的主動區域與晶粒側邊緣之間。
當自剖面側視角度觀察時，晶粒的半導體部分包括底部N++型基板層。N-型漂移層設置於所述N++型基板層上，N-型漂移層向上延伸至頂側半導體表面。此N-型漂移層具有下層部分及摻雜程度更高的N-型上層部分。深溝槽切入至N-型上層部分中且向下延伸穿過N-型上層部分，使得深溝槽僅穿透N-型下層部分的頂部。
在主動區域中，P型主體區位於第三深溝槽與第四深溝槽之間。此P型主體區自頂側半導體表面向下延伸至N-型漂移層中。在主動區域中，N+型源極區設置於第三深溝槽與第四深溝槽之間。P型主體區亦自主動區域(穿過閘極匯流排線與嵌入式場板接地區域)側向地(laterally)延伸並延伸至邊緣區域中。
溝槽功率N通道場效電晶體晶粒具有頂側源極金屬電極結構、頂側閘極金屬電極結構及底側汲極金屬電極結構。源極金 屬電極結構耦合至主動區域的一個或多個N+型源極區，且亦耦合至主動區域的一個或多個P型主體區。閘極金屬電極結構耦合至主動區域的一個或多個閘極。汲極金屬電極結構設置於晶粒的半導體部分的底部上，使得其耦合至底側半導體表面且與N++型基板層接觸。
另外，溝槽功率N通道場效電晶體晶粒包括第一浮置P型井區及第二浮置P型井區。第一浮置P型井區自頂側半導體表面向下延伸至N-型漂移層中。第一浮置P型井區整個設置於半導體晶粒結構的邊緣區域中，且整個設置於第三深溝槽與第四深溝槽之間。同樣地，第二浮置P型井區自頂側半導體表面向下延伸至N-型漂移層中。第二浮置P型井區整個設置於半導體晶粒結構的邊緣區域中，且整個設置於第三深溝槽與第四深溝槽之間。
第一浮置P型井區及第二浮置P型井區被設置成使得其沿著第五直線設置。所述第五直線自半導體晶粒結構的側邊緣垂直地延伸，並橫向地延伸穿過第一深溝槽及第二深溝槽，並延伸於第三溝槽與第四溝槽之間，並且延伸至半導體晶粒結構的主動區域中。此第五線平行於第三深溝槽的第三直線且亦平行於第四深溝槽的第四直線。第一浮置P型井區及第二浮置P型井區沿著此第五直線設置於P型主體區與第二深溝槽之間。在一個實例中，第一浮置P型井區是兩個浮置P型井區中的外側浮置P型井區(最接近於晶粒側邊緣的浮置P型井區)，且此第一浮置P型井區形成第二深溝槽的內側壁的一部分。所述第一浮置P型井區及所述第 二浮置P型井區在其不耦合至總體MOSFET裝置的源極電極結構、汲極電極結構或閘極電極結構這一意義上而言是「浮置」的。 在相對於源極電極結構而言汲極電極結構上存在大的電壓的情況中，第一浮置P型井區及第二浮置P型井區用於防止邊緣區域中發生突崩擊穿。在一個實例中，若不提供一組浮置P型井區(包括第一浮置P型井區及第二浮置P型井區)，則溝槽功率N通道場效電晶體晶粒將在靠近第二深溝槽的邊緣區域中遭受突崩擊穿。 藉由提供此一組浮置P型井區，總體溝槽功率N通道場效電晶體晶粒不會首先在邊緣區域中遭受突崩擊穿，而是首先在主動區域中遭受突崩擊穿。因此，總體電晶體裝置的汲極-源極擊穿電壓BVDSS得以增大。
在下文的詳細說明中闡述進一步的細節及實施例以及方法。此概述並不旨在界定本發明。本發明是由申請專利範圍界定。
1:半導體晶粒結構/晶粒結構/半導體晶粒
2:周邊側邊緣/右側邊緣/側邊緣
3、4、5:周邊側邊緣
6:第一周邊深溝槽/深溝槽/第一深溝槽
7:第二周邊深溝槽/深溝槽/溝槽/第二深溝槽
8:第三深溝槽/深溝槽/溝槽
9:第四深溝槽/溝槽/深溝槽
10:主動區域
11:閘極匯流排線與嵌入式場板接地區域
12:邊緣區域
13:閘極結構
13A、13B:部分
13BA、13BB:朝下延伸部分/部分
13BC:橋接部分/部分
14:嵌入式場板結構
14A、14B:部分/嵌入式場板部分
15:N-型漂移層
15A:下層部分
15B:上層部分
16:N++型基板層
17:頂側半導體表面
18:底側半導體表面
19:P型主體區
20:N+型源極區
20A、20B:橫檔部分
22:P+型主體接觸區
23:絕緣介電層
23A、23B:絕緣介電特徵/溝槽填充絕緣介電特徵
24:汲極金屬電極結構/汲極金屬電極/底側汲極金屬電極
25:金屬閘極電極結構
26:源極金屬電極結構/源極金屬結構/源極金屬電極
27:主體金屬結構/主體金屬
28:通道
30:P型主體區延伸部/P型區/延伸部/最左側P型區
32:絕緣介電材料
33:絕緣介電層
29、31、34、36、37、39、40、42、43、45、46、47、48、49:P型區
35、38、41、44:浮置P型區/P型區/浮置P型井區
50:P型主體區
51:N+型源極區
52:第五直線
53、54、55、56:線
57:P型區
106:金屬源極接墊
107:閘極接墊
A-A’、B-B’、C-C’:剖面線
所附圖式繪示出本發明的實施例，在所附圖式中相似的編號表示相似的組件。
圖1是根據一個新穎方面的半導體晶粒結構1的俯視圖(示出金屬層的晶粒俯視圖)。
圖2是示出圖1所示半導體晶粒結構1的頂側半導體表面中的深溝槽的簡化俯視圖，也就是說，圖2為半導體表面處的晶粒俯視圖(未示出位於半導體上方的層)。
圖3是晶粒結構1的右上角部分的圖式，圖3示出主動區域、閘極匯流排線與嵌入式場板接地區域以及邊緣區域，也就是說，圖3為半導體表面處的晶粒俯視圖(未示出位於半導體上方的層)。
圖4是與圖3類似的圖式，但圖4示出截取剖面線C-C'的位置，也就是說，圖4為半導體表面處的晶粒俯視圖(未示出位於半導體上方的層)。
圖5是沿著圖3的剖面線A-A'截取的剖視圖，也就是說，圖5為主動區域的剖視圖(沿著剖面線A-A'截取)。
圖6是在圖5中以剖面形式繪示的主動區域的部分的透視圖，也就是說，圖6為主動區域的立體圖，其中示出溝槽填充材料及位於半導體表面上方的結構(在剖面線A-A'處進行觀看)。
圖7是圖6所示結構的的透視圖，但未示出溝槽填充材料且未示出位於頂側半導體表面上方的結構，也就是說，圖7為主動區域的立體圖，其中未示出溝槽填充材料及位於半導體表面上方的結構(在剖面線A-A'處進行觀看)。
圖8是沿著圖3及圖4的邊緣區域12的剖面線C-C'截取的剖面圖，也就是說，圖8為邊緣區域的剖視圖(沿著剖面線在剖面線C-C'截取)。
圖9是圖8所示的邊緣區域的透視圖，也就是說，圖9為示出主體金屬的邊緣區域立體圖(在剖面線C-C'處進行觀看)。
圖10是圖9所示結構的透視圖，但未示出主體金屬，也就是說，圖10為邊緣區域的立體圖，其中示出溝槽填充材料及位於半 導體表面上方的結構(在剖面線C-C'處進行觀看)。
圖11是圖10所示結構的透視圖，但未示出溝槽填充材料且未示出位於頂側半導體表面17上方的結構，也就是說，圖11為邊緣區域的立體圖，其中未示出溝槽填充材料及位於半導體表面上方的結構(在剖面線C-C'處進行觀看)。
圖12是繪示出圖1所示半導體晶粒結構1的各種特徵及結構的相對位置的簡化俯視圖(沿著自晶粒的邊緣向內垂直延伸的線的結構)。
圖13是示出擊穿電壓如何隨著圖14的替代性半導體晶粒結構的單位晶格半寬度(unit cell half width)而變化的曲線圖。
圖14繪示出具有不同的邊緣區域結構的替代性半導體晶粒結構。
圖15是示出擊穿電壓如何隨著圖16所示替代性半導體晶粒結構的單位晶格半寬度而變化的曲線圖。
圖16繪示出與圖15的曲線圖相關的新穎的半導體晶粒結構。
圖17是示出位於半導體晶粒結構的主動區域中的另一嵌入式場板結構的剖面圖。
圖18是是示出位於半導體晶粒結構的邊緣區域中的另一嵌入式場板結構的剖面圖。
現在將詳細地參考背景實例及本發明的一些實施例，所 述一些實施例的實例在附圖中加以說明。在下文的說明及申請專利範圍中，當第一物體被稱為設置於第二物體「之上」或設置於第二物體「上」時，應理解為所述第一物體可直接位於所述第二物體上，或者第一物體與第二物體之間可存在中間物體。類似地，本文中使用諸如「左(left)」、「右(right)」、「頂部(top)」、「頂側(topside)」、「向上(up)」、「朝上(upward)」、「向下(down)」、「朝下(downward)」、「豎直地(vertically)」、「側向的(lateral)」、「側向地(laterally)」、「側(side)」、「下邊(under)」、「背側(backside)」、「底部(bottom)」及「底側(bottomside)」等用語來闡述所述結構的不同部分之間的相對定向，且應理解所述總體結構可實際上在三維空間中以任何方式進行定向。在下文的說明中，N型矽通常可被簡稱為N型矽，或者可更具體地稱為N++型矽、N+型矽、N型矽或N-型矽。N++、N+、N及N-標識符旨在在一般粗略意義上標識摻質濃度的相對範圍。舉例而言，被闡述為N型矽的矽與被闡述為N-型矽的矽之間的濃度範圍可存在交疊。N+型矽範圍的最低(bottom)摻質濃度可低於N型矽範圍的最高(top)摻質濃度。本專利文件中亦採用相同的方式來闡述P型矽(有時更具體地稱為P++型矽、P+型矽、P型矽或P-型矽)。
圖1是根據一個新穎方面的半導體晶粒結構1的俯視圖。此半導體晶粒結構1是嵌入式場板N通道場效電晶體晶粒(embedded field plate N-channel field effect transistor die)，亦被稱為EFP MOSFET。「EFP」代表「嵌入式場板」。當自俯視角度觀 察半導體晶粒結構1時，所述晶粒結構具有四個周邊側邊緣2至5。位於晶粒結構的頂部上的是：源極金屬電極結構26；金屬源極接墊106，是源極金屬電極結構26的一部分；金屬閘極電極結構25；閘極接墊107，是金屬閘極電極結構25的一部分；主體金屬結構27；以及金屬空乏終止環(未示出)。所述金屬空乏終止環(depletion stopper ring)是包繞主體金屬結構且沿著晶粒結構的四個周邊側邊緣延伸的另一金屬環。
在此佈局中，閘極電極結構放置於主體金屬與源極電極之間以能夠使閘極電極結構形成迴路。使閘極電極結構具有迴路形狀會促使閘極訊號分佈更均勻。另外，若突崩擊穿將出現於邊緣區域中，則源極金屬與主體金屬之間的間距將會在此電流路徑中提供一些電阻，這是所期望的且會提高裝置耐用性。
圖2是圖1所示半導體晶粒結構1的簡化俯視圖，但在圖2的圖示中未示出位於頂側半導體表面的水平面上方的結構。 晶粒結構的在圖2中以白色示出的部分是頂側半導體表面。陰影部分是多個深溝槽以及位於所述多個深溝槽中的任何結構(諸如，嵌入式場板)。應特別注意第一周邊深溝槽6。在圖示中，此第一周邊深溝槽6在處於與晶粒結構的右側邊緣2平行的豎直維度中的第一直線上延伸。參考編號7表示第二周邊深溝槽。此第二周邊深溝槽7圍繞晶粒的邊緣延伸，但位於第一周邊深溝槽6內側。此第二周邊深溝槽7沿著晶粒結構的右側邊緣2在第二直線上延伸。參考編號8標示第三深溝槽。此第三深溝槽8在第三 直線上延伸。第三深溝槽8的左端在晶粒結構的左側上終止於深溝槽7中的一個位置處。第三深溝槽8的右端在晶粒結構的右側上終止於深溝槽7中的另一位置處。同樣地，第四深溝槽9在直線上延伸。第四深溝槽9的左端在晶粒結構的左側上終止於深溝槽7中的一個位置處。第四深溝槽9的右端在晶粒結構的右側上終止於深溝槽7中的另一位置處。第三深溝槽8與第四深溝槽9跨越晶粒的中心部分彼此平行地延伸，如圖中所繪示的。雖然深溝槽8及深溝槽9被稱為單獨的深溝槽，但三個溝槽7、8及9實際上合併在一起以形成單個深溝槽結構。深溝槽在圖2中繪示出為相當寬以使圖示清晰。實際上，存在更多水平延伸的深溝槽，且該些深溝槽較所繪示的溝槽要窄得多。深溝槽不僅較圖2中所繪示的溝槽要窄得多，而且深溝槽中的鄰近深溝槽之間的間距亦更小。嵌入式場板結構位於每一深溝槽的中心中。圖2中未示出此嵌入式場板結構。另外，在晶粒結構的主動區域10中，存在向上延伸至頂側半導體表面17的閘極結構及其他結構，頂側半導體表面17未示出。圖2中未示出該些其他結構以將圖式簡化。
圖3是晶粒結構1的右上角部分的圖式。在此圖式中，示出了更多的深溝槽且所示深溝槽具有更緊湊的間隔。提供所述圖式以指出三個區域，亦即：主動區域10、閘極匯流排線與嵌入式場板接地區域11以及邊緣區域12。剖面線A-A'是在主動區域10的左側處截取的剖面線。剖面線B-B'是在邊緣區域12的底側處截取的剖面線。
圖4是與圖3類似的圖式，但圖4示出截取剖面線C-C'的位置。剖面線C-C'是在邊緣區域12的左側處截取。
圖5是沿著圖3的剖面線A-A'截取的剖視圖。左側處所示的深溝槽是第三深溝槽8。右側所示的深溝槽是第四深溝槽9。 閘極結構13的一部分13A在左側處延伸至第三深溝槽8中，且閘極結構13的一部分13B在右側處延伸至第四深溝槽9。閘極結構13的該些部分13A及13B是N+型多晶矽的特徵。參考編號13標示總體閘極結構。參考編號14A及參考編號14B標示嵌入式場板結構14的部分。若在頂側半導體表面處以剖面形式觀看晶粒上任何位置處的深溝槽，則深溝槽中存在嵌入式場板結構14的一部分，所述部分顯示為圖5的圖示中的部分14A及部分14B。嵌入式場板結構14是N+型多晶矽的結構。N-型漂移層15設置於N++型基板層16上。N++型基板層16是單晶晶圓材料，而N-型漂移層15通常是磊晶矽。
N-型漂移層15依次包括下層部分15A及上層部分15B。 N-型漂移層的上層部分15B具有較N-型漂移層的下層部分15A高的N-型摻質濃度。N-型漂移層15被標記為向上一直延伸至頂側半導體表面17，此乃因其確實延伸到半導體晶粒1的其他區域中的此表面(見圖9至11)。深溝槽自頂側半導體表面17向下延伸，並延伸穿過N-型漂移層的上層部分15B，並延伸至N-型漂移層的下層部分15A的頂部中。參考編號32標示深溝槽中的絕緣介電材料。此絕緣介電材料32通常是熱氧化矽(例如，SiO2)。此絕緣 介電材料32將深溝槽的半導體側壁與閘極結構13的一些部分以及與嵌入式場板結構14的一些部分分隔開。參考編號18標示底側半導體表面。P型主體區自頂側半導體表面17朝下延伸，如圖所示。圖5的右側處的參考編號19標示P型主體區中的一者。一組N+型源極區自頂側半導體表面17朝下延伸至P型主體區中，如圖所示。該些N+型源極區中的一者由參考編號20標示。當自俯視角度觀察時，該些N+型源極區具有階梯形狀。所述階梯形狀包括兩個平行延伸的側及一組橫跨橫檔(spanning rung)。源極金屬結構26在N+型源極區的橫檔區域處耦合至此N+型源極區的頂部。在圖5的特定剖面中不存在源極金屬電極26與N+型源極區之間的該些連接點。另外，源極金屬電極結構26亦經由P+型主體接觸區耦合至P型主體區。舉例而言，源極金屬結構26在圖5的右側處經由P+型主體接觸區22耦合至P型主體區19。絕緣介電特徵23A及絕緣介電特徵23B將源極金屬電極26與閘極結構13分隔開。位於晶粒結構的頂部上的金屬閘極電極結構25的結構(參見圖1)在圖5的特定剖面中無法看到，但金屬閘極電極結構25經由晶粒上別處的連接耦合至閘極結構13的N+型多晶矽。汲極金屬電極結構24設置於底側半導體表面18上。
當相對於源極金屬電極26而在閘極結構13上施加較電晶體裝置的臨限值電壓高的正電壓時，則在鄰近閘極結構的溝槽的邊緣處會形成導電通道。此通道自N+型源極區豎直地朝下延伸，穿過P型主體區，並延伸至N-型漂移層15的下伏N-型材料。 在源極-汲極電壓的影響下，電子可自N+型源極區，豎直地向下穿過此導電通道，並流動至N-型漂移層15，穿過N-型漂移層15，並穿過N++型基板層16而流動至汲極金屬電極24。舉例而言，在N+型源極區20的情形中，藉由箭頭28來說明所述通道。
當以剖面形式觀察深溝槽時，如在圖5的情形中，深溝槽內的嵌入式場板自位於頂側半導體表面17處或極靠近頂側半導體表面17的開始點開始朝下延伸，並朝下穿過深溝槽的中心，而延伸至接近N-型漂移層15的上層部分15B的深度的深度。當以剖面形式觀察深溝槽時，如在圖5的情形中，閘極結構13具有第一朝下延伸部分，所述第一朝下延伸部分沿著深溝槽的一個側邊緣與位於所述深溝槽的所述側上的P型主體區之間的邊界朝下延伸；且亦具有第二朝下延伸部分，所述第二朝下延伸部分沿著深溝槽的相對側邊緣與位於所述深溝槽的所述相對側上的P型主體區之間的邊界朝下延伸。在圖5中，參考編號13BA標示深溝槽9中的閘極結構部分的一個此第一朝下延伸部分，且參考編號13BB標示深溝槽9中的閘極結構的一個此第二朝下延伸部分。兩個朝下延伸部分13BA與13BB在頂部處經由閘極結構的橋接部分13BC連接在一起。此橋接部分13BC設置於頂側半導體表面17上方，且其橋接且橫跨於嵌入式場板部分14B的頂部跨度(top extent)之上，如圖5中所示。兩個朝下延伸部分13BA及13BB以及橋接部分(bridge portion)13BC全部皆是由同一層N+型多晶矽製作而成。用語「層」在此指代一定量相連的多晶矽，其中 多晶矽是在同一多晶矽沉積步驟中沉積的多晶矽。在此意義上，部分13BA、部分13BB及部分13BC是一個多晶矽層。
圖6是在圖5中以剖面形式繪示的主動區域的部分的透視圖。在圖6的結構中看到階梯形N+型源極區20的兩個橫檔部分(rung portions)20A及20B。橫檔部分實際上是總體N+型源極區20的一些部分。
圖7是圖6所示結構的透視圖，但未示出溝槽填充材料且未示出位於頂側半導體表面上方的結構。自此透視圖會看到階梯形N+型源極區。在階梯形N+型源極區51的橫檔之間為P+型主體接觸區。
圖8是沿著圖3及圖4的邊緣區域12的剖面線C-C'截取的剖面圖。汲極金屬電極24、N++型基板層16及N-型漂移層15的下層部分15A以及N-型漂移層15的上層部分15B是與在圖5的主動區域10的剖面中相同的結構。參考編號29、參考編號30及參考編號31標示主動區域的P型主體區的延伸部。具體而言，P型主體區延伸部30是P型主體區50的延伸部。參考編號14標示N+型多晶矽的嵌入式場板層。所述N+型多晶矽是製作圖5的嵌入式場板部分14A及嵌入式場板部分14B的同一N+型多晶矽層。圖8的嵌入式場板結構與圖5的嵌入式場板結構是同一N+型多晶矽份量(amount)的完全不同部分。圖8的頂部處的主體金屬27是與圖1中所示相同的主體金屬27。參考編號32標示溝槽填充絕緣介電層的特徵。所述溝槽填充絕緣介電層是形成圖5中 所示的主動區域中的溝槽填充絕緣介電特徵23A及23B的同一層溝槽填充絕緣電介質。圖8的絕緣介電層33(例如，SiO2)是與圖5中的剖面中由參考編號23標示的相同的絕緣介電層(例如，SiO2)。邊緣區域12中不存在N+型源極區。邊緣區域12中不存在閘極結構。閘極結構13不延伸至邊緣區域12中。
圖9是邊緣區域12的透視圖。
圖10是圖9所示結構的透視圖，但未示出主體金屬27。
圖11是圖10所示結構的透視圖，但未示出溝槽填充材料且未示出位於頂側半導體表面17上方的結構。此圖式揭示出諸多隔離且浮置的P型區34至49。該些浮置P型區中的每一者彼此整個分隔開。該些P型區中的每一者是浮置的，且不耦合至晶粒的源極電極結構，不耦合至晶粒的汲極電極結構，亦不耦合至晶粒的閘極電極結構。當自俯視角度觀察晶粒結構1時，P型區46至P型區49實際上是環繞晶粒結構1的周邊的同心環形結構。 P型區44、P型區41、P型區38、P型區35及P型區30整個設置於第三深溝槽8(參見圖2)與第四深溝槽9(參見圖2)之間。 P型區44、P型區41、P型區38及P型區35整個設置於主動區域10(參見圖1)與晶粒的右側邊緣2(參見圖1)之間。
圖12是繪示出圖1所示半導體晶粒結構1的各種特徵及結構的相對位置的簡化俯視圖。在所述圖式的定向中，深溝槽6在與晶粒的側邊緣2平行的第一直線上延伸。深溝槽7在與第一條線平行的第二直線上延伸。深溝槽6與深溝槽7是彼此平行地 且平行於側邊緣2延伸的一對深溝槽。深溝槽8是在第三直線上延伸的第三深溝槽。第三線垂直於側邊緣2。深溝槽9是在第四直線上延伸的第四深溝槽。第四線平行於第三條線。深溝槽8與深溝槽9是彼此平行地且垂直於側邊緣2延伸的一對深溝槽。第三深溝槽8終止於第二深溝槽7中。同樣地，第四深溝槽9亦終止於第二深溝槽7中。該些深溝槽6、7、8及9是與圖2中所繪示且與上文中所述相同的深溝槽。P型區31、P型區30及P型區29不是浮置的，而是其連接至主動區域中的源極金屬。
嵌入式場板結構14至少部分地設置於四個深溝槽6、7、8及9中。嵌入式場板結構14的第一部分至少部分地設置於第一深溝槽6中。嵌入式場板結構14的第二部分至少部分地設置於第二深溝槽7中。嵌入式場板結構14的第三部分至少部分地設置於第三深溝槽8中。嵌入式場板結構14的第四部分至少部分地設置於第四深溝槽9中。
P型主體區50設置於主動區域10中，但P型主體區50具有側向地延伸穿過閘極匯流排線與嵌入式場板接地區域11且延伸至邊緣區域12中的延伸部30。P型主體區50亦整個設置於第三深溝槽8與第四深溝槽9之間。N+型源極區51整個設置於主動區域10中且整個設置於第三深溝槽8與第四深溝槽9之間。閘極結構13的部分13A至少部分地設置於主動區域10中的第三深溝槽8中，且閘極結構13的部分13B至少部分地設置於主動區域10中的第四深溝槽9中。閘極結構13沒有延伸至晶粒的邊緣區域 12中的部分。浮置P型區44、浮置P型區41、浮置P型區38及浮置P型區35中的每一者整個設置於第三深溝槽8與第四深溝槽9之間且整個設置於晶粒的邊緣區域12內。圖12所示結構的組成部分被定向成使得P型區44、P型區41、P型區38、P型區35及P型區30沿著第五直線52設置。第五直線52垂直於側邊緣2延伸且自側邊緣2延伸，且然後橫向地延伸穿過第一深溝槽6，且然後橫向地延伸穿過第二深溝槽7，且然後延伸於第三深溝槽8與第四深溝槽9之間並延伸至晶粒的主動區域10中。如圖12中所繪示的，P型區44、P型區41、P型區38、P型區35及P型區30沿著此第五直線52設置於側邊緣2與主動區域10之間。
圖13及圖14繪示且闡釋具有不同的邊緣區域結構的替代性半導體晶粒結構。並非具有圖12中所示的所述多個新穎的浮置P型區44、41、38及35，而是替代性半導體晶粒結構具有單個P型區57。此單個P型區57自圖3所示A-A'區段的位置向外一直延伸至第二深溝槽7。在其他方面中，替代性半導體晶粒結構與圖1所示新穎的半導體晶粒結構相同。圖13所示圖式的水平軸闡明半導體晶粒結構的單位晶格的半寬度。標注有正方形的線53表示主動區域的擊穿電壓作為單位晶格半寬度的函數如何變化。標注有圓形的線54是表示邊緣區域的擊穿電壓作為單位晶格半寬度的函數如何變化的模擬結果。在單位晶格半寬度是2.0微米時，替代性半導體晶粒結構經過模擬是在153伏特的擊穿電壓BVDSS下在由星號58表示的位置中遭受突崩擊穿。因此，總體N通道場效電 晶體晶粒的擊穿電壓BVDSS低於在裝置不首先在其邊緣區域中發生擊穿的情況下擊穿電壓本可能會出現的值。在2.0單位晶格半寬度的位置處總體N通道場效電晶體晶粒的擊穿電壓BVDSS是圖13所示兩條線中的較低者。
圖15及圖16繪示且闡釋新穎的半導體晶粒結構1的邊緣區域12的新穎結構的相對優勢。標注有正方形的線55示出主動區域的擊穿電壓作為單位晶格半寬度的函數如何變化。標注有三角形的線56示出邊緣區域的擊穿電壓如何隨著單位晶格半寬度而變化。在單位晶格半寬度是2.0微米時，總體半導體晶粒結構的擊穿電壓是由主動區域的擊穿電壓來確定，此乃因邊緣區域的擊穿電壓(由線56表示)大於主動區域的擊穿電壓。在單位晶格半寬度為2.0的位置處，線56高於線55。如圖16中所示，底側汲極金屬電極24上的167伏特電位與P型區30上的0伏特電位之間可存在167伏特的大差值，但P型區30、P型區35、P型區38、P型區41及P型區44之間的間隙使得浮置區上的電位彼此不同。 因此，最左側P型區30上的0伏特電位並不會側向向右一直延伸至第二深溝槽7的左邊緣，此乃因存在橫跨此距離的單個導電P型區。而是，167伏特的差值可跨越此側向距離而下降。P型區30、P型區35、P型區38、P型區41及P型區44上的電壓分別是0伏特、6伏特、12伏特、18伏特及24伏特。這意味著在圖16所示結構的情形中，即使汲極金屬電極24與源極金屬電極26之間存在167伏特的較大差值，但第二深溝槽7的左邊緣處的相對電 壓僅為143伏特。總體半導體晶粒結構經過模擬而具有167伏特的擊穿電壓BVDSS。由於模擬軟體的限制，線56實際上是對不具有三個平坦側壁(溝槽7、溝槽8及溝槽9的側壁)而是具有半圓柱半徑側壁結構的類似結構的模擬。
儘管上文出於指導目的而闡述了某些具體實施例，但此專利文件的教示具有普適性且並不限於上述具體的實施例。儘管示出特定閘極結構及嵌入式場板結構位於深溝槽中，但在其他實施例中，使用其他閘極結構及其他嵌入式場板結構。在主動區域與周邊深溝槽之間利用浮置P型井區44、浮置P型井區41、浮置P型井區38及浮置P型井區35並不限於特定的閘極結構/嵌入式場板設計。在給定半導體裝置內，嵌入式場板在主動區域中可具有相較於其在邊緣區域中所具有的形式不同的形式。舉例而言，圖17所示結構可用於主動區域中，且圖18所示結構可用於邊緣區域中。在圖17的剖面中，嵌入式場板整個設置於閘極結構的底部跨度(extent)之下。閘極結構的底部跨度位於P型主體區的底部跨度處或略低於P型主體區的底部跨度。浮置P型井區44、浮置P型井區41、浮置P型井區38及浮置P型井區35亦可與該些類型的埋入式場板結構搭配使用。因此，可在不背離申請專利範圍中所闡明的本發明範疇的情況下實踐所述實施例的各種特徵的各種潤飾、更改及組合。
2:周邊側邊緣/右側邊緣/側邊緣
6:第一周邊深溝槽/深溝槽/第一深溝槽
7:第二周邊深溝槽/深溝槽/溝槽/第二深溝槽
8:第三深溝槽/深溝槽/溝槽
9:第四深溝槽/溝槽/深溝槽
30:P型主體區延伸部/P型區/延伸部/最左側P型區
35、38、41、44:浮置P型區/P型區/浮置P型井區
50:P型主體區
51:N+型源極區
52:第五直線

Claims (16)

  1. 一種半導體晶粒結構，具有邊緣區域及主動區域，所述半導體晶粒結構包括：N-型漂移層，其中第一深溝槽向下延伸至所述N-型漂移層中，其中所述第一深溝槽在與所述半導體晶粒結構的側邊緣平行的第一直線上延伸，其中第二深溝槽向下延伸至所述N-型漂移層中，其中所述第二深溝槽在與所述第一深溝槽的所述第一直線平行的第二直線上延伸，其中第三深溝槽向下延伸至所述N-型漂移層中，其中所述第三深溝槽在垂直於所述半導體晶粒結構的所述側邊緣的第三直線上延伸且終止於所述第二深溝槽中，其中第四深溝槽在垂直於所述半導體晶粒結構的所述側邊緣的第四直線上延伸且終止於所述第二深溝槽中，其中所述第一直線平行於所述第二直線，且其中所述第三直線平行於所述第四直線；嵌入式場板結構，至少部分地設置於所述第三深溝槽中且至少部分地設置於所述第四深溝槽中；P型主體區，向下延伸至所述N-型漂移層中，其中所述P型主體區設置於所述第三深溝槽與所述第四深溝槽之間的所述半導體晶粒結構的所述主動區域中，其中所述P型主體區沒有延伸至所述半導體晶粒結構的所述邊緣區域中的部分；N+型源極區，向下延伸至所述P型主體區中，其中所述N+型源極區設置於所述第三深溝槽與所述第四深溝槽之間的所述半導體晶粒結構的所述主動區域中； 第一浮置P型井區，向下延伸至所述N-型漂移層中，其中所述第一浮置P型井區整個設置於所述半導體晶粒結構的所述邊緣區域中，其中所述第一浮置P型井區整個設置於所述第三深溝槽與所述第四深溝槽之間；第二浮置P型井區，向下延伸至所述N-型漂移層中，其中所述第二浮置P型井區整個設置於所述半導體晶粒結構的所述邊緣區域中，其中所述第二浮置P型井區整個設置於所述第三深溝槽與所述第四深溝槽之間，其中所述第一深溝槽、所述第二深溝槽、所述第一浮置P型井區、所述第二浮置P型井區及所述P型主體區被設置成使得其沿著第五直線設置，其中所述第五直線自所述半導體晶粒結構的所述側邊緣垂直地延伸並橫向地延伸穿過所述第一深溝槽及所述第二深溝槽，並延伸於所述第三深溝槽與所述第四深溝槽之間，且延伸至所述半導體晶粒結構的所述主動區域中，其中所述第一浮置P型井區及所述第二浮置P型井區沿著所述第五直線設置且設置於所述P型主體區與所述第二深溝槽之間；閘極結構，至少部分地設置於所述第三深溝槽中且至少部分地設置於所述第四深溝槽中，其中所述閘極結構設置於所述半導體晶粒結構的所述主動區域中；閘極電極，耦合至所述閘極結構；汲極電極；以及源極電極，耦合至所述N+型源極區。
  2. 根據申請專利範圍第1項所述的半導體晶粒結構，其中 所述半導體晶粒結構具有頂側半導體表面，其中所述N-型漂移層包括下層部分及上層部分，其中所述N-型漂移層的所述下層部分具有較所述N-型漂移層的所述上層部分所具有的N型摻質濃度低的N型摻質濃度，其中所述N-型漂移層的所述上層部分設置於所述N-型漂移層的所述下層部分上且向上延伸至所述頂側半導體表面。
  3. 根據申請專利範圍第2項所述的半導體晶粒結構，其中所述第一深溝槽、所述第二深溝槽、所述第三深溝槽及所述第四深溝槽中的每一者延伸至所述N-型漂移層的所述下層部分中。
  4. 根據申請專利範圍第1項所述的半導體晶粒結構，其中所述閘極結構沒有延伸至所述半導體晶粒結構的所述邊緣區域中的部分。
  5. 根據申請專利範圍第1項所述的半導體晶粒結構，其中所述源極電極耦合至所述P型主體區。
  6. 根據申請專利範圍第1項所述的半導體晶粒結構，其中所述嵌入式場板結構的第一部分設置於所述第一深溝槽中，其中所述嵌入式場板結構的第二部分設置於所述第二深溝槽中，其中所述嵌入式場板結構的第三部分設置於所述第三深溝槽中，且其中所述嵌入式場板結構的第四部分設置於所述第四深溝槽中。
  7. 根據申請專利範圍第1項所述的半導體晶粒結構，其中所述嵌入式場板結構電性耦合至所述P型主體區。
  8. 根據申請專利範圍第1項所述的半導體晶粒結構，其中 所述嵌入式場板結構經由所述P型主體區電性耦合至所述源極電極。
  9. 根據申請專利範圍第1項所述的半導體晶粒結構，更包括：第三浮置P型井區，向下延伸至所述N-型漂移層中，其中所述第三浮置P型井區整個設置於所述半導體晶粒結構的所述邊緣區域中，且其中所述第三浮置P型井區整個設置於所述第一深溝槽與所述第二深溝槽之間。
  10. 根據申請專利範圍第1項所述的半導體晶粒結構，更包括：第三浮置P型井區，向下延伸至所述N-型漂移層中，其中所述第三浮置P型井區整個設置於所述半導體晶粒結構的所述邊緣區域中，其中所述第三浮置P型井區整個設置於所述第一深溝槽與所述半導體晶粒結構的所述側邊緣之間。
  11. 根據申請專利範圍第1項所述的半導體晶粒結構，其中所述第一浮置P型井區形成所述第二深溝槽的側壁的一部分。
  12. 根據申請專利範圍第2項所述的半導體晶粒結構，其中位於所述邊緣區域中的所述嵌入式場板結構是一定量的N+型多晶矽，其中所述一定量的N+型多晶矽自所述第三深溝槽向上延伸，且向上延伸於所述頂側半導體表面之上，並向下延伸至所述第四深溝槽中。
  13. 根據申請專利範圍第12項所述的半導體晶粒結構，更 包括：主體金屬層，設置於所述邊緣區域中，其中所述主體金屬層沒有延伸至所述半導體晶粒結構的所述主動區域中的部分，且其中所述主體金屬層電性耦合至位於所述邊緣區域中的所述嵌入式場板結構的所述一定量的N+型多晶矽。
  14. 一種場板功率N通道場效電晶體晶粒，具有主動區域及邊緣區域，所述場板功率N通道場效電晶體晶粒包括：源極金屬電極；周邊深溝槽，圍繞所述場板功率N通道場效電晶體晶粒的周邊延伸，其中所述周邊深溝槽中不設置閘極，其中所述周邊深溝槽設置於所述邊緣區域中，且其中所述周邊深溝槽沒有設置於所述主動區域中的部分；多個平行延伸的深溝槽，其中所述多個平行延伸的深溝槽中的每一者自所述主動區域延伸且終止於所述周邊深溝槽中；埋入式場板結構，部分地設置於所述周邊深溝槽中且部分地設置於所述多個平行延伸的深溝槽中；P型主體區，設置於所述主動區域中，其中所述P型主體區耦合至所述源極金屬電極；N+型源極區，向下延伸至所述P型主體區中；以及多個浮置P型井區，其中所述多個浮置P型井區中的每一者整個設置於所述邊緣區域中，其中直線自所述邊緣區域延伸且延伸至所述主動區域，且其中所述多個浮置P型井區沿著所述直線 設置於所述周邊深溝槽與所述主動區域之間。
  15. 根據申請專利範圍第14項所述的場板功率N通道場效電晶體晶粒，其中沿著所述直線在所述周邊深溝槽與所述P型主體區之間的任何位置處不設置額外的P型主體區。
  16. 根據申請專利範圍第14項所述的場板功率N通道場效電晶體晶粒，更包括：閘極結構，其中所述閘極結構整個設置於所述主動區域中，且其中所述閘極結構沒有延伸至所述邊緣區域中的部分。
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