CN110277452B - 嵌入式场极板场效应晶体管 - Google Patents

嵌入式场极板场效应晶体管 Download PDF

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CN110277452B
CN110277452B CN201910125073.6A CN201910125073A CN110277452B CN 110277452 B CN110277452 B CN 110277452B CN 201910125073 A CN201910125073 A CN 201910125073A CN 110277452 B CN110277452 B CN 110277452B
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deep trench
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semiconductor die
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die structure
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CN110277452A (zh
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K·W·索科
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IXYS LLC
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及嵌入式场极板场效应晶体管。沟槽N沟道场效应晶体管具有有效区域和边缘区域。第一对平行延伸的深沟槽与管芯的侧边缘平行延伸。第二对平行延伸的深沟槽与侧边缘垂直地朝向侧边缘延伸，使得第二对的每个沟槽终止到第一对的内侧深沟槽中。嵌入式场极板结构嵌入在这些沟槽中。多个浮动P型阱区整体布置于第二对深沟槽之间，在有效区域与第一对的内侧深沟槽之间。使用这种边缘区域结构，因为与不具有浮动P型阱区的相同结构相比较，边缘区域的击穿电压增加，所以总体设备的击穿电压BVDSS增加。

Description

嵌入式场极板场效应晶体管
技术领域
所描述的实施例涉及功率场效应晶体管以及相关的方法。
背景技术
为了增加沟槽功率场效应晶体管(也称作功率沟槽MOSFET)首次经历雪崩击穿的漏极到源极电压，涉及“掩埋场极板”的一种类型的沟槽功率MOSFET正在普及。这种类型的沟槽功率MOSFET有各种其他名称。例如，有时也使用术语“掩埋源极”。术语“RESURF”也连同这种类型的沟槽功率MOSFET一起使用。在典型的结构中，掩埋场极板晶体管是具有特别深沟槽的沟槽MOSFET。在该深沟槽内，连同栅极一起的是垂直取向的导电掩埋场极板。这种掩埋场极板典型地布置于栅极下面，使得它沿着深沟槽的最深部分的内部侧表面而延伸。掩埋场极板，像它上面的栅极一样，由绝缘介电层与沟槽侧壁的半导体材料分离。由于这种布置，掩埋场极板沿着紧靠深沟槽外部的N-型半导体材料中的漂移区延伸并且与之相邻。该漂移区是布置于晶体管的P型主体区下面的一定量的N-型半导体材料。通过将掩埋场极板耦合到晶体管的源极电极，与不具有掩埋场极板的相同基本沟槽MOSFET结构相比较，对于给定的RDS(ON)和集成电路大小，可以增加晶体管的击穿电压BVDSS。关于这种一般晶体管结构存在许多变化。
发明内容
沟槽功率N沟道场效应晶体管管芯(die)的半导体部分具有切割到它的顶面半导体表面中的多个深沟槽。这些深沟槽的第一个在与管芯的侧边缘平行的第一直线中延伸。这些深沟槽的第二个在与第一直线平行的第二直线中延伸，使得第一深沟槽布置于第二深沟槽与管芯的侧边缘之间。这两个深沟槽平行于彼此，并且平行于管芯的侧边缘而延伸。可能存在更多这种平行延伸的深沟槽，但是至少存在这两个。另外，第三深沟槽在与管芯的侧边缘垂直的第三直线中延伸。这个第三深沟槽终止到第二深沟槽中。第四深沟槽在与管芯的侧边缘垂直的第四直线中延伸。第四深沟槽也终止于第二深沟槽中。第三深沟槽和第四深沟槽平行于彼此而延伸，并且在它们之间不存在深沟槽。沟槽功率N沟道场效应晶体管管芯也具有嵌入式场极板结构。在一个示例中，该嵌入式场极板结构的第一部分至少部分布置于第一深沟槽中，该嵌入式场极板结构的第二部分至少部分布置于第二深沟槽中，该嵌入式场极板结构的第三部分至少部分布置于第三深沟槽中，以及该嵌入式场极板结构的第四部分至少部分布置于第四深沟槽中。
当从自顶向下的角度考虑时，沟槽功率N沟道场效应晶体管管芯具有边缘区域和有效区域(active area)。边缘区域与管芯的侧边缘相邻布置。在该边缘区域中不存在栅极或者N+型源极区。另一方面，有效区域具有栅极和N+型源极区。边缘区域布置于管芯的有效区域与管芯侧边缘之间。
当从横截面侧视图的角度考虑时，管芯的半导体部分涉及底部N++型基板层。布置于N++型基板层上的是向上延伸到顶面半导体表面的N-型漂移层。这个N-型漂移层具有下层部分，和更高度掺杂的N-型上层部分。深沟槽切割成N-型上层部分并且向下延伸通过N-型上层部分，使得它们刚好穿透N-型下层部分的顶部。
在有效区域中，在第三深沟槽与第四深沟槽之间的是P型主体区。该P型主体区从顶面半导体表面向下延伸到N-型漂移层中。N+型源极区布置于有效区域中第三深沟槽与第四深沟槽之间。P型主体区也从有效区域横向地延伸(通过栅极总线线路和嵌入式场极板接地区域)并且进入边缘区域中。
沟槽功率N沟道场效应晶体管管芯具有顶面源极金属电极结构、顶面栅极金属电极结构和底面漏极金属电极结构。源极金属电极结构耦合到有效区域的一个或多个N+型源极区，并且也耦合到有效区域的一个或多个P型主体区。栅极金属电极结构耦合到有效区域的一个或多个栅极。漏极金属电极结构布置于管芯的半导体部分的底部，使得它耦合到底面半导体表面，并且与N++型基板层接触。
另外，沟槽功率N沟道场效应晶体管管芯包括第一浮动P型阱区和第二浮动P型阱区。第一浮动P型阱区从顶面半导体表面向下延伸到N-型漂移层中。它整体布置于半导体管芯结构的边缘区域中，并且整体位于第三深沟槽与第四深沟槽之间。类似地，第二浮动P型阱区从顶面半导体表面向下延伸到N-型漂移层中。它整体布置于半导体管芯结构的边缘区域中，并且整体位于第三深沟槽与第四深沟槽之间。
第一浮动P型阱区和第二浮动P型阱区被布置使得它们延伸第五直线而布置。第五直线从半导体管芯结构的侧边缘垂直地延伸，并且横贯地延伸通过第一深沟槽和第二深沟槽，并且在第三沟槽与第四沟槽之间延伸，并且进入半导体管芯结构的有效区域中。该第五线平行于第三深沟槽的第三直线并且也平行于第四深沟槽的第四直线。第一浮动P型阱区和第二浮动P型阱区沿着该第五直线布置于P型主体区与第二深沟槽之间。在一个示例中，第一浮动P型阱区是两个中的外部那个(最接近管芯侧边缘的一个)，并且这个第一浮动P型阱区形成第二深沟槽的内部侧壁的一部分。这第一浮动P型阱区和第二浮动P型阱区在它们不耦合到总体MOSFET设备的源极电极结构、漏极电极结构或者栅极电极结构的意义上是“浮动的”。在相对于源极电极结构的漏极电极结构上大电压的情况下，第一浮动P型阱区和第二浮动P型阱区用于防止边缘区域中的雪崩击穿。在一个示例中，如果没有提供一组浮动P型阱区(包括第一浮动P型阱区和第二浮动P型阱区)，那么沟槽功率N沟道场效应晶体管管芯将在边缘区域中第二深沟槽附近遭受雪崩击穿。通过提供这组浮动P型阱区，总体沟槽功率N沟道场效应晶体管管芯不在边缘区域中首先遭受雪崩击穿，而是在有效区域中首先遭受雪崩击穿。因此，增加总体晶体管设备的漏极到源极击穿电压BVDSS。
更多细节以及实施例和方法在下面的详细描述中描述。该概述不打算限定本发明。本发明由权利要求书限定。
附图说明
附随附图例示本发明的实施例，其中类似的数字指示类似的组件。
图1是根据一个新颖性方面的半导体管芯结构1的自顶向下图。
图2是示出图1的半导体管芯结构的顶面半导体表面中的深沟槽的简化自顶向下图。
图3是示出有效区域、栅极总线线路和嵌入式场极板接地区域以及边缘区域的管芯结构1的右上角部分的图。
图4是与图3类似的图，除了图4示出获得截面线C-C’的位置。
图5是沿着图3的截面线A-A’获得的横截面图。
图6是在图5中的横截面中例示的有效区域的部分的角度图。
图7是图6的结构的角度图，但是没有示出沟槽填充材料以及没有示出顶面半导体表面上面的结构。
图8是沿着图3和图4的边缘区域12的截面线C-C’获得的横截面图。
图9是图8的边缘区域的角度图。
图10是图9的结构的角度图，但是没有示出主体金属。
图11是图10的结构的角度图，但是没有示出沟槽填充材料以及没有示出顶面半导体表面17上面的结构。
图12是例示图1的半导体管芯结构的各种特征和结构的相对位置的简化自顶向下图。
图13是关于图14的作为替代的半导体管芯结构，示出击穿电压如何随着单位单元半宽度而变化的曲线图。
图14例示具有不同边缘区域结构的作为替代的半导体管芯结构。
图15是关于图16的作为替代的半导体管芯结构，示出击穿电压如何随着单位单元半宽度而变化的曲线图。
图16例示图15的曲线图所属的新颖的半导体管芯结构。
图17是示出半导体管芯结构的有效区域中另一种嵌入式场极板结构的横截面图。
图18是示出半导体管芯结构的边缘区域中另一种嵌入式场极板结构的横截面图。
具体实施方式
现在将详细地参考本发明的背景示例和一些实施例，其示例在附随附图中例示。在下面的描述和权利要求书中，当第一物体称作布置于第二物体“上面”或者“上”时，应当理解第一物体可以直接位于第二物体上，或者介于中间的物体可以存在于第一物体与第二物体之间。类似地，诸如“左”、“右”、“顶部”、“顶面”、“上”、“向上”、“下”、“向下”、“垂直”、“横向”、“横向地”、“侧面”、“下面”、“背面”、“底部”和“底面”这样的术语在本文中用来描述所描述结构的不同部分之间的相对取向，并且应当理解，所描述的总体结构可以实际地在三维空间中以任何方式取向。在下面的描述中，N型硅可以通常简单地称作N型硅或者它可以更加具体地称作N++型硅、N+型硅、N型硅或者N-型硅。N++、N+、N和N-标识打算以粗略的一般意义标出掺杂物浓度的相对范围。例如，在描述为N-型硅的硅与描述为N型硅的硅之间可能存在浓度范围的重叠。N+型硅范围的底部的掺杂物浓度可能低于N型硅范围的顶部的掺杂物浓度。在本专利文献中也采用描述P型硅的相同方式(以有时更加具体地称作P++型硅、P+型硅、P型硅或者P-型硅的术语)。
图1是根据一个新颖性方面的半导体管芯结构1的自顶向下图。这个半导体管芯结构1是嵌入式场极板N沟道场效应晶体管管芯，也称作EFP MOSFET。“EFP”代表“嵌入式场极板”。当从自顶向下的角度考虑管芯结构时，半导体管芯结构1具有四个外围侧边缘2-5。管芯结构的顶上是源极金属电极结构26的一部分、金属栅极电极结构25、作为金属栅极结构25的一部分的栅极垫7、主体金属结构27以及金属止耗环(未示出)。金属止耗环是环绕主体金属结构并且沿着管芯结构的外围侧边缘延伸的另一个金属环。
在这个布局中，栅极电极结构位于主体金属与源极电极之间，以便能够使得栅极电极结构成为环路。使得栅极电极结构具有环路形状促进更加均匀的栅极信号分布。另外，如果雪崩击穿在边缘区域中发生，源极金属与主体金属之间的分离将在这个电流路径中提供一些电阻，这是期望的并且提高设备强度。
图2是图1的半导体管芯结构1的简化的自顶向下图，除了在图2的例示中，没有示出顶侧半导体表面的级别以上的结构。图2中所示为白色的管芯结构的部分是顶侧半导体表面。阴影部分是多个深沟槽以及它们中的任何结构，诸如嵌入式场极板。特别注意的是第一外围深沟槽6。这个第一外围深沟槽6与管芯结构的右侧边缘2平行地在例示中垂直维度上在第一直线中延伸。参考数字7指示第二外围深沟槽。该第二外围深沟槽7围绕管芯的边缘延伸，但是在第一外围深沟槽6内侧。该第二外围深沟槽7沿着管芯结构的右侧边缘2在第二直线中延伸。参考数字8识别第三深沟槽。该第三深沟槽8在第三直线中延伸。它的左端在管芯结构的左侧进入深沟槽7中的位置终止。它的右端在管芯结构的右侧进入深沟槽7中的另一个位置终止。类似地，第四深沟槽9在直线中延伸。它的左端在管芯结构的左侧进入深沟槽7中的位置终止。它的右端在管芯结构的右侧进入深沟槽7中的另一个位置终止。第三深沟槽8和第四深沟槽9如所例示跨越管芯的中心部分彼此平行地延伸。深沟槽8和9称作单独的深沟槽，即使三个沟槽7、8和9实际地融合在一起形成单个深沟槽结构。深沟槽在
图2中例示为相当宽，以便使得例示清晰。实际上，存在许多更多水平延伸的深沟槽，并且这些深沟槽比所例示的沟槽窄得多。不仅深沟槽比图2中例示的沟槽窄得多，而且在深沟槽的相邻沟槽之间也存在小得多的间隔。位于每个深沟槽中心的是嵌入式场极板结构。这种嵌入式场极板结构在图2中没有示出。另外，在管芯结构的有效区域10中，存在栅极结构以及没有例示的向上延伸到顶侧半导体表面17的其他结构。这些其他结构在图2中没有示出以便简化图。
图3是管芯结构1的右上角部分的图。在该图中，示出更多的深沟槽并且所示的深沟槽具有更加紧密的间距。提供该图以指出三个区域，也就是有效区域10，栅极总线线路和嵌入式场极板接地区域11，以及边缘区域12。截面线A-A’是在有效区域10的左侧获得的截面线。截面线B-B’是在边缘区域12的底侧获得的截面线。
图4是与图3相类似的图，除了图4示出在那里获得截面线C-C’。截面线C-C’在边缘区域12的左侧获得。
图5是沿着图3的截面线A-A’获得的横截面图。所示在左侧的深沟槽是第三深沟槽8。所示在右侧的深沟槽是第四深沟槽9。栅极结构13的部分13A延伸到左侧的第三深沟槽8中，并且栅极结构13的部分13B延伸到右侧的第四深沟槽9中。栅极结构13的这些部分13A和13B是N+型多晶硅的特征。总体栅极结构由参考数字13识别。参考数字14A和14B识别嵌入式场极板结构14的部分。如果管芯上任何位置的深沟槽在顶侧半导体表面处的横截面中观看，那么存在就像图5的例示中部分14A和14B那样出现的嵌入式场极板结构14的部分。嵌入式场极板结构14是N+型多晶硅的结构。N-型漂移层15布置于N++型基板层16上。N++型基板层16是单晶晶片材料，而N-型驱动层典型地是外延硅。
N-型漂移层15又包括下层部分15A和上层部分15B。N-型漂移层的上层部分15B比N-型漂移层的下层部分15A具有更高的N型掺杂物浓度。N-型漂移层15标注为始终向上延伸到顶侧半导体表面17，因为它向上延伸到例示平面的外部的这个表面。深沟槽从顶侧半导体表面17向下延伸，并且延伸通过N-型漂移层的上层部分15B，并且延伸到N-型漂移层的下层部分15A的顶部中。参考数字32识别深沟槽中的绝缘介电材料。该绝缘介电材料32典型地是热氧化硅。该绝缘介电材料32将深沟槽的半导体侧壁与栅极结构13的部分以及与嵌入式场极板结构14的部分分离。参考数字18识别底侧半导体表面。P型主体区如所示从顶侧半导体表面17向下延伸。图5右侧的参考数字19识别P型主体区的一个。一组N+型源极区如所示从顶侧半导体表面17向下延伸到P型主体区中。这些N+型源极区的一个由参考数字20识别。当从自顶向下的角度考虑时，这些N+型源极区具有阶梯形状。阶梯形状涉及两个平行延伸的边，以及一组跨越梯级。源极金属结构26在它的梯级区域耦合到这种N+型源极区的顶部。源极金属电极26与N+型源极区之间的这些连接点在图5的特定横截面中不存在。另外，源极金属电极结构26也由P+型主体接触区耦合到P型主体区。例如，源极金属结构26在图5的右侧由P+型主体接触区22耦合到P型主体区19。绝缘介电特征23A和23B将源极金属电极26与栅极结构13分离。位于管芯结构的顶部上的栅极总线线路和电极25结构(参看图1)在图5的特定横截面中看不到，但是栅极总线线路结构25由管芯上其他位置的连接而耦合到栅极结构13的N+型多晶硅。漏极金属电极结构24布置于底侧半导体表面18上。
当高于晶体管设备的阈值电压的正电压相对于源极金属电极26置于栅极结构13上时，那么导电沟道在与栅极结构相邻的沟槽的边缘处形成。这个沟道从N+型源极区垂直向下延伸，通过P型主体区，并且到达N-型漂移层15的底层N-型材料。在源极到漏极电压的影响下，电子可以从N+型源极区垂直向下流动通过这个导电沟道，并且到达N-型漂移层15，通过N-型漂移层15，并且通过N++型基板层16，并且到达漏极金属电极24。例如，在N+型源极区20的情况下，沟道由箭头28例示。
当在如图5的情况下的横截面中考虑深沟槽时，深沟槽内的嵌入式场极板从顶侧半导体表面17处或者非常接近顶侧半导体表面17的开始点开始向下延伸，并且向下延伸通过深沟槽的中心，到达与N-型漂移层15的上层部分15B的深度接近的深度。当在如图5的情况下的横截面中考虑深沟槽时，栅极结构具有沿着深沟槽的一个侧边缘与深沟槽的那侧上的P型主体区之间的边界向下延伸的第一向下延伸部分，并且也具有沿着深沟槽的相对侧边缘与深沟槽的那侧上的P型主体区之间的边界向下延伸的第二向下延伸部分。在图5中，参考数字13BA识别深沟槽9中的栅极结构部分的一个这种第一向下延伸部分，并且参考数字13BB识别深沟槽9中的栅极结构的一个这种第二向下延伸部分。两个向下延伸部分13BA和13BB在顶部由栅极结构的桥接部分13BC连接在一个。这个桥接部分13BC布置于顶侧半导体表面17上面，并且如图5中所示，它桥接并且跨越嵌入式场极板部分14B的顶部延伸。两个向下延伸部分13BA和13BB以及桥接部分13BC全部由N+型多晶硅的相同层做成。术语“层”在这里指连续量的多晶硅，其中该多晶硅是在同一多晶硅沉积步骤中沉积的多晶硅。在这种意义下，部分13BA、13BB和13BC是一层多晶硅。
图6是在图5中的横截面中例示的有效区域的部分的角度图。阶梯形状的N+型源极区20的两个梯级部分20A和20B在图16的结构中看到。梯级部分实际上是总体N+型源极区20的部分。
图7是图6的结构的角度图，但是没有示出沟槽填充材料以及没有示出顶侧半导体表面上面的结构。阶梯形状的N+型源极区从这个角度看到。阶梯形状的N+型源极区的梯级之间的是P+型主体接触区。
图8是沿着图3和图4的边缘区域12的截面线C-C’而获得的横截面图。漏极金属电极24、N++型基板层16以及N-型漂移层15的下层部分15A，和N-型漂移层15的上层部分15B是与图5的有效区域10的横截面中相同的结构。参考数字29、30和31识别有效区域的P型主体区的延伸。特别地，P型主体区延伸30是P型主体区50的延伸。参考数字14识别N+型多晶硅的嵌入式场极板层。这是制造图5的嵌入式场极板部分14A和14B的相同N+型多晶硅层。图8的嵌入式场极板结构和图5的嵌入式场极板结构都是相同的一定量的N+型多晶硅的不同部分。图8的顶部的主体金属27是图1中所示的相同主体金属27。参考数字32识别沟槽填充绝缘介电层的特征。这是形成图5中所示的有效区域中的沟槽填充绝缘介电特征23A和23B的相同层的沟槽填充绝缘电介质。图8的绝缘介电层33是图5的横截面中由参考数字23所识别的相同的绝缘介电层。在边缘区域12中不存在N+型源极区。在边缘区域12中不存在栅极结构。栅极结构13不延伸到边缘区域12中。
图9是边缘区域12的角度图。
图10是图9的结构的角度图，但是没有示出主体金属27。
图11是图10的结构的角度图，但是没有示出沟槽填充材料以及没有示出顶侧半导体表面17上面的结构。这个图显露许多隔离的并且浮动的P型区34-49。这些浮动P型区的每个与其他每个完全分离。这些P型区的每个是浮动的，并且不耦合到管芯的源极电极结构，也不耦合到管芯的漏极电极结构，也不耦合到管芯的栅极电极结构。当从自顶向下的角度考虑管芯结构1时，P型区46-49实际上是环绕管芯结构1的外围的同心环形。P型区44、41、38、35和30整体布置于第三深沟槽8(参看图2)与第四深沟槽9(参看图2)之间。P型区44、41、38和35整体布置于有效区域10(参看图1)与管芯的右侧边缘2(参看图1)之间。
图12是例示图1的半导体管芯结构的各种特征和结构的相对位置的简化自顶向下图。在该图的取向中，深沟槽6在与管芯的侧边缘2平行的第一直线中延伸。深沟槽7在与第一线平行的第二直线中延伸。深沟槽6和7是平行于彼此并且平行于侧边缘2延伸的一对深沟槽。深沟槽8是在第三直线中延伸的第三深沟槽。第三线与侧边缘2垂直。深沟槽9是在第四直线中延伸的第四深沟槽。第四线与第三线平行。深沟槽8和9是平行于彼此并且与侧边缘2垂直延伸的一对深沟槽。第三深沟槽8终止到第二深沟槽7中。类似地，第四深沟槽9终止到第二深沟槽7中。这些深沟槽6、7、8和9是与图2中例示的以及在上面的文本中描述的相同的深沟槽。P型区31、30和29不是浮动的，而是它们连接到有效区域中的源极金属。
嵌入式场极板结构14至少部分地布置于四个深沟槽6、7、8和9中。嵌入式场极板结构14的第一部分至少部分地布置于第一深沟槽6中。嵌入式场极板结构14的第二部分至少部分地布置于第二深沟槽7中。嵌入式场极板结构14的第三部分至少部分地布置于第三深沟槽8中。嵌入式场极板结构14的第四部分至少部分地布置于第四深沟槽9中。
P型主体区50布置于有效区域12中，但是它具有横向延伸通过栅极总线路线和嵌入式场极板接地区域11，并且延伸到边缘区域12中的延伸30。P型主体区50也整体地布置于第三深沟槽8与第四深沟槽9之间。N+型源极区51整体布置于有效区域12中以及第三深沟槽与第四深沟槽之间。栅极结构13的部分13A至少部分地布置于有效区域10中第三深沟槽8中，并且栅极结构13的部分13B至少部分地布置于有效区域10中第四深沟槽9中。栅极结构13没有延伸到管芯的边缘区域12中的部分。浮动P型区44、41、38和35的每个整体布置于第三深沟槽与第四深沟槽之间，并且整体位于管芯的边缘区域12内。图12的结构的构成部分被取向为使得P型区44、41、38、35和30沿着第五直线52而布置。第五直线52垂直于侧边缘2而延伸，并且从侧边缘2延伸，并且然后横贯地(transversely)延伸通过第一深沟槽6，并且然后横贯地延伸通过第二深沟槽7，并且然后在第三深沟槽8与第四深沟槽9之间延伸，并且延伸到管芯的有效区域12中。P型区44、41、38、35和30如图12中所例示的沿着这个第五直线52布置于侧边缘2与有效区域10之间。
图13和14例示并且说明具有不同边缘区域结构的作为替代的半导体管芯结构。不是如图12中所示具有新颖的多个浮动P型区44、41、38和35，作为替代的半导体管芯结构具有单个P型区57。这个单个P型区57从图3的A-A’截面的位置始终向外延伸到第二深沟槽7。在其他方面，作为替代的半导体管芯结构与图1的新颖的半导体管芯结构相同。图13的图的水平轴阐明半导体管芯结构的单位单元半宽度。用正方形表示的线53指示有效区域的击穿电压如何作为单位单元半宽度的函数而变化。用圆形表示的线54是指示边缘区域的击穿电压如何作为单位单元半宽度的函数而变化的模拟结果。在2.0微米的单位单元半宽度处，作为替代的半导体管芯结构被模拟在153伏特的击穿电压BVDSS下在由星星58指示的位置遭受雪崩击穿。因此，总体N沟道场效应晶体管管芯的击穿电压BVDSS低于如果设备不在它的边缘区域中首先击穿否则可能的击穿电压。总体N沟道场效应晶体管管芯的击穿电压BVDSS是2.0单位单元半宽度的位置处图13的两条线中较低的一个。
图15和图16例示并且说明新颖的半导体管芯结构1的边缘区域12的新颖结构的相对优点。用正方形表示的线55指示有效区域的击穿电压如何作为单位单元半宽度的函数而变化。用三角形表示的线56示出边缘区域的击穿电压如何作为单位单元半宽度的函数而变化。在2.0微米的单位单元半宽度时，总体半导体管芯结构的击穿电压由有效区域的击穿电压确定，因为边缘区域的击穿电压(如由线56所指示)大于有效区域的击穿电压。在2.0的单位单元半宽度的位置，线56高于线55。如图16中所示，在底侧漏极金属电极24上的167伏特电势与P型区30上的零伏特电势之间存在167伏特的大的差，但是P型区30、35、38、41和44之间的间隙仍然允许浮动区上的电势彼此不同。由于存在跨越这个距离的单个导电P型区，最左边的P型区30上的零伏特电势因此不会横向地始终向右延伸到第二深沟槽7的左边缘。而是，167伏特的差可以跨越这个横向距离而降低。P型区30、35、38、41和44上的电压分别是零伏特、六伏特、十二伏特、十八伏特和二十四伏特。这意味着在图16的结构的情况下第二深沟槽7的左边缘处的相对电压仅是143伏特，即使漏极金属电极24相对于源极金属电极26之间的167伏特的大的差。总体半导体管芯结构被模拟具有167伏特的击穿电压BVDSS。由于模拟软件的限制，线56实际上是不具有三个平面侧壁(沟槽7、8和9的侧壁)而是具有半圆柱半径侧壁结构的类似结构的模拟。
虽然为了指导的目的在上面描述某些具体的实施例，但是本专利文献的讲授具有普遍的适用性并且不局限于上面描述的具体实施例。虽然在深沟槽中示出特定的栅极结构和嵌入式场极板结构，但是在其他实施例中，使用其他栅极结构和其他嵌入式场极板结构。有效区域与外围深沟槽之间的浮动P型阱区44、41、38和35的实体不局限于特定的栅极结构/嵌入式场极板设计。在给定半导体设备内，与嵌入式场极板在边缘区域中具有的形式相比较，它可以在有效区域中具有不同的形式。例如，可以在有效区域中采用图17的结构并且可以在边缘区域中采用图18的结构。在图17的横截面中，嵌入式场极板整体布置于栅极结构的底部延伸以下。栅极结构的底部延伸处于P型主体区的底部延伸处或者稍微低于P型主体区的底部延伸。浮动P型阱区44、41、38和35同样可以采用这些类型的掩埋场极板结构。因此，可以在不背离如权利要求书中陈述的本发明的范围的情况下，实践所描述实施例的各种特征的修改、改编和组合。

Claims (13)

1.一种半导体管芯结构，具有边缘区域和有效区域，所述半导体管芯结构包括：
N-型漂移层，其中第一深沟槽向下延伸到所述N-型漂移层中，其中所述第一深沟槽在与所述半导体管芯结构的侧边缘平行的第一直线中延伸，其中第二深沟槽向下延伸到所述N-型漂移层中，其中所述第二深沟槽在与所述第一深沟槽的所述第一直线平行的第二直线中延伸，其中第三深沟槽向下延伸到所述N-型漂移层中，其中所述第三深沟槽在与所述半导体管芯的所述侧边缘垂直的第三直线中延伸并且终止到所述第二深沟槽中，其中第四深沟槽在与所述半导体管芯的所述侧边缘垂直的第四直线中延伸并且终止到所述第二深沟槽中，其中所述第一直线与所述第二直线平行，并且其中所述第三直线与所述第四直线平行；
嵌入式场极板结构，至少部分地布置于所述第三深沟槽中并且至少部分地布置于所述第四深沟槽中；
P型主体区，向下延伸到所述N-型漂移层中，其中所述P型主体区布置于所述半导体管芯结构的在所述第三深沟槽与所述第四深沟槽之间的所述有效区域中，其中所述P型主体区没有延伸到所述半导体管芯结构的所述边缘区域中的部分；
N+型源极区，向下延伸到所述P型主体区中，其中所述N+型源极区布置于所述半导体管芯结构的在所述第三深沟槽与所述第四深沟槽之间的所述有效区域中；
第一浮动P型阱区，向下延伸到所述N-型漂移层中，其中所述第一浮动P型阱区整体布置于所述半导体管芯结构的所述边缘区域中，其中所述第一浮动P型阱区整体布置于所述第三深沟槽与所述第四深沟槽之间；
第二浮动P型阱区，向下延伸到所示N-型漂移层中，其中所述第二浮动P型阱区整体布置于所述半导体管芯结构的所述边缘区域中，其中所述第二浮动P型阱区整体布置于所述第三深沟槽与所述第四深沟槽之间，其中所述第一深沟槽、所述第二深沟槽、所述第一浮动P型阱区、所述第二浮动P型阱区以及所述P型主体区被布置为使得它们沿着第五直线而布置，其中所述第五直线从所述半导体管芯结构的所述侧边缘垂直延伸并且横贯地延伸通过所述第一深沟槽和所述第二深沟槽，并且在所述第三深沟槽与所述第四深沟槽之间延伸，并且延伸到所述半导体管芯结构的所述有效区域中，其中所述第一浮动P型阱区和所述第二浮动P型阱区沿着所述第五直线而布置并且布置于所述P型主体区与所述第二深沟槽之间；
栅极结构，至少部分地布置于所述第三深沟槽中并且至少部分地布置于所述第四深沟槽中，其中所述栅极结构布置于所述半导体管芯结构的所述有效区域中；
栅极电极，耦合到所述栅极结构；
漏极电极；以及
源极电极，耦合到所述N+型源极区。
2.根据权利要求1所述的半导体管芯结构，其中所述半导体管芯结构具有顶侧半导体表面，其中所述N-型漂移层包括下层部分和上层部分，其中所述N-型漂移层的所述下层部分比所述N-型漂移层的所述上层部分具有更低的N型掺杂物浓度，其中所述N-型漂移层的所述上层部分布置于所述N-型漂移层的所述下层部分上并且向上延伸到所述顶侧半导体表面。
3.根据权利要求2所述的半导体管芯结构，其中所述第一深沟槽、第二深沟槽、第三深沟槽和第四深沟槽的每个延伸到所述N-型漂移层的所述下层部分中。
4.根据权利要求1所述的半导体管芯结构，其中所述栅极结构没有延伸到所述半导体管芯结构的所述边缘区域中的部分。
5.根据权利要求1所述的半导体管芯结构，其中所述源极电极耦合到所述P型主体区。
6.根据权利要求1所述的半导体管芯结构，其中所述嵌入式场极板结构的第一部分布置于所述第一深沟槽中，其中所述嵌入式场极板结构的第二部分布置于所述第二深沟槽中，其中所述嵌入式场极板结构的第三部分布置于所述第三深沟槽中，并且其中所述嵌入式场极板结构的第四部分布置于所述第四深沟槽中。
7.根据权利要求1所述的半导体管芯结构，其中所述嵌入式场极板结构电耦合到所述P型主体区。
8.根据权利要求1所述的半导体管芯结构，其中所述嵌入式场极板结构经由所述P型主体区电耦合到所述源极电极。
9.根据权利要求1所述的半导体管芯结构，还包括：
向下延伸到所述N-型漂移层中的第三浮动P型阱区，其中所述第三浮动P型阱区整体布置于所述半导体管芯结构的所述边缘区域中，并且其中所述第三浮动P型阱区整体布置于所述第一深沟槽与所述第二深沟槽之间。
10.根据权利要求1所述的半导体管芯结构，还包括：
向下延伸到所述N-型漂移层中的第三浮动P型阱区，其中所述第三浮动P型阱区整体布置于所述半导体管芯结构的所述边缘区域中，其中所述第三浮动P型阱区整体布置于所述第一深沟槽与所述半导体管芯结构的所述侧边缘之间。
11.根据权利要求1所述的半导体管芯结构，其中所述第一浮动P型阱区形成所述第二深沟槽的侧壁的一部分。
12.根据权利要求2所述的半导体管芯结构，其中所述边缘区域中的所述嵌入式场极板结构是一定量的N+型多晶硅，其中所述一定量的N+型多晶硅从所述第三深沟槽向上延伸，并且向上且在所述顶侧半导体表面上方以及向下到所述第四深沟槽中。
13.根据权利要求12所述的半导体管芯结构，还包括：
布置于所述边缘区域中的主体金属层，其中所述主体金属层没有延伸到所述半导体管芯结构的所述有效区域中的部分，并且其中所述主体金属层电耦合到所述边缘区域中所述嵌入式场极板结构的所述一定量的N+型多晶硅。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210202470A1 (en) * 2019-12-31 2021-07-01 Nami MOS CO., LTD. Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed
JP7094611B2 (ja) * 2020-09-18 2022-07-04 サンケン電気株式会社 半導体装置
EP4113623A1 (en) * 2021-07-01 2023-01-04 Infineon Technologies Austria AG Transistor device
WO2024054763A1 (en) * 2022-09-09 2024-03-14 Semiconductor Components Industries, Llc Semiconductor device termination structures and methods of manufacturing semiconductor device termination structures
JP2024043638A (ja) * 2022-09-20 2024-04-02 株式会社東芝 半導体装置およびその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832234A (zh) * 2012-09-10 2012-12-19 张家港凯思半导体有限公司 一种沟槽型半导体功率器件及其制造方法和终端保护结构
WO2016014224A1 (en) * 2014-07-25 2016-01-28 United Silicon Carbide, Inc. Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same
JP2016062981A (ja) * 2014-09-16 2016-04-25 株式会社東芝 半導体装置及びその製造方法

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2581252B1 (fr) * 1985-04-26 1988-06-10 Radiotechnique Compelec Composant semiconducteur du type planar a structure d'anneaux de garde, famille de tels composants et procede de realisation
US7652326B2 (en) * 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US20070291175A1 (en) * 2006-06-19 2007-12-20 Mediatek, Inc. Display system, tv receiver, and method for reminding a schedule
US9252251B2 (en) * 2006-08-03 2016-02-02 Infineon Technologies Austria Ag Semiconductor component with a space saving edge structure
JP2008124346A (ja) * 2006-11-14 2008-05-29 Toshiba Corp 電力用半導体素子
DE102009005914B4 (de) * 2008-01-28 2014-02-13 Denso Corporation Halbleitervorrichtung mit Halbleiterelement mit isoliertem Gate und bipolarer Transistor mit isoliertem Gate
CN102318045B (zh) * 2008-02-14 2014-08-06 马克斯半导体股份有限公司 改良式击穿电压的边缘端点
US8415739B2 (en) * 2008-11-14 2013-04-09 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture
US8304829B2 (en) * 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8174067B2 (en) * 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US7879686B2 (en) * 2009-01-16 2011-02-01 Infineon Technologies Austria Ag Semiconductor device and method for manufacturing
US8372717B2 (en) * 2009-12-28 2013-02-12 Force Mos Technology Co., Ltd. Method for manufacturing a super-junction trench MOSFET with resurf stepped oxides and trenched contacts
US8546893B2 (en) * 2010-01-12 2013-10-01 Mohamed N. Darwish Devices, components and methods combining trench field plates with immobile electrostatic charge
US9117739B2 (en) * 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
JP5925991B2 (ja) * 2010-05-26 2016-05-25 三菱電機株式会社 半導体装置
US8476136B2 (en) * 2010-12-14 2013-07-02 Stmicroelectronics S.R.L. Method and a structure for enhancing electrical insulation and dynamic performance of MIS structures comprising vertical field plates
JP5661583B2 (ja) * 2011-09-21 2015-01-28 株式会社東芝 半導体装置の製造方法
US8975662B2 (en) * 2012-06-14 2015-03-10 Infineon Technologies Austria Ag Method of manufacturing a semiconductor device using an impurity source containing a metallic recombination element and semiconductor device
JP2014146666A (ja) * 2013-01-28 2014-08-14 Toshiba Corp 半導体装置
US9431392B2 (en) * 2013-03-15 2016-08-30 Infineon Technologies Austria Ag Electronic circuit having adjustable transistor device
JP6177154B2 (ja) * 2013-07-16 2017-08-09 株式会社東芝 半導体装置
US9761702B2 (en) * 2014-02-04 2017-09-12 MaxPower Semiconductor Power MOSFET having planar channel, vertical current path, and top drain electrode
CN103779399A (zh) * 2014-02-20 2014-05-07 西安芯派电子科技有限公司 一种具有超结结构的半导体器件
US9761676B2 (en) * 2014-03-26 2017-09-12 Infineon Technologies Americas Corp. Power semiconductor device with embedded field electrodes
JP6420175B2 (ja) * 2014-05-22 2018-11-07 ルネサスエレクトロニクス株式会社 半導体装置
US20160020279A1 (en) * 2014-07-18 2016-01-21 International Rectifier Corporation Edge Termination Using Guard Rings Between Recessed Field Oxide Regions
US9553184B2 (en) * 2014-08-29 2017-01-24 Nxp Usa, Inc. Edge termination for trench gate FET
US9472662B2 (en) * 2015-02-23 2016-10-18 Freescale Semiconductor, Inc. Bidirectional power transistor with shallow body trench
US11257944B2 (en) * 2015-04-27 2022-02-22 Rohm Co., Ltd. Semiconductor device and semiconductor device manufacturing method
DE102015106790B4 (de) * 2015-04-30 2020-08-06 Infineon Technologies Austria Ag Halbleitervorrichtung und Trench-Feldplatten-Feldeffekttransistor mit einem thermisch gewachsene und abgelagerte Teile aufweisenden Felddielektrikum
JP6666671B2 (ja) * 2015-08-24 2020-03-18 ローム株式会社 半導体装置
US10388783B2 (en) * 2016-02-17 2019-08-20 Polar Semiconductor, Llc Floating-shield triple-gate MOSFET
JP2017162939A (ja) * 2016-03-08 2017-09-14 株式会社東芝 半導体装置
US9818828B2 (en) * 2016-03-09 2017-11-14 Polar Semiconductor, Llc Termination trench structures for high-voltage split-gate MOS devices
JP6801324B2 (ja) * 2016-09-15 2020-12-16 富士電機株式会社 半導体装置
CN107403839B (zh) * 2017-07-25 2023-06-06 无锡新洁能股份有限公司 适用于深沟槽的功率半导体器件结构及制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832234A (zh) * 2012-09-10 2012-12-19 张家港凯思半导体有限公司 一种沟槽型半导体功率器件及其制造方法和终端保护结构
WO2016014224A1 (en) * 2014-07-25 2016-01-28 United Silicon Carbide, Inc. Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same
JP2016062981A (ja) * 2014-09-16 2016-04-25 株式会社東芝 半導体装置及びその製造方法

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