TWI720306B - 不同厚度晶粒之晶圓接合的方法 - Google Patents

不同厚度晶粒之晶圓接合的方法 Download PDF

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TWI720306B
TWI720306B TW107112358A TW107112358A TWI720306B TW I720306 B TWI720306 B TW I720306B TW 107112358 A TW107112358 A TW 107112358A TW 107112358 A TW107112358 A TW 107112358A TW I720306 B TWI720306 B TW I720306B
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尚恩 基爾科因
艾瑞克 米勒
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美商雷神公司
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Abstract

用於將一或多個可具有不同厚度之晶粒接合至晶圓的方法、組件、及設備被敘述。該晶粒可被加工及切割，並設有保護免於晶圓切成小方塊及處理碎物之平面化氧化物層及連接至積體電路的一或多個金屬化支柱結構。該晶粒之正面被接合至第一操作晶圓，使得該個別支柱結構係在共同平面中對齊。該被接合晶粒的基板材料背面接著被薄化至均勻之厚度及接合至第二操作晶圓。該組件可接著被翻轉，且該第一操作晶圓及保護層包括被移除的潛在切成小方塊及處理碎物。該支柱結構被顯露，導致包括該第二操作晶圓及一或多個被安裝至其上之均勻地薄化的晶粒之合成晶圓組件。

Description

不同厚度晶粒之晶圓接合的方法
相關申請案，本申請案主張對2017年4月13日提出之美國臨時申請案第62/485,173號的優先權及此臨時申請案之利益，其用於所有目的係全部以引用的方式併入本文中。
本揭示內容大致上有關積體電路(ICs)、半導體裝置及其他小型化裝置的加工，且更特別地是有關最佳化涉及不同高度晶粒之晶粒至晶圓接合製程的良率。
IC加工中之趨勢已是不同尺寸ICs的互連、在不同尺寸晶圓上加工、及提供不同功能(亦即，類比、數位、光學)及材料。該ICs能在堆疊之前被測試，以允許已知合格晶粒(KGD)被結合，以改善良率。比較於與在晶片區域上增加IC或系統有關聯的良率及成本，此垂直堆疊及垂直互連方式之經濟上的成功取決於該堆疊及互連的良率及成本係有利的。用於實現此方式之製造方法係使用直接接合雜化(DBH)垂直地堆疊ICs，以於晶圓之間形成共價接合。
垂直堆疊及垂直互連的一版本係在此ICs(基板上)以晶粒至晶圓(D2W)之格式被接合，在此晶粒係IC側向下地接合至IC側向上的共同晶圓，以允許已知合格晶粒之堆疊，以改善良率。為了造成製造IC的成本盡可能地小，複合半導體裝置(GaAs、InP、GaN等)之很多情況可同時在典型為100毫米直徑的小半導體晶圓上被加工。典型之晶圓代工廠ICs係在200毫米直徑矽晶圓上加工。為利用與來自小晶圓的裝置接合之DBH晶圓，該等裝置需要被切割成晶粒，且接著被接合至200毫米晶圓。晶片切成小方塊係將晶圓分開成多數個別晶粒的製程，且典型涉及鋸條、化學藥品、雷射、或其組合之使用，以切穿及沿著 延伸於配置在該晶圓上的多數裝置間之鋸口區域。晶片切成小方塊能留下偏差，其可於以下接合製程中轉換成良率低下的空隙。由於切單顆期間所產生之此等微粒及由於處理限制(亦即，為了不會將其打破地處理晶圓，該晶圓將具有至少700微米的厚度)而未能重新拋光(例如CMP)該晶粒之接合表面，D2W接合係典型很低良率。此外，含有超過一晶粒的多晶片模組之製造商正因為其小巧性及處理功率而變得很受人歡迎。此封裝的製造商總是正尋求減少此等封裝之尺寸或厚度的方式。減少此封裝之厚度的一方式係使用盡可能薄之晶粒。
雖然很多用於使整個晶圓變薄的方法存在，其係接著全部地被使用，很少用於使個別晶粒變薄之方法存在。如此，所需要者係D2W製造製程，其容納不同尺寸設計、切割晶粒的使用，並克服目前限制。
按照某些實施例，技術被提供，用於將可具有不同厚度之複數個晶粒接合至共同晶圓(例如具有約200毫米的直徑)。該晶粒可包含由不同裝置晶圓(例如具有約100毫米之直徑)及平面化氧化物層所加工及切割的直接接合雜化(DBH)裝置結構。每一被切割之晶粒具有正面、基板材料背面、及厚度。每一晶粒正面包括該平面化氧化物層，其保護一或多個連接至該晶粒中所形成的裝置結構之金屬化支柱結構。
複數個晶粒的每一者可為正面(電路側)向下地接合至第一操作晶圓之前面，使得與每一晶粒有關聯的金屬化支柱結構位在一共同平面中。該複數個晶粒可在該x-y方向中與精確地對齊取放儀器。該被黏合之複數個晶粒的材料基板背面可被薄化至均勻之厚度(例如經過晶背研磨及/或CMP等)，且二氧化矽層可被沈積接合在該薄化晶粒背面上及在該第一操作晶圓的暴露表面上。該均勻地薄化之複數個晶粒的背面可接著被接合至第二操作晶圓之前面。該第一操作可接著被移除，且該平面化氧化物層可被由該複數個致均勻地薄化的晶粒之每一正面移除，以顯露該一或多個金屬化支柱結構。
於某些實施例中，該晶粒的一或多個可呈現潛在偏差之 區域，其能導致於接合步驟中良率低下的空隙，在此該等區域源自來自其個別裝置晶圓之晶粒的切成小方塊。該等區域大致上被設置在鄰接每一晶粒中之一或多個金屬化支柱結構的平面中(且在該等支柱結構與該臨時晶圓組件結構中之晶粒接合的第一操作晶圓之間)。該等區域不會負面地影響該晶粒的正面接合至該第一操作前面，且有利地係，該等區域將被移除，而具有與每一晶粒相關聯之保護平面化氧化物層。這顯著地增加該製程的良率，其中已知合格晶粒可在該最後合成之晶圓結構中被接合。
於一實施例中，該製程另包括不同裝置晶圓上的晶粒裝置結構之加工、以相關聯的氧化物層保護該晶粒裝置結構之每一者、及切割該晶粒。該裝置晶粒的至少一者可為複合半導體裝置(例如GaAs、InP、GaN等)。藉由應用低溫氧化物接合製程(諸如在美國專利第8,053,329號中所敘述之接合，其內容係以引用的方式併入本文中)、藉由DBH接合、或藉由在該均勻薄化的晶粒背面及第一與第二操作前面之間施加黏接劑，該第一及/或第二操作前面可被接合至該晶粒。該第一及/或第二操作前面可藉由薄化被移除，所得到者在該裝置晶粒的暴露中用於該第二操作前面。
在另一實施例中，於薄化之前，該晶粒之背面的均勻薄化可選擇性地在藉由以強度增強的聚合材料充填被接合至該第一操作前面的每一晶粒之間的間隙之前，以幫助維持該晶粒於譬如CMP處理期間的相對定位。然後，該聚合充填材料可在薄化之後、於沈積接合該SiO2層之前、或在移除該第一操作晶圓之後被移除。
20、25、30、35、40、45、50、55、60、65‧‧‧步驟
100a‧‧‧晶粒
100b‧‧‧晶粒
100c‧‧‧晶粒
102a‧‧‧厚度
102b‧‧‧厚度
102c‧‧‧厚度
106a‧‧‧正面
106b‧‧‧正面
106c‧‧‧正面
108a‧‧‧背面
108b‧‧‧背面
108c‧‧‧背面
110a‧‧‧整合裝置結構
112a‧‧‧支柱結構
112b‧‧‧支柱結構
112c‧‧‧支柱結構
114a‧‧‧平面化氧化物層
114b‧‧‧平面化氧化物層
114c‧‧‧平面化氧化物層
116a‧‧‧區域
116b‧‧‧區域
116c‧‧‧區域
118‧‧‧第一矽操作晶圓
120‧‧‧前面
122‧‧‧背面
124‧‧‧氧化物層
126‧‧‧共同平面
130‧‧‧材料
132‧‧‧間隙
134‧‧‧位準
136‧‧‧想要高度
140‧‧‧三防漆
142‧‧‧第二操作晶圓
144‧‧‧中介晶圓組件
150‧‧‧聚合物充填料
本揭示內容之至少一實施例的各種態樣係在下面參考所附圖面被討論。其將被了解為了說明的簡單及清楚之故，被顯示在該等圖面中的元件已不需被精確地或按一定比例畫出。譬如，用於清楚之故，部份該等元件之尺寸可相對其他元件被誇大，或數個物理零組件可被包括在一說明元件中。再者，在被適當考慮之處，參考數字可在該等圖面之中被重複，以指示對應或類似的步驟或零組件。用於清楚之目的，並非每一零組件可在每一圖示中被標明。該等圖面被提 供用於說明及解釋之目的，且係不意欲為本發明之限制的定義。在該等圖面中：圖1係根據說明性實施例用於不同厚度晶粒之晶粒至晶圓接合的方法之流程圖。
圖2概要地說明將不同高度的晶粒接合(黏合)至第一操作晶圓之步驟；圖3概要地說明以聚合材料充填晶粒間之間隙的步驟；圖4概要地說明晶背研磨及/或CMP之步驟，以將所有晶粒厚度設定至均勻的位準；圖5概要地說明將第二操作晶圓接合(黏合)至該晶粒之背面的步驟；圖6概要地說明將該晶圓結構翻轉至較佳方位及移除該第一操作晶圓之步驟；及圖7概要地說明由該晶粒移除保護性平面化氧化物層及潛在的碎物區域、並顯露該裝置晶粒支柱結構之步驟。
於以下詳細敘述中，極多特定細節被提出，以便提供本揭示內容的態樣之完全理解。其將被那些普通熟習該技術領域所了解，這些可沒有部分這些特定細節而被獨立地實踐。在其他情況中，熟知方法、程序、零組件及結構可能尚未被詳細地敘述，以便不會使該等實施例模糊不清。較佳實施例的以下敘述本質上係僅只示範的，且絕無意欲限制該揭示內容、其應用、或使用。其亦將被了解在此中所採用之措辭及用語係只用於敘述之目的，且將不被當作限制。其被了解為清楚之故，某些特色就分開實施例的情況被敘述，但亦可組合地被提供於單一實施例中。反之，為簡潔之故，就單一實施例的情況敘述各種特色，但亦可被分開地提供或於任何合適之子組合中。
沒有在此中所使用的元件、動作、或指令應被解釋為重要或本質上的，除非如此明確地敘述。亦如在此中所使用，該等物件“一(a)”及“一(an)”係意欲包括一或多個項目，並可與“一或多個”被交替地使用。再者，該片語“基於”係意欲意指“至少局部地基 於”，除非以另外之方式明確地陳述。其將被進一步了解該“包含”(及包含的任何形式，諸如“包含(comprises)”及“正包含(comprising)”)、“具有”(及具有之任何形式，諸如“具有(has)”、及“正具有(having)”)、“包括”(及包括的任何形式，諸如“包括(includes)”、及“正包括(including)”)、及“含有”(及含有之任何形式，諸如“含有(contains)”、及“正含有(containing)”)等詞係無限制的連綴動詞。其結果是，“包含,”、“具有,”、“包括,”、或“含有”一或多個步驟或元件之方法、結構或裝置擁有那些一或多個步驟或元件，但不被限制於只擁有那些一或多個步驟或元件。再者，以某一方式被建構來的裝置或結構係以至少該方式所建構，但亦能以未被列出之方式所建構。
用於下文敘述之目的，該“上”、“下”、“直立”、“水平”、“前面”、“背面”及其衍生詞將有關所揭示之結構及方法，如該等圖示中所導向。該“頂部上”、“鄰接”、“被定位在...上”或“被定位在...頂部上”意指該第一元件、諸如第一結構為存在第二元件、諸如第二結構上或接近第二元件、諸如第二結構，其中諸如介面結構的介入元件可為存在該第一元件及該第二元件之間。該“直接接觸”一詞意指諸如第一結構的第一元件、及諸如第二結構之第二元件被連接，而在該二元件的介面沒有任何中間傳導、絕緣或半導體層。
參考圖1，說明有一示範接合製程10，用於將複數個具有不同厚度之已知合格晶粒安裝至一操作晶圓成為3D堆疊，且接著藉由在單一晶圓位準均勻厚度薄化製程中薄化該晶粒的背面來校正晶圓厚度變動。如在此中所使用，該“晶粒”一詞被使用於意指小塊半導體材料，其已被加工(例如DBH接合處理等)具有一電路。該“基本技術晶圓”被使用於意指積體電路、半導體裝置、及其他小型化裝置，包括、但不限於CMOS、光電子裝置、紅外線偵測器、MEMS、與類似者等，其典型具有大約200毫米之直徑。該“裝置晶圓”一詞被使用於意指積體電路、半導體裝置、及其他小型化裝置的加工中所使用之半導體材料的薄片，其具有比基本技術晶圓之直徑較小的直徑、典型大約 100毫米。該“操作晶圓”一詞被使用於意指一晶圓，其當它們被處理及薄化時對其他零組件(例如被切割之晶粒)提供機械式支撐。於大部分晶粒至晶圓(D2W)應用中，電子零組件在諸階段中被製成於一或多個裝置晶圓上及在基本技術晶圓上。用於不同尺寸的裝置晶圓及/或不同材料，裝置晶圓被切成小方塊，且該被切割之晶粒係對齊與接合至承接基本技術晶圓的晶粒位址上。傳統技術係很低良率，由於該被切割晶粒由切成小方塊及處理拾取碎物及不能被清潔或準備用於接合之事實，既然該晶粒不能被載入至用於最後拋光的CMP工具上。在接合至可被清潔及拋光的矽操作晶圓、及移除晶圓區域之後，所揭示的技術藉由薄化該晶粒克服此障礙，在此晶圓區域可含有此碎物。
包含(例如矽)以均勻地薄化之KGD填充的操作晶圓之合成結構可為藉由接合方法10所加工，其能以加工一裝置晶圓及第一與第二矽操作晶圓的選擇性步驟20及切割該晶粒之步驟25開始。然後，方法10以步驟30將該晶粒暫時地接合至該第一矽操作晶圓的前面來繼續，使得該晶粒之裝置支柱結構係於一共同平面中對齊，而包括均勻地薄化該接合晶粒的背面之步驟35，其可包括以機械式穩定性之強化聚合材料(例如BCB、聚醯亞胺、PR等)充填該接合晶粒間之間隙的選擇性步驟40，將二氧化矽層沈積接合至薄化晶粒之背部(背面)及第一操作晶圓的前面之暴露表面積的步驟45，將該薄化晶粒之背面接合至該第二操作晶圓的前面之步驟50，移除該第一操作晶圓的步驟55，及顯露該晶粒之裝置支柱結構的步驟60，在此用於顯露該裝置支柱結構之製程包括可含有切單顆及處理碎物的潛在切單顆偏差之區域的移除。這些個別步驟係在下文參考圖2-7更詳細地敘述。此外，每標準處理之選擇性進一步的晶圓接合可譬如在該最後之合成結構加工步驟65之後被施行至基本技術晶圓。
圖2-7概要地顯示用於生產合成結構的方法或製程，該合成結構包含按照方法10以均勻地薄化之已知合格晶粒佔據的(例如矽)操作晶圓。用於易於討論，圖2-7可被考慮為大致上對應於圖1之方法10中所提出的步驟之連續個別製程步驟。
如於圖2中所顯示，具有可變(例如大於5μm)厚度 102a-102c的一或多個晶粒100a-100c能以該技術領域中習知之方式在一或多個裝置晶圓上事先被加工及切割。代表性晶粒100a包括正面(電路側)106a、基板材料背面108a、整合裝置結構110a(例如DBH結構)、對該整合裝置結構提供互連的一或多個金屬化支柱結構112a、及覆蓋該支柱結構112a之保護性平面化氧化物層114a。在該平面化氧化物層114a內者可為潛在切單顆及/或處理碎物的區域116a，但用於其隨後藉由該目前揭示方法10之移除，由於未能適當地CMP該合成晶粒結構，將以別的方式導致接合空隙及於接合強度中之晶粒至晶粒變化性。包括前面120、背面122、及在該前正面120的氧化物層124之第一矽操作晶圓118亦可已事先被加工。該晶粒100a-100c的正面106a-106c及該第一操作晶圓118之前面120可被製備及暫時地接合，使得該個別支柱結構112a-112c係在共同平面126中對齊。該晶粒100a-110c可使用取放儀器在該x-y平面126中被精確地對齊，並可已事先被測試為已知合格晶粒。該晶粒背面108a-108c的最後Z軸對齊將藉由研磨及CMP被達成。該晶粒100a-100c可被接合至第一操作晶圓118之前面120，並可藉由在該正面106a-106c及第一晶圓前面120之間施加暫時的黏接劑(及適當之熱及力量)，允許黏合至其上，或藉由類似技術，經過低溫氧化物接合製程(例如藉由加州聖荷西市之Tessera技術公司所提供的ZiBond®接合)被達成。該暫時性黏接劑可包含耗蝕性黏接劑、熱塑性、熱硬化、及UV硬化黏接劑，並可藉由旋轉塗佈、或其他習知技術被施加。
將該晶粒100a-100c暫時性接合至該第一操作晶圓118提供需要之支撐，以便允許用於該晶粒背面108a-108c的薄化及處理，而不會破壞、弄彎或摺疊該晶粒。參考圖3，選擇性地，如果額外之機械式強化被需要，聚合材料130可被使用來將該晶粒100a-100c間之間隙132暫時地充填至大約等於該晶粒100a-100c的最後想要高度之位準134。此步驟可需要退火(例如150℃)，以固定該材料130的位置。如可在圖4中被看見，晶背研磨及CMP可被施加至該背面108a-108c，以將該晶粒100a-100c薄化至該最後之想要高度136。該研磨及薄化由該晶粒100a-100c的背面108a-108c移除該基板材料，直至想要之厚度(例如40μm)被達成。該晶粒厚度較佳地是被控制至在1μm內，以能夠有高良 率接合。如果聚合物充填材料130已被採用，其可由該晶圓組件被移除(例如經過加熱激活)。
參考圖5，晶粒100a-100c的薄化背面108-108c及該第一操作晶圓118之前面120的暴露表面136可被製備具有保護性三防漆140、諸如用於矽晶圓之二氧化矽塗層。第二操作晶圓142可接著被暫時地接合至晶粒100a-100c的經製備、平面化背面108a-108c。當被使用於將該第一晶圓操作118接合至該晶粒100a-100c時，類似接合製程可被採用。
如圖6中所顯示，中介晶圓組件144可被翻轉至較佳方位，以允許在該第一操作晶圓118上之處理。晶背研磨及CMP可接著被施加，以由該組件移除該第一操作晶圓118，導致覆蓋該支柱結構112a-112c的保護性平面化氧化物層114a-114c之暴露。如已注意者，在該平面化氧化物層114a-114c內者可為潛在切單顆及/或處理碎物的區域116a-116c。參考圖7，如果需要，另一聚合物充填料150可於晶背研磨及CMP該晶粒之正面106a-106c上的保護性平面化氧化物層114a-114c之前被施加至該等間隙132，以便移除該平面化氧化物層114a-114c及潛在碎物的區域116a-116c，並顯露在相同平面126中的金屬化支柱結構112a-112c。如果聚合物充填料150被使用，其可被移除，導致最後之合成晶圓結構，其係預備好供使用於隨後之標準晶圓至晶圓接合製程中。
上述方法實施例可採用現存工具及材料，及提供勝過目前使用的接合方法之優點，包括、但不限於來自不同技術的不同厚度之整合裝置晶粒的能力，例如CMOS、光電子裝置、MEMS、及其他微電子裝置。此外，結果之裝置的良率可藉由只將已知合格晶粒併入該等裝置及消除潛在晶粒切單顆及處理碎物而被增加，藉此顯著地改善良率。再者，接合薄晶粒之能力允許用於多數裝置層的堆疊，包括那些來自不同技術者，被直立地連接，同時維持低輪廓封裝。
其將被了解在此中所敘述之建構及操作上的實施例係複數個可能配置之示範，以提供該相同的一般特色、特徵、及一般系統操作。對其他人於閱讀及理解該之前的詳細敘述時將發生修改及變 更。其係意欲使該揭示內容被解釋為包括所有此等修改及變更。如此，本揭示內容之廣度及範圍不應被該等上述示範實施例的任何一者所限制，但應只按照至此為止所附之以下申請專利範圍及其同等項被界定。
20、25、30、35、40、45、50、55、60、65‧‧‧步驟

Claims (14)

  1. 一種將一或多個晶粒接合至晶圓之方法，包含：承接複數個晶粒，每一晶粒具有正面、基板材料的背面及厚度，每一正面包括保護一或多個金屬化支柱結構之一平面化氧化物層，該一或多個金屬化支柱結構連接至該晶粒中所形成的裝置結構；將該複數個晶粒之每一正面接合至一第一操作晶圓的前面，使得與每一晶粒有關聯之該金屬化支柱結構位在一共同平面中；將該被接合的複數個晶粒之該基板材料背面的每一者薄化至均勻之厚度；將SiO 2層沈積接合在該複數個晶粒的個別背部及該第一操作晶圓之暴露前面上；將該複數個均勻地薄化的晶粒之背面接合至一第二操作晶圓的前面；藉由薄化移除該第一操作晶圓；及由該複數個均勻地薄化之晶粒的每一正面移除該平面化氧化物層，以顯露該一或多個金屬化支柱結構。
  2. 如申請專利範圍第1項之方法，其中該晶粒的至少一者之厚度係與該另一晶粒不同。
  3. 如申請專利範圍第1項之方法，其中與每一晶粒有關聯的保護性平面化氧化物層包括潛在晶粒切單顆及處理碎物之區域，使得該保護性平面化氧化物層的移除亦移除該潛在晶粒切單顆及處理碎物之區域。
  4. 如申請專利範圍第1項之方法，另包含：加工在不同裝置晶圓上的晶粒裝置結構之每一者；保護具有相關聯的氧化物層之晶粒裝置結構的每一者；及切割該晶粒。
  5. 如申請專利範圍第1項之方法，其中該晶粒的至少一者包含一複合裝置。
  6. 如申請專利範圍第1項之方法，其中晶背研磨及CMP被施加，以均 勻地薄化該被接合晶粒的該基板材料背面。
  7. 如申請專利範圍第1項之方法，另包含藉由薄化來移除該第二操作晶圓，以便暴露該晶粒。
  8. 如申請專利範圍第1項之方法，其中每一晶粒包含已知一合格晶粒，且該第二晶圓具有大約200毫米的直徑。
  9. 如申請專利範圍第1項之方法，其中將該個別晶粒正面接合至該第一操作晶圓的前面包含將一低溫氧化物接合製程施加至該晶粒正面及第一操作晶圓前面。
  10. 如申請專利範圍第1項之方法，其中將該個別晶粒正面接合至該第一操作晶圓的前面包含在該晶粒正面及第一操作前面之間施加黏接劑。
  11. 如申請專利範圍第1項之方法，其中將該均勻地薄化的晶粒背面接合至該第二操作晶圓之前面包含將低溫氧化物接合製程施加至該均勻地薄化的晶粒背面及該第二操作前面。
  12. 如申請專利範圍第1項之方法，其中將該均勻地薄化的晶粒背面接合至該第二操作晶圓之前面包含在該均勻地薄化的晶粒背面及該第二操作前面之間施加一黏接劑。
  13. 如申請專利範圍第1項之方法，另包含：於薄化之前，以強度增強的一聚合材料充填被接合至該第一操作晶圓的每一晶粒間之間隙；及在沈積該SiO 2層之前或於移除該第一操作晶圓之後移除該聚合間隙充填材料。
  14. 如申請專利範圍第1項之方法，其中將該晶粒正面接合至該第一操作晶圓另包含將每一晶粒精確地定位在該晶粒的相關聯金屬化支柱結構之間距的一預定百分比內。
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