CN110199385A - 不同厚度的管芯的晶圆键合方法 - Google Patents
不同厚度的管芯的晶圆键合方法 Download PDFInfo
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- CN110199385A CN110199385A CN201880008253.XA CN201880008253A CN110199385A CN 110199385 A CN110199385 A CN 110199385A CN 201880008253 A CN201880008253 A CN 201880008253A CN 110199385 A CN110199385 A CN 110199385A
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Abstract
描述了用于键合可以具有与晶圆不同的厚度的一个或多个管芯(100a‑100c)的方法、组件和器件。可以用平面化氧化物层(114a)制造和单体化管芯,以防止晶圆划片和处理碎片,连接到集成电路的一个或多个金属化柱结构(112a‑112c)。管芯的正面(16a‑106c)被键合到第一处理晶圆(118),使得相应的柱结构在共同的平面中对准。键合管芯的基板材料背面(108a‑108c)然后被减薄至均匀的厚度并键合到第二处理晶圆。然后可以翻转组件,并且移除包括潜在划片和处理碎屑的保护层和第一处理晶圆。柱结构被显示,从而产生复合晶圆组件,其包括第二处理件和安装在其上的一个或多个经均匀减薄的管芯。
Description
背景
技术领域
本公开总体上涉及集成电路(IC)、半导体器件和其他小型化器件的制造,并且更具体地涉及优化,涉及具有不同高度的管芯(die)的管芯到晶圆键合过程的产量(yield)。
背景技术
IC制造的趋势已经是IC不同尺寸的互连、在不同尺寸的晶圆上制造、并提供不同的功能(即模拟的、数字的、光学的)和材料。可以在堆叠之前测试IC以允许已知良好管芯(Known Good Die,KGD)被组合以提高产量。这种垂直堆叠和垂直互连方法的经济上的成功取决于堆叠和互连的产量和成本相比于与芯片区域上增加的IC或系统相关联的产量和成本是有利的。用于实现该方法的制造方法是使用直接键合杂化(DBH)来垂直堆叠IC,以在晶圆之间形成共价键。
垂直堆叠和垂直互连的一种版本是(基板上的)IC以管芯到晶圆(D2W)的格式被键合,其中管芯IC面朝下键合到IC面朝上的公共晶圆,以允许堆叠已知良好管芯来提高产量。为了使制造IC的成本尽可能小,可以在小的半导体晶圆(通常直径为100mm)上一次制造多个化合物半导体器件(GaAs、InP、GaN等)的实例。典型的铸造IC是在200mm直径的硅晶圆上制造的。为了利用与来自小晶圆的器件键合的DBH晶圆,器件需要被单体化(singulated)到管芯,并然后键合到200mm晶圆。芯片划片(dicing)是将晶圆分成多个单独的管芯的过程,并且通常涉及使用锯片、化学品、激光或它们的组合以通过并沿着被布置在晶圆上的多个器件之间延伸的切口区域进行切割。芯片划片可能留下像差(aberration),其可能在随后的键合过程转化为降低产量的空隙。D2W键合通常非常低产,这是由于在单体化期间产生的这种粒子并且因处理限制而无法再抛光(例如,CMP)管芯的键合表面(即,为了在不破坏晶圆的情况下处理晶圆,晶圆应该具有至少700um的厚度)而引起的。此外,由于包含一个以上管芯的多芯片模块的紧凑性和处理能力,其制造商正变得非常流行。这种封装的制造商一直在寻找减小这种封装的尺寸或厚度的途径。减小这种封装厚度的一种途径是使用尽可能薄的管芯。
虽然存在许多用于减薄整个晶圆(然后以其整体进行使用)的方法,但是很少存在用于减薄单个管芯的方法。因此,所需要的是适应于使用不同尺寸的单体化管芯的D2W制造过程,其克服了当前的限制。
发明内容
根据某些实施例,提供了一种用于将可以具有不同厚度的多个管芯键合到(例如具有约200mm的直径的)公共晶圆的技术。管芯可以包括由不同的(例如具有约100mm的直径的)器件晶圆制造和单体化的直接键合杂化(DBH)器件结构和平面化(planarized)氧化物层。每个单体化管芯具有正面、基板材料背面和厚度。每个管芯正面包括平面化氧化物层,其保护连接到在管芯中形成的器件结构的一个或多个金属化柱结构(post structure)。
多个管芯中的每一个可以正面(电路面)朝下键合到第一处理晶圆的正面,使得与每个管芯相关联的金属化柱结构位于共同平面中。多个管芯可以利用拾取和放置仪器在x-y方向上被精确对准。可以(例如,通过背面研磨(backgrind)和/或CMP等)将键合的多个管芯的材料基板背面减薄至均匀的厚度,并且可以在经减薄的管芯背面上和第一处理晶圆的暴露表面上沉积二氧化硅层。然后,经均匀减薄的多个管芯的背面可以被键合到第二处理晶圆的正面。第一处理件(handle)然后可以被移除,并且平面化氧化物层可以从多个经均匀减薄的管芯的每个正面移除,以显示一个或多个金属化柱结构。
在某些实施例中,管芯中的一个或多个可以呈现出潜在像差的区域,其可以导致在键合步骤中降低产量的空隙,其中该区域由从其相应的一个或多个器件晶圆对管芯进行划片造成。该区域通常设置在与每个管芯中的一个或多个金属化柱结构相邻的平面中(并且在柱结构和中间晶圆组件结构中的键合管芯的第一处理件正面之间)。该区域不会对将管芯的正面键合到第一处理件产生负面影响,并且有利地,将利用与每个管芯相关联的保护性平面化氧化物层来移除该区域。这显著提高了过程的产量,其中已知良好管芯可以被键合在最终的复合晶圆结构中。
在一个实施例中,该过程还包括在不同的器件晶圆上制造管芯器件结构、用相关联的氧化物层保护每个管芯器件结构、以及使管芯单体化。器件管芯中的至少一个可以是化合物半导体器件(例如,GaAs、InP、GaN等)。第一处理件和/或第二处理件可以通过以下被键合到管芯:应用低温氧化物键合过程(诸如美国专利8,053,329中描述的键合,其内容通过引用并入)、DBH键合、或在经均匀减薄的管芯背面与第一处理件和第二处理件正面之间施加粘合剂。可以通过减薄来移除第一处理件和/或第二处理件,对于第二处理件导致了器件管芯暴露。
在另一个实施例中,管芯背面的均匀减薄可以可选地在以下之后:在减薄之前用增强强度的聚合物材料填充被键合到第一处理件的每个管芯之间的间隙,以帮助在例如CMP处理期间保持管芯的相对定位。然后,可以在沉积键合SiO2层之前或在移除第一处理晶圆之后,在减薄之后移除聚合物填充材料。
附图说明
下面参考附图讨论本公开的至少一个实施例的各方面。将理解的是,为了说明的简单和清楚,图中所示的元件不一定精确地或按比例绘制。例如,为了清楚起见,一些元件的尺寸可能相对于其他元件被夸大,或者一个示出的元件中可以包括若干物理部件。此外,在认为适当的情况下,附图标记可以在图中重复以指示相应或类似的步骤或部件。出于清楚的目的,并非每个部件都可以在每个图中被标记。图出于说明和解释的目的被提供,且不旨在作为本发明的限制的定义。在图中:
图1是根据说明性实施例的用于不同厚度管芯的管芯到晶圆键合的方法的流程图;
图2示意性地示出了将不同高度的管芯键合(或粘合)到第一处理晶圆的步骤;
图3示意性地示出了用聚合物材料填充管芯之间的间隙的步骤;
图4示意性地示出了背面研磨和/或CMP以将所有管芯厚度设定为均匀水平的步骤;
图5示意性地示出了将第二处理晶圆键合(或粘合)到管芯背面的步骤;
图6示意性地示出了将晶圆结构翻转到优选取向并移除第一处理晶圆的步骤;并且
图7示意性地示出了从管芯移除保护性平面化氧化物层和潜在碎片区域并显示器件管芯柱结构的步骤。
具体实施方式
在以下详细描述中,阐述了许多具体细节以便提供对本公开的方面的透彻理解。本领域普通技术人员将理解的是,可以在不独立地实现这些具体细节中的一些的情况下实践这些。在其他情况下,可能没有详细描述众所周知的方法、过程、部件和结构,以免使实施例模糊。优选实施例的以下描述本质上仅是示例性的,并且决不旨在限制本公开、其应用或用途。此外,要理解的是,本文采用的措辞和术语仅用于描述的目的,并且不应视为限制。应当理解的是,为了清楚起见,某些特征在单独的实施例的上下文中描述,但是也可以在单个实施例中组合提供。相反,为简洁起见,各种特征在单个实施例的上下文中描述,但也可单独提供或以任何合适的子组合提供。
除非明确地如此描述,否则本文使用的元件、动作或指令不应被解释为关键或必要的。此外,如本文所使用的,冠词“一”和“一个”旨在包括一个或多个项目,并且可以与“一个或多个”互换使用。此外,除非另有明确说明,否则短语“基于”旨在意为“至少部分地基于”。将进一步理解的是,术语“包括”(和任何形式的包括,诸如“包括(comprises)”和“包括(comprising)”)、“具有”(和任何形式的具有,诸如“具有(has)”和“具有(having)”)、“包含”(和任何形式的包含,诸如“包含(includes)”和“包含(including)”)以及“含有”(和任何形式的含有,诸如“含有(contains)”和“含有(containing)”)是开放式连接动词。结果,“包括”、“具有”、“包含”或“含有”一个或多个步骤或元件的方法、结构或器件拥有那些一个或多个步骤或元件,但不限于仅拥有那些一个或多个步骤或元件。此外,以某种方式配置的器件或结构以至少该方式配置,但是也可以以未列出的方式配置。
出于以下描述的目的,术语“上部”、“下部”、“垂直”、“水平”、“正面”、“背面”及其派生词应涉及所公开的结构和方法,如以附图取向。术语“在顶部”、“相邻”、“定位在”或“定位在顶部”意为第一元件(诸如第一结构)存在于第二元件(诸如第二结构)上或其附近,其中在第一元件和第二元件之间可以存在诸如接口结构的中间元件。术语“直接接触”意为第一元件(诸如第一结构)和第二元件(诸如第二结构)在两个元件的接口处没有任何中间导电、绝缘或半导体层的情况下进行连接。
参考图1,示出了示例性键合过程10,其用于将具有不同厚度的多个已知良好管芯安装到处理晶圆以形成3D堆叠,并然后通过在单个晶圆级均匀厚度减薄处理中减薄管芯的背面来校正晶圆厚度变化。如本文所使用的,术语“管芯”用于指代已经制造(例如,DBH键合处理等)出的具有电路的小片半导体材料。术语“基础技术晶圆”用于指代集成电路、半导体器件和其他小型化器件(包括但不限于CMOS、光电子器件、红外检测器、MEMS等,其通常具有大约200mm的直径)。术语“器件晶圆”用于指代在制造集成电路、半导体器件和其他小型化器件中所使用的半导体材料薄片,其具有小于基础技术晶圆的直径的直径,通常大约为100mm。术语“处理晶圆”用于指代在其它部件(例如,单体化管芯)被处理和减薄时为它们提供机械支撑的晶圆。在大多数管芯到晶圆(D2W)应用中,电子部件被分阶段地构建在一个或多个器件晶圆上和基础技术晶圆上。对于不同尺寸的器件晶圆和/或不同的材料,器件晶圆被划片,并且单体化管芯被对准并键合到接收基础技术晶圆的管芯位置上。传统技术的产量非常低,这是因为单体化管芯从划片和处理中拾取碎片并且因管芯不能加载到CMP工具上进行最终抛光而不能被清洁或准备键合。所公开的技术通过以下克服了这种障碍:在键合到可以被清洁和抛光的硅处理晶圆之后减薄管芯,并移除可能包含这种碎片所在的晶圆区域。
包括填充有经均匀减薄的KGD的(例如硅)处理晶圆的复合结构可以通过键合方法10来制造,键合方法10可以开始于制造器件晶圆和第一硅处理晶圆和第二硅处理晶圆的可选步骤20和将管芯单体化的步骤25。然后,方法10继续:将管芯临时键合到第一硅处理晶圆的正面使得管芯的器件柱结构在公共平面中对准的步骤30、均匀地减薄键合管芯的背面的步骤35(其可以包括用机械稳定性增强聚合物材料(例如,BCB、聚酰亚胺、PR等)来填充键合管芯之间的间隙的可选步骤40)、将二氧化硅层沉积键合到经减薄的管芯的背面和第一处理晶圆的正面的暴露表面区域的步骤45、将经减薄的管芯的背面键合到第二处理晶圆的正面的步骤50、移除第一处理晶圆的步骤55、以及显示管芯的器件柱结构的步骤60,其中用于显示器件柱结构的过程包括移除可能包含单体化和处理碎片的潜在单体化像差的区域。这些单独的步骤在下文中参考图2-7更详细地描述。另外,在最终复合结构制造步骤65之后,可以执行按照标准处理的可选的其它晶圆键合,例如,键合到基础技术晶圆。
图2-7示意性地示出了根据方法10的用于产生复合结构的方法或过程,该复合结构包括填充有经均匀减薄的已知良好管芯的(例如,硅)处理晶圆。图2-7可以被认为是连续的单独处理步骤,为了便于讨论,其通常对应于图1的方法10中所述的步骤。
如图2中所示,具有可变(例如,大于5μm)厚度102a-102c的一个或多个管芯100a-100c可以以本领域已知的方式在一个或多个器件晶圆上已经被先前制造并单体化。代表性管芯100a包括正(电路)面106a、基板材料背面108a、集成器件结构110a(例如,DBH结构)、提供与集成器件结构的互连的一个或多个金属化柱结构112a、以及覆盖柱结构112a的保护性平面化氧化物层114a。在平面化氧化物层114a内,可以是潜在的单体化和/或处理碎片的区域116a,但是对于其随后通过本公开的方法10的移除,将以其它方式导致键合空隙和管芯间键合强度的变化,这是由于无法对复合管芯结构进行适当地CMP而引起的。包括正面120、背面122和正面120处的氧化物层124的第一硅处理件118也可以被先前制造。可以制备并临时键合管芯100a-100c的正面106a-106c和第一处理晶圆118的正面120,使得相应的柱结构112a-112c在公共平面126中对准。管芯100a-110c可以使用拾取和放置仪器在X-Y平面126中被精确地对准,并且可以已经先前被测试为已知良好管芯。通过研磨和CMP将实现管芯背面108a-108c的最终Z轴对准。可以通过低温氧化物键合过程(例如,加利福尼亚州圣何塞的Tessera Technologies提供的键合)、通过在正面106a-106c和第一晶圆正面120之间施加允许粘合到其上的临时粘合剂(和适当的热量和力)或通过类似技术来实现将管芯100a-100c键合到第一处理晶圆118的正面120。临时粘合剂可以包括牺牲粘合剂、热塑性、热固化和UV固化粘合剂,并且可以通过旋涂或其他已知技术来施加。
将管芯100a-100c临时键合到第一处理晶圆118提供了必要的支撑,以便允许在不使管芯破裂、翘曲或折叠的情况下减薄和处理管芯背面108a-108c。参考图3,如果需要附加的机械加固,则可选地,聚合物材料130可以用于将管芯100a-100c之间的间隙132临时填充到大约等于管芯100a-100c的最终所需高度的水平134。该步骤可能要求退火(例如,150℃)以保持材料130的位置。如图4中可以看出的,背面研磨和CMP可以被施加到背面108a-108c,以使管芯100a-100c减薄至最终所需高度136。研磨和减薄将基板材料从管芯100a-100c的背面108a-108c移除,直到达到所需厚度(例如,40μm)为止。管芯厚度优选地被控制在1μm内,以实现高产量键合。如果已采用聚合物填充材料130,则可(例如通过热激活)将其从晶圆组件中移除。
参考图5,管芯100a-100c的经减薄的背面108-108c和第一处理晶圆118的正面120的暴露表面136可以制备有保护性保形涂层140,诸如用于硅晶圆的二氧化硅涂层。第二处理晶圆142然后可以被临时键合到制备的管芯100a-100c的平面化背面108a-108c。可以采用与用于将第一晶圆处理件118键合到管芯100a-100c类似的键合过程。
如图6所示,中间晶圆组件144可以翻转到优选的取向以允许在第一晶圆处理件118上进行处理。背面研磨和CMP然后可以被施加以将第一处理晶圆118从组件移除,从而导致覆盖柱结构112a-112c的保护性平面化氧化物层114a-114c暴露。如所指出的,在平面化氧化物层114a-114c内,可以是潜在的单体化和/或处理碎片的区域116a-116c。参考图7,如果必要的话,可以在以下之前将另一个聚合物填充物150施加到间隙132:对管芯的正面106a-106c上的保护性平面化氧化物层114a-114c进行背面研磨和CMP,以便移除潜在碎片的区域116a-116c和平面化氧化物层114a-114c并且在公共平面126中显示金属化柱结构112a-112c。如果使用聚合物填充物150,则可以将其移除,从而得到最终的复合晶圆结构,其准备好用于随后的标准晶圆到晶圆键合过程。
上述方法实施例可以采用现有工具和材料,并提供优于当前使用的键合方法的优点,包括但不限于集成来自不同技术(例如CMOS、光电子器件、MEMS和其他微电子器件)的不同厚度的器件管芯的能力。此外,通过仅将已知良好的管芯并入到器件中并消除潜在的管芯单体化和处理碎屑,可以提高所得器件的产量,从而显著提高产量。此外,键合薄管芯的能力允许堆叠多个器件层,包括来自不同技术的垂直连接同时保持低剖面封装(low-profile package)的器件层。
将理解的是,本文描述的架构和操作实施例是用于提供相同的一般特征、特性和一般系统操作的多个可能布置的示例。在阅读和理解前面的详细描述时,其他人将想到修改和改变。本公开旨在被解释为包括所有这种修改和改变。因此,本公开的广度和范围不应受任何上述示例性实施例的限制,而应仅根据所附以下权利要求及其等同物来限定。
Claims (14)
1.一种将一个或多个管芯键合到晶圆的方法,包括:
接收多个管芯,每个管芯具有正面、基板材料背面和厚度,每个正面包括平面化氧化物层,其保护连接到在所述管芯中形成的器件结构的一个或多个金属化柱结构;
将所述多个管芯的每个正面键合到第一处理晶圆的正面,使得与所述管芯中的每个相关联的金属化柱结构位于共同的平面中;
将键合的所述多个管芯的每个基板材料背面减薄至均匀的厚度;
将SiO2层沉积键合在所述多个管芯的各个背面和所述第一处理晶圆的暴露的正面上;
将经均匀减薄的所述多个管芯的背面键合到第二处理晶圆的正面;
通过减薄来移除所述第一处理晶圆;并且
将所述平面化氧化物层从经均匀减薄的所述多个管芯的每个正面中移除,以显示所述一个或多个金属化柱结构。
2.根据权利要求1所述的方法,其中,所述管芯中的至少一个的厚度与其它管芯不同。
3.根据权利要求1所述的方法,其中,与每个管芯相关联的保护性平面化氧化物层包括潜在管芯单体化和处理碎片的区域,使得所述保护性平面化氧化物层的移除还移除了所述潜在管芯单体化和处理碎片的区域。
4.根据权利要求1所述的方法,还包括:
在不同的器件晶圆上制造管芯器件结构中的每个;
用相关联的氧化物层保护所述管芯器件结构中的每个;并且
使所述管芯单体化。
5.根据权利要求1所述的方法,其中,所述管芯中的至少一个包括复合器件。
6.根据权利要求1所述的方法,其中,背面研磨和CMP被施加以均匀地减薄键合的管芯的基板材料背面。
7.根据权利要求1所述的方法,还包括通过减薄来移除所述第二处理晶圆以暴露所述管芯。
8.根据权利要求1所述的方法,其中,每个管芯包括已知良好管芯,并且第二晶圆具有约200mm的直径。
9.根据权利要求1所述的方法,其中,将相应的管芯正面键合到所述第一处理晶圆的正面包括:将低温氧化物键合过程应用于管芯正面和第一处理晶圆正面。
10.根据权利要求1所述的方法,其中,将相应的管芯正面键合到所述第一处理晶圆的正面包括:在管芯正面和第一处理件正面之间施加粘合剂。
11.根据权利要求1所述的方法,其中,将经均匀减薄的管芯背面键合到所述第二处理晶圆的正面包括:将低温氧化物键合过程应用于经均匀减薄的管芯背面和第二处理件正面。
12.根据权利要求1所述的方法,其中,将经均匀减薄的管芯背面键合到所述第二处理晶圆的正面包括:在经均匀减薄的管芯背面和第二处理件正面之间施加粘合剂。
13.根据权利要求1所述的方法,还包括:
在减薄之前,使用增强强度的聚合物材料来填充被键合到所述第一处理晶圆的每个管芯之间的间隙;并且
在沉积SiO2层之前或在移除所述第一处理晶圆之后,移除聚合物间隙填充材料。
14.根据权利要求1所述的方法,其中,将管芯正面键合到所述第一处理晶圆还包括:在所述管芯的相关联金属化柱结构的间距的预定百分比内精确地引用所述管芯中的每个。
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CN112530863A (zh) * | 2019-10-12 | 2021-03-19 | 长江存储科技有限责任公司 | 用于裸片对裸片进行键合的方法和结构 |
CN115172192A (zh) * | 2022-09-09 | 2022-10-11 | 之江实验室 | 一种多芯粒晶圆级集成的混合键合方法 |
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US11158607B2 (en) * | 2018-11-29 | 2021-10-26 | Apple Inc. | Wafer reconstitution and die-stitching |
JP7235566B2 (ja) * | 2019-04-01 | 2023-03-08 | 株式会社ディスコ | 積層デバイスチップの製造方法 |
CN110233139B (zh) * | 2019-06-18 | 2021-12-03 | 青岛歌尔微电子研究院有限公司 | 一种电路单元封装方法 |
US11705471B2 (en) * | 2020-10-23 | 2023-07-18 | Raytheon Company | Close butted collocated variable technology imaging arrays on a single ROIC |
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US20180301365A1 (en) | 2018-10-18 |
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JP2020521315A (ja) | 2020-07-16 |
TW201906022A (zh) | 2019-02-01 |
KR102181666B1 (ko) | 2020-11-24 |
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CA3059415A1 (en) | 2018-10-18 |
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