TWI718720B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI718720B
TWI718720B TW108138502A TW108138502A TWI718720B TW I718720 B TWI718720 B TW I718720B TW 108138502 A TW108138502 A TW 108138502A TW 108138502 A TW108138502 A TW 108138502A TW I718720 B TWI718720 B TW I718720B
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semiconductor device
substrate
primer material
retaining wall
wall structure
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TW108138502A
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TW202027237A (zh
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潘志堅
鄭禮輝
高金福
盧思維
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置的製造方法，包括：貼附一第一半導體裝置於一基底的一第一表面上； 形成一犧牲結構於圍繞第一半導體裝置的基底的第一表面上，犧牲結構環繞基底的第一表面的一第一區域；以及形成一底膠材料於第一區域內。

Description

半導體裝置及其製造方法
本發明實施例係關於一種半導體技術，且特別是關於一種半導體裝置及其製造方法。
由於各種電子元件（例如，電晶體，二極體、電阻器、電容器等）的集積密度的不斷改進，半導體工業經歷了快速增長。 在大多數情況下，上述集積密度的改進來自於最小特徵部件尺寸的不斷縮小，這容許將更多組件集積至給定區域內。
隨著縮小電子裝置需求的增長，出現了對更小與更具創意的半導體晶片封裝技術的需求。這種封裝系統的一個示例為層疊封裝（Package-on-Package, PoP）技術。在PoP裝置中，頂部半導體封裝體堆疊於底部半導體封裝體的頂部，以提供高度的集積度及元件密度。另一個示例為基底上晶圓上晶片（Chip-On-Wafer-On-Substrate, CoWoS）結構，其中，一個半導體晶片貼附至一晶圓（例如，一中介層）而形成一晶圓上晶片（Chip-On-Wafer, CoW）結構。接著將CoW結構貼附至一基底（例如，印刷電路板），以形成CoWoS結構。這些與其他先進的封裝技術能夠生產出具有強化功能及小佔用面積（footprint）的半導體裝置。
一種半導體裝置的製造方法包括：貼附一第一半導體裝置至一基底的一第一表面；形成一犧牲結構於圍繞第一半導體裝置的基底的第一表面上，犧牲結構環繞基底的第一表面的一第一區域；以及形成一底膠材料於第一區域內。
一種半導體裝置的製造方法包括：接合一第一半導體裝置至一基底的一上表面的一第一區域，其中基底的上表面具有位於第一區域附近並接合至其上的多個被動部件；形成一擋牆結構於圍繞第一區域的基底的上表面上，擋牆結構設置於第一半導體裝置與被動部件之間，擋牆結構突出於基底的上表面上方；噴塗一底膠材料於擋牆結構的周界內；以及固化噴塗的底膠材料。
一種半導體裝置包括：一基底；一第一半導體裝置，貼附至基底的一第一側；以及一底膠材料，圍繞第一半導體裝置且位於基底與第一半導體裝置之間，其中底膠材料的一導角具有遠離基底的一第一部以及位於第一部與基底之間的一第二部，其中第一部的一第一寬度隨著第一部朝向基底延伸而持續增加，且第二部的一第二寬度為均勻一致的。
以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化本揭露內容。當然，這些僅為範例說明並非用以限定本發明。舉例來說，若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本揭露內容在各個不同範例中會重複標號及/或文字。在整個說明書中，除非另有說明，否則不同圖式中的相同標號表示透過使用相同或相似材料及方法所形成的相同或相似部件。
再者，在空間上的相關用語，例如＂下方＂、＂之下＂、＂下＂、＂上方＂、＂上＂等等在此處係用以容易表達出本說明書中所繪示的圖式中元件或特徵部件與另外的元件或特徵部件的關係。這些空間上的相關用語除了涵蓋圖式所繪示的方位外，還涵蓋裝置於使用或操作中的不同方位。此裝置可具有不同方位（旋轉90度或其他方位）且此處所使用的空間上的相關符號同樣有相應的解釋。
第1A圖係繪示出根據一些實施例之半導體裝置100的剖面示意圖。半導體裝置100具有一晶圓上晶片（CoW）結構。如第1A圖所示，半導體裝置100包括一晶圓150（例如，中介層）、貼附至晶圓150上的一或多個晶片111（例如，111A、111B及111C）、位於晶111與晶圓150之間的一底膠材料133以及位於晶圓150上方且圍繞晶片111的一模塑材料135。半導體裝置100隨後貼附至基底，以形成具有基底上晶圓上晶片（CoWoS）結構的半導體裝置200，其細節如下文所述。
為了形成半導體裝置100，將一或多個晶片111（也可稱為半導體晶片，晶片或積體電路（IC）晶片）貼附至晶圓150的上表面。在所示的實施例中，晶圓150為中介層。因此，在理解其他類型的合適晶圓也可以用作晶圓150的情形下，晶圓150在本文的討論中也可稱為中介層。在一些實施例中，晶片111（例如111A、 111B及111C）為相同類型的晶片（例如，記憶體晶片或邏輯晶片）。 在其他實施例中，晶片111是不同類型的，例如，晶片111A可為邏輯晶片，而晶片111B及111C可為記憶體晶片。 晶片111的數量及晶片111的相對位置在第1A圖中僅為示例，晶片可能為其他數量並位於其他位置，且完全包括於本文實施例的範圍內。
在一些實施例中，晶片111A包括一基底111AS、形成於基底111AS內/上的電子部件（例如，電晶體、電阻器、電容器、或二極體等）以及位於基底111AS上方的內連線結構112，其連接電子部件而形成晶片111A的功能電路。晶片111A也包括多個導電接墊102及形成於導電接墊102上的導電柱體117（也稱為晶片連接器）。導電柱體117提供晶片111A的電路的電性連接。
晶片111A的基底111AS可為摻雜或未摻雜的半導體基底或為絕緣體上覆矽（silicon-on-insulator, SOI）基底的主動層。一般而言，SOI基底包括一半導體材料層，例如矽、鍺、矽鍺、SOI、絕緣體上覆矽鍺（silicon germanium on insulator, SGOI）或其組合。可使用的其他基底包括多層基底、漸變基底或混合晶向（hybrid orientation）基底。
晶片111A的電子部件包括各式各樣的主動部件（例如，電晶體）及被動部件（例如，電容器、電阻器、電感器）等。可使用任何合適的方法形成晶片111A的電子部件於晶片111A的基底111AS內或上方。晶片111A的內連線結構112包括形成於一或多個介電層內的一或多個金屬化層（例如，銅層），且用於連接各種電子部件以形成功能電路。在一實施例中，內連線結構由介電層與導電材料（例如，銅）的交替層形成，且可透過任何合適的製程（例如，沉積、鑲嵌或雙鑲嵌等）形成。
可形成一或多個鈍化層（未繪示）於晶片111A的內連線結構112上，以提供晶片111A的下方結構一定程度的保護。鈍化層可由一或多種合適的介電材料製成，例如氧化矽、氮化矽、低介電常數（low-k）介電材料（例如，碳摻雜的氧化物）、極低k介電材料（例如，多孔碳摻雜的二氧化矽）、其組合等。鈍化層可透過如化學氣相沉積（chemical vapor deposition, CVD）之類的製程形成，儘管也可採用任何合適的製程。
導電接墊102可形成於鈍化層上方，且可延伸穿過鈍化層，以電性接觸晶片111A的內連線結構112。導電接墊102可包括鋁，但是可替代使用其他材料，例如銅。
晶片111A的導電柱體117形成於導電接墊102上，以提供用於電性連接至晶片111A的電路的多個導電區域。導電柱體117可為銅柱體、接觸凸塊（例如，微型凸塊等），且可包括銅、錫、銀、其組合或其他合適的材料。
可使用相同或相似的製程步驟來形成晶片111B及晶片111C，然而可形成不同的電子部件及不同的電性連接器，以針對不同的晶片形成具有不同功能的電路。此處不再贅述細節。
觀察晶圓150，其包括一基底123、多個通孔電極121（也稱為基底通孔電極（through-substrate via, TSV））、重佈結構131，位於晶圓150的上表面處的多個導電接墊132以及位於晶圓150的下表面處的外部連接器125（也可稱為導電凸塊）。第1A圖中的晶圓150的結構僅為非限定性示例。可能具有其他結構，且完全包括於本實施例的範圍內。
基底123可為摻雜或未摻雜的矽基底或絕緣體上覆矽（SOI）基底的主動層。然而，基底123可替代為玻璃基底、陶瓷基底、高分子基底或可提供合適的保護及/或內連接功能的任何其他基底。
在一些實施例中，基底123可包括多個電子部件，諸如電阻器、電容器、信號分配電路、或其組合等。這些電子部件可為主動電子部件、被動電子部件或其組合。在其他實施例中，基底123內沒有主動和被動電子部件。 所有這樣的組合完全包括於本實施例的範圍內。
通孔電極121形成於基底123內，且從基底123的上表面123U延伸至基底123的下表面123L。通孔電極121提供導電接墊132與外部連接器125之間的電連接。通孔電極121可由合適的導電材料形成，例如銅、鎢、鋁、合金、摻雜的多晶矽或其組合等。可在通孔電極121與基底123之間形成一阻擋層。阻擋層可包括合適的材料，例如氮化鈦，然而也可使用其他替代材料，例如氮化鉭、鈦等。
一旦形成了通孔電極121，就可於基底123的上表面123U上形成重佈結構131，以於通孔電極121、外部連接器125以及晶片111A、111B及111C之間提供內連接。重分佈結構131包括設置於重分佈結構131的一或多個介電層內的多個導電特徵部件137（導線及/或介層連接窗（via））。在一些實施例中，一或多個介電層由高分子形成，諸如聚苯並噁唑（polybenzoxazole, PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene, BCB）等。在其他實施例中，介電層由氮化物形成（例如，氮化矽）、氧化物（例如，氧化矽）、磷矽酸鹽玻璃（phosphosilicate glass, PSG）、硼矽酸鹽玻璃（borosilicate glass, BSG），硼磷矽酸鹽玻璃（boron-doped phosphosilicate glass, BPSG）等。重佈結構131的一或多個介電層可透過任何可接受的沉積製程形成，例如旋塗、化學氣相沉積（CVD）、層壓或其組合等。
在一些實施例中，重佈結構131的導電特徵部件包括導線及/或導電介層連接窗，由合適的導電材料形成，諸如銅、鈦、鎢或鋁等。形成導電特徵可透過形成多個開口於重佈結構的介電層內以露出下方的導電特徵部件；形成一種子層於介電層上方及開口內；形成具有設計圖案的圖案化光阻於種子層上方；鍍覆（例如，電鍍或化學鍍）導電材料於設計圖案內及種子層上方；以及去除上方未形成導電材料的光阻及種子層的部分。在形成重佈結構131之後，可使用任何合適的材料（例如，銅、鋁、金、鎢或其組合等），形成多個導電接墊132於重佈結構131上方並電性耦接至重佈結構131。
接下來，形成多個外部連接器125於基底123的下表面123L上。外部連接器125可為任何合適類型的外部接點，例如微凸塊、銅柱體、銅層、鎳、 無鉛（lead free, LF）層、化學鍍鎳鈀浸金（electroless nickel electroless palladium immersion gold, ENEPIG）層、Cu/LF層、Sn/Ag層、Sn/Pb或其組合等。
如第1A圖所示，晶片111的導電柱體117可透過焊料區接合至晶圓150的導電接墊132。可進行回流製程以將晶片111接合到晶圓150。
在將晶片111接合至晶圓150之後，形成一底膠材料133於晶片111與晶圓150之間。底膠材料133可包括液體環氧樹脂，其使用點膠針或其他合適的點膠工具噴塗於晶片111與晶圓150之間的間隙內，接著進行固化而硬化。如第1A圖所示，底膠材料133填充於晶片111與晶圓150之間的間隙內，且也可填充於晶片111的側壁之間的間隙內。
接下來，一模塑材料135形成於晶圓150上方且圍繞晶片111。模塑材料135也圍繞底膠材料133。模塑材料135可包括環氧樹脂、有機高分子、加入或不加入二氧化矽基填充物或玻璃填充物的高分子或其他材料。在一些實施例中，模塑材料135包括液體模塑材料（liquid molding compound, LMC），其施加時為凝膠型液體。當施加時，模塑材料135也可包括液體或固體。或者，模塑材料135可包括其他絕緣及/或封膠材料。在一些實施例中，使用晶圓級模製製程來施加模塑材料135。可使用壓縮成型（compressive molding）、轉注成型（transfer molding）、成型底膠（molded underfill, MUF）或其他方法來成型模塑材料135。
接下來，在一些實施例中，使用固化製程來固化模塑材料135。固化製程可包括使用退火製程或其他加熱製程將模塑材料135加熱至預定溫度維持一段預定時間。固化製程也可包括紫外線（ultra-violet, UV）曝光製程、紅外線（infrared, IR）能量曝光製程、其組合或其與加熱製程的組合。或者，可使用其他方法來固化模塑材料135。在一些實施例中，不包括固化製程。
在形成模塑材料135之後，可進行一平坦化製程，例如化學和機械平坦化（chemical and mechanical planarization, CMP）製程，以自晶片111上方去除模塑材料135的多餘部分，使模塑材料135與晶片111具有共平面的上表面。 如第1A圖所示，模塑材料135與晶圓150的基底123相鄰。
第1B圖係繪示出第1A圖的半導體裝置100的簡化示意性剖面示意圖。在後續的圖式中使用第1B圖所示的半導體裝置100來表示第1A圖的半導體裝置100。為了簡化起見，第1B圖中未繪示半導體裝置100的所有特徵部件。
第2-6圖係繪示出根據一實施例之各個不同製造階段的半導體裝置200的各個視圖（例如，剖面示意圖、平面示意圖）。 如第2圖所示，第1A圖（或第1B圖）的半導體裝置100接合至一基底209（例如，印刷電路板）的上表面，以形成半導體裝置200。在一些實施例中，半導體裝置200具有基底上晶圓上晶片（Chip-On-Wafer-On-Substrate, CoWoS）結構。第2圖也繪示出貼附至基底209的上表面的被動部件211，以及形成於基底209的下表面上的外部連接器207。
在一些實施例中，基底209為多層電路板，例如印刷電路板（PCB）。 舉例來說，基底209可包括一或更多個介電層201（例如，201A，201B），由雙馬來醯亞胺三嗪（bismaleimide triazine, BT）樹脂、FR-4（由玻璃纖維編織布與具有阻燃性的環氧樹脂黏著劑組成的複合材料）、陶瓷、玻璃、塑料、膠帶、薄膜或其他支撐材料形成的。 基底209可包括多個導電特徵部件（例如，導線202和介層連接窗204）形成於基底209內/上。如第2圖所示，基底209具有形成於基底209的上表面209U上的多個導電接墊203以及形成於基底209的下表面（與上表面209U相對）上的多個導電接墊205，導電接墊203及205電性耦接至基底209的導電特徵部件。
半導體裝置100接合至基底209的導電接墊203。可進行回流製程，以將半導體裝置100的外部連接器125電性及機械性耦接至基底209的導電接墊203。
第2圖也繪示出多個被動部件211，其貼附至基底209的上表面209U且與半導體裝置100相鄰。被動部件211可為表面組裝裝置（surface-mount devices, SMDs），例如表面組裝電容器、 表面組裝電感器或表面組裝電阻器等。被動部件211的接觸端子213接合至導電接墊203。在一些實施例中，被動部件211在半導體裝置100貼附至基底209之前先貼附至基底209。在其他實施例中，在半導體裝置100貼附至基底209之後，被動部件211才貼附至基底209。
請再參照第2圖，外部連接器207（其可為焊球或銅柱體等）形成於基底209的下表面的導電接墊205上。因此，半導體裝置100、被動部件211及外部連接器207透過基底209的導電特徵電進行內連接。為簡化起見，在後續的圖式中未繪示出基底209的細節，例如導電特徵部件202/204及導電接墊203/205。可理解的是這些特徵部件可形成於基底209內/上，如第2圖所示。
接下來，請參照第3圖，形成一擋牆結構221於圍繞半導體裝置100的基底209的上表面209U上。擋牆結構221形成於半導體裝置100與被動部件211之間（另請參照第4圖）並且環繞（例如，圍繞）半導體裝置100貼附至其的上表面209U的區域。擋牆結構221在後續的製程中用於將底膠材料225包圍（例如，限制、局限）於擋牆結構221的邊界內。因此，擋牆結構221也可稱為底膠限制器（stopper）。在後續的製程中，在烘烤底膠材料225之後去除擋牆結構221。因此，擋牆結構221也可稱為犧牲結構。
如第3圖所示，擋牆結構221由合適的材料220形成，例如高分子、聚醯亞胺、環氧樹脂等。在一些實施例中，擋牆結構221的材料220與半導體裝置200的其他元件具有蝕刻選擇比（例如，具有不同的蝕刻速率），使得在後續的去除擋牆結構的製程中，可容易地使用蝕刻製程來去除擋牆結構221而實質上不侵蝕半導體裝置200的其他元件（例如，基底209、被動部件211及半導體裝置100）。 在示例性實施例中，擋牆結構221由丙烯酸類高分子形成，其可透過使用氫氧化鉀（KOH）的濕蝕刻製程而輕易去除。
在一些實施例中，使用點膠工具215將擋牆結構221的材料220（也可稱為犧牲材料）以液體形式沉積（例如噴塗）於基底209的上表面209U上。如第3及4圖所示，材料220選擇性地噴塗於圍繞半導體裝置100的區域中，因而在半導體裝置100周圍形成擋牆結構221。在一些實施例中，材料220在沉積於基底209上時進行固化。舉例來說，固化裝置217（可用於產生紫外（UV）線219的裝置）可用於進行UV固化製程，以在沉積材料220的同時固化材料220。取決於用於擋牆結構221的材料220的組成，還可使用其他固化製程，例如以熱固化製程來代替或附帶於UV固化製程（其中在固化裝置217可包括加熱裝置的情況下）。除了液體形式之外，材料220也可以凝膠形式進行點膠。
根據一些實施例，材料220的噴塗速度及/或固化製程的參數（例如，UV固化製程的UV劑量及/或熱固化製程的溫度） 可進行調節以得到用於擋牆結構（例如221、221A、221B）的不同形狀（例如，擋牆結構221的側壁輪廓）。在一實施例中，調整UV固化製程的UV劑量（例如，UV線的強度）以控制擋牆結構221的形狀。舉例來說，約在0.1瓦特（W）與1W之間的低UV劑量下，可用來形成底部具有突起221P的擋牆結構221。約在3W與4W之間的高UV劑量下，可形成在底部具有底切的擋牆結構221A（如第7圖所示）。約在1W與3W之間的中等UV劑量下，可形成具有筆直側壁的擋牆結構221B（如第9圖所示）。
請再參照第3圖，在一些實施例中，擋牆結構221形成具有約在2μm與1500μm之間的高度H，以及約在10μm與1000μm之間的寬度W。若高度H與寬度W小於各自述及的範圍，則擋牆結構221在後續的製程中可能無法有效地包圍（例如，限制）底膠材料225，且底膠材料225可能溢出擋牆結構上 221而與被動部件211接觸，這可能會損壞半導體裝置200。若高度H和寬度W大於所述及的範圍，則形成的圍堰結構221所需的材料成本及時間會很高而不符合經濟。
第4圖係繪示出在形成擋牆結構221之後的半導體裝置200的平面示意圖。 如第4圖所示，擋牆結構221形成於半導體裝置100與被動部件211之間，並圍繞半導體裝置100。在所示的實施例中，擋牆結構221具有矩形形狀（例如，中空矩形形狀）。儘管擋牆結構221在第4圖中繪示為具有矩形形狀，然而其他合適的形狀，例如三角形形狀（例如，中空三角形形狀）、五邊形形狀（例如，中空五邊形形狀）或其他多邊形（例如，中空多邊形形狀）也涵蓋於在本實施例的範圍內。
接下來，在第5圖中，將底膠材料225（例如，以液體形式）沉積於擋牆結構221的邊界（例如，周界）內，例如，位於半導體裝置100與基底209之間以及位於基底周圍，然後固化而硬化。圍繞半導體裝置100的周邊（例如，側壁）的固化的底膠材料225的部分（例如，不在半導體裝置100正下方的部分）被稱為底膠材料225的導角（fillet）。底膠材料225可相同或相似於第1A圖的底膠材料133，且可透過相同或相似的形成方法形成，因此不再贅述。由於擋牆結構221的限制，因此底膠材料225保留於擋牆結構221內，且擋牆結構221的邊界之外的上表面209U的區域並無底膠材料225，如第5圖所示。換句話說，在一些實施例中，擋牆結構221防止或減少底膠材料225溢出擋牆結構221外的區域。如此一來，底膠材料225不會接觸到被動部件211。
被動部件211接合至半導體裝置200的基底209，以提供強化的功能。然而，隨著半導體製造的集積密度的持續增加，半導體裝置100與基底209的尺寸繼續縮小，因而縮小了被動部件211與半導體裝置100之間的距離（例如，參照第4及6圖中的W3）。如此一來，底膠材料255在未使用擋牆結構221沉積的情況下可物理接觸（例如，覆蓋）被動部件211。由於底膠材料225與被動部件211之間的熱膨脹係數（coefficients of thermal expansion, CTE）不匹配，因此當底膠材料225接觸被動部件211則可能發生損壞（如，分層）。本實施例透過使用擋牆結構221，防止或減少底膠材料225溢出至擋牆結構221外的上表面209U的區域，因而防止或降低對形成的半導體裝置200的損壞。
擋牆結構221的使用也容許減小被動部件211與半導體裝置100之間的距離W3（相較於不使用擋牆結構221的對照方法），同時仍可避免底膠材料225與被動部件211之間的物理接觸。換句話說，可縮小半導體裝置200的尺寸（例如，基底209的尺寸）而不會因底膠材料225與被動部件211之間的物理接觸而造成損壞。 另外，由於底膠材料225被限制於由擋牆結構221限定的較小區域內，底膠材料225的導角的高度H2（請參照第6圖）增加，這提供了對半導體裝置100的更好的保護。因此，提高了半導體裝置200的可靠度及良率。
接下來，在第6圖中，在底膠材料225固化之後，去除擋牆結構221。可進行適當的蝕刻製程，例如濕蝕刻製程，以去除擋牆結構221。在所示的實施例中，擋牆結構221由高分子（例如，丙烯酸類高分子）形成，且蝕刻製程為使用氫氧化鉀（KOH）作為蝕刻化學的選擇性濕蝕刻製程。濕蝕刻製程選擇性地去除擋牆結構221，而實質上不侵蝕半導體裝置200的其他元件。儘管以濕蝕刻為例，然而也可以使用其他合適的去除方法，例如乾蝕刻或電漿蝕刻（例如，使用圖案化罩幕覆蓋半導體裝置200的其他元件，同時露出擋牆結構221來進行），且完全涵蓋於本實施例的範圍內。在一些實施例中，省略了去除擋牆結構221的蝕刻製程，並且擋牆結構221保留於半導體裝置200的最終產品內。在擋牆結構221保留於半導體裝置200內的實施例中，（固化的）底膠材料225的導角的形狀及尺寸可相同或相似於第6圖所示的那些。
在圖6中，（固化的）底膠材料225的導角具有遠離基底209的上部、接觸（例如，物理接觸）基底209的下部以及位於上部與下部之間的中間部。導角的上部具有傾斜的側壁225A，導角的中部具有筆直的側壁225B，且導角的下部具有傾斜的側壁225C。 由於擋牆結構221的底部具有突起221P（請參照第3圖），因此底膠材料225的導角的相應下部具有底切。在一些實施例中，在側壁225C與基底209的上表面209U之間測量的底切角θ約在2度與89度之間。
在第6圖的示例中，底膠材料225的導角的上部的寬度沿著半導體裝置100的側壁與底膠材料的各個側壁225A之間的第6圖的水平方向測量，係隨著上部朝向基底209延伸而增加。由於筆直的側壁225B，導角的中間部分具有均勻一致的寬度。導角的下部的寬度隨著下部朝向基底209的延伸而減小。導角接觸基底209的底表面的寬度W1小於導角的中間部的寬度W2。寬度W1及W2小於半導體裝置100與被動部件211之間的距離W3。底膠材料225的導角的高度H2為在上表面209U與導角中間部的最上邊緣225E之間測量，其小於半導體裝置100的高度H1，其中最上邊緣225E為底膠材料225的導角的上部與中間部之間的界面處的邊緣。
第7及8圖係繪示出根據一實施例之各個不同製造階段的半導體裝置200A的剖面示意圖。半導體裝置200A相似於半導體裝置200，其中相似的標號表示使用相同或相似材料及相同或相似方法形成的相似部件。需注意的是形成的半導體裝置200A使用具有不同於第5圖中的擋牆結構221的側壁輪廓的擋牆結構221A。特別地，第7圖中的擋牆結構221A的底部具有底切。如此一來，在沉積及固化底膠材料225之後，底膠材料225的導角的下部具有突起225P（請參照第8圖）。
請參照第8圖，在底膠材料225固化之後，去除擋牆結構221A。 （固化的）底膠材料225的導角具有遠離基底209的上部、與基底209接觸的下部以及位於上部與下部之間的中間部。導角的上部具有傾斜的側壁225A，導角的中間部具有筆直的側壁225B（例如，垂直於上表面209U），且導角的下部具有傾斜的側壁225C。由於擋牆結構221A的底部具有底切（請參照第7圖），因此導角的下部具有突起225P。在一些實施例中，在側壁225C與基底209的上表面209U之間測量的突起225P的角度α約在5度與85度之間。
在第8圖的示例中，底膠材料225的導角的上部的寬度隨著上部朝向基底209的延伸而增加。由於筆直的側壁225B，導角的中間部具有均勻一致的寬度。導角的下部具有隨著下部朝向基底209延伸而增加的寬度。導角接觸基底209的底表面的寬度W1大於導角的中間部的寬度W2。寬度W1及W2小於半導體裝置100與被動部件211之間的距離W3。底膠材料225的導角的高度H2小於半導體裝置100的高度H1。
在一些實施例中，省略了去除擋牆結構221A的蝕刻製程，且擋牆結構221A保留於半導體裝置200A的最終產品中。在擋牆結構221A保留於半導體裝置200A中的實施例中，（固化的）底膠材料225的導角的形狀及尺寸可相同或相似第8圖所示的那些。
第9及10圖繪示出根據一個實施例之各個不同製造階段的半導體裝置200B的剖面示意圖。半導體裝置200B相似於半導體裝置200，其中相同的標號表示使用相同或相似材料及相同或相似方法形成的相似部件。需注意的是形成的半導體裝置200B使用具有不同於第5圖中的擋牆結構221的側壁輪廓的擋牆結構221B。特別地，第9圖中的擋牆結構221B具有筆直的側壁。如此一來，在沉積並固化底膠材料225之後，底膠材料225的導角的下部具有筆直的側壁。
請參照第10圖，在底膠材料225固化之後，去除擋牆結構221B。（固化的）底膠材料225的導角具有遠離基底209的上部和與基底209接觸的下部。導角的上部具有傾斜的側壁225A，並且導角的下部具有筆直的側壁225B。需 注意的是由於擋牆結構221B的筆直的側壁，固化的底膠材料225的導角不具有側壁輪廓與下部不同的中間部。如此一來，在第10圖中所述的底膠材料225的導角，僅以上部及下部用來描述導角。
在第10圖的示例中，底膠材料225的導角的上部的寬度隨著上部朝向基底209延伸而增加。由於側壁225B是筆直的，因此底膠材料225的導角的下部具有均勻一致的寬度。與基底209接觸的導角的下表面的寬度W1等於導角的下部的寬度W2。寬度W1及W2小於半導體裝置100與被動部件211之間的距離W3。底膠材料225的導角的高度H2小於半導體裝置100的高度H1。
在一些實施例中，省略去除擋牆結構221B的蝕刻製程，且擋牆結構221B保留於半導體裝置200B的最終產品中。在擋牆結構221B保留於半導體裝置200B內的實施例中，（固化的）底膠材料225的導角的形狀及尺寸可相同或相似於第10圖所示的那些。
上述實施例可獲得諸多優點。所述的擋牆結構（例如221、221A、221B）防止或減少底膠材料225溢出至擋牆結構的邊界之外的區域。如此一來，避免或減少因底膠材料225與被動部件211之間的物理接觸而對半導體裝置200造成的損壞。擋牆結構透過容許縮小半導體裝置100與被動部件211之間的距離而容許減小基底209的尺寸，且同時防止底膠材料225接觸被動部件211。另一優點在於由於使用擋牆結構，因此底膠材料225的導角的高度H2增加。導角高度的增加為半導體裝置100提供更好的保護，因而提高半導體裝置200的可靠度。
第11圖繪示出在一些實施例中形成半導體裝置的方法流程圖1000。應可理解的是第11圖所示的實施例方法僅為諸多可能的實施例方法的一示例。任何所屬技術領域中具有通常知識者將瞭解到許多更動、替代與潤飾。舉例來說，可加入、移除、替換，重置以及重複第11圖所示的各個步驟。
請參照第11圖，在步驟區塊1010中，貼附一第一半導體裝置至一基底的一第一表面。在步驟區塊1020中，形成一犧牲結構於圍繞第一半導體裝置的基底的第一表面上，犧牲結構環繞基底的第一表面的一第一區域。在步驟區塊1030中，形成一底膠材料於第一區域內。
根據一個實施例，一種半導體裝置的製造方法包括：貼附一第一半導體裝置至一基底的一第一表面；形成一犧牲結構於圍繞第一半導體裝置的基底的第一表面上，犧牲結構環繞基底的第一表面的一第一區域；以及形成一底膠材料於第一區域內。在一實施例中，基底的第一表面具有貼附於其上的多個被動部件，其中犧牲結構形成於被動部件與第一半導體裝置之間。在一實施例中，形成犧牲結構包括：以液體形式或凝膠形式噴塗一犧牲材料於圍繞第一半導體裝置的基底的第一表面上；以及在噴塗犧牲材料同時，固化犧牲材料。在一實施例中，固化犧牲材料包括進行一紫外線（UV）固化製程或一熱固化製程。在一實施例中，透過UV固化製程來固化犧牲材料，其中形成犧牲結構包括透過調節UV固化製程的UV劑量來控制犧牲結構的形狀。在一實施例中，犧牲材料包括高分子、聚醯亞胺或環氧樹脂。在一實施例中，犧牲結構將底膠材料保留於第一區域內，其中基底的第一表面的第一區域外的多個區域沒有底膠材料。在一實施例中，上述方法更包括在形成底膠材料之後去除犧牲結構。在一實施例中，上述方法更包括在去除犧牲結構之前固化底膠材料。在一實施例中，在進行固化之後，底膠材料的一導角具有遠離基底的上部、接觸基底的下部以及位於上部與下部之間的中間部，其中上部的一第一寬度隨著上部朝向基底延伸而持續增加，並且中間部具有均勻一致的一第二寬度。在一實施例中，下部的一第三寬度隨著下部朝向基底延伸而持續變化。在一實施例中，去除犧牲結構包括使用對犧牲結構具有選擇比的一蝕刻劑進行一濕蝕刻製程，其中犧牲結構由丙烯酸高分子形成，且蝕刻劑包括氫氧化鉀。
根據一個實施例，一種半導體裝置的製造方法包括：接合一第一半導體裝置至一基底的一上表面的一第一區域，其中基底的上表面具有位於第一區域附近並接合至其上的多個被動部件；形成一擋牆結構於圍繞第一區域的基底的上表面上，擋牆結構設置於第一半導體裝置與被動部件之間，擋牆結構突出於基底的上表面上方；噴塗一底膠材料於擋牆結構的周界內；以及固化噴塗的底膠材料。在一實施例中，上述方法更包括在固化之後去除擋牆結構。在一實施例中，形成擋牆結構的步驟包括：噴塗一高分子材料於圍繞第一半導體裝置的基底的上表面上；以及在噴塗高分子材料時固化高分子材料。在一個實施例中，透過紫外線（UV）固化製程來固化高分子材料，其中上述方法更包括調節UV固化製程中的UV劑量以控制擋牆結構的一側壁輪廓。
根據一個實施例，一種半導體裝置包括：一基底；一第一半導體裝置，貼附至基底的一第一側；以及一底膠材料，圍繞第一半導體裝置且位於基底與第一半導體裝置之間，其中底膠材料的一導角具有遠離基底的一第一部以及位於第一部與基底之間的一第二部，其中第一部的一第一寬度隨著第一部朝向基底延伸而持續增加，且第二部的一第二寬度為均勻一致的。在一實施例中，底膠材料的導角更包括一第三部與基底接觸，第三部設置於第二部與基底之間，其中第三部的一第三寬度隨著第三部朝向基底延伸而持續變化。在一實施例中，隨著第三部朝向基底延伸，第三部的第三寬度持續減小。在一實施例中，半導體裝置更包括一擋牆結構，位於圍繞第一半導體裝置的基底的一第一側上，底膠材料設置於擋牆結構的邊界內，底膠材料自第一半導體裝置連續地延伸至擋牆結構。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎，以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神和保護範圍內，且可在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。
100,200,200A,200B:半導體裝置 102,132,203,205:導電接墊 111,111A,111B,111C:晶片 111AS,123,209:基底 112:內連線結構 117:導電柱體 121:通孔電極 123L:下表面 123U,209U:上表面 125,207:外部連接器 131:重佈結構 133:底膠材料 135:模塑材料 137,202,204:導電特徵部件 150:晶圓 201,201A,201B:介電層 211:被動部件 213:接觸端子 215:點膠工具 217:固化裝置 219:紫外（UV）線 220:材料 221,221A,221B:擋牆結構 221P,225P:突起 225:底膠材料 225A,225B,225C:側壁 225E:最上邊緣 1000:方法流程圖 1010,1020,1030:步驟區塊 H,H1,H2:高度 W,W1,W2:寬度度 W3:距離 α:角度 θ:底切角度
第1A圖繪示出根據一些實施例的半導體裝置剖面示意圖。 第1B圖繪示出根據一實施例的第1A圖的半導體裝置的示意性剖面示意圖。 第2-6圖繪示出根據一實施例的第1圖的半導體裝置的各個製造階段剖面示意圖。 第7及8圖繪示出根據一實施例的第1圖的半導體裝置的各個製造階段剖面示意圖。 第9及10圖繪示出根據一實施例的第1圖的半導體裝置的各個製造階段剖面示意圖。 第11圖繪示出在一些實施例的半導體裝置的形成方法流程圖。
100,200:半導體裝置
111:晶片
201:介電層
209:基底
209U:上表面
211:被動部件
221:擋牆結構
225:底膠材料

Claims (13)

  1. 一種半導體裝置的製造方法，包括：貼附一第一半導體裝置至一基底的一第一表面；形成一犧牲結構於圍繞該第一半導體裝置的該基底的該第一表面上，該犧牲結構環繞該基底的第一表面的一第一區域；形成一底膠材料於該第一區域內；以及在形成底膠材料之後去除該犧牲結構。
  2. 如請求項1之半導體裝置的製造方法，其中該基底的該第一表面具有貼附於其上的複數個被動部件，其中該犧牲結構形成於該等被動部件與該第一半導體裝置之間。
  3. 如請求項1之半導體裝置的製造方法，其中形成該犧牲結構包括：以液體形式或凝膠形式噴塗一犧牲材料於圍繞該第一半導體裝置的該基底的該第一表面上；以及在噴塗該犧牲材料同時，進行一紫外線(UV)固化製程或一熱固化製程固化該犧牲材料。
  4. 如請求項3之半導體裝置的製造方法，其中該透過該UV固化製程來固化該犧牲材料，其中形成該犧牲結構包括透過調節該UV固化製程的UV劑量來控制該犧牲結構的形狀。
  5. 如請求項1至3項任一項之半導體裝置的製造方法，其中該犧牲結構將該底膠材料保留於該第一區域內，其中該基底的該第一表面的該第一區域外的複數個區域沒有該底膠材料。
  6. 如請求項1之半導體裝置的製造方法，更包括在去除該犧牲結構之前固化該底膠材料。
  7. 如請求項6之半導體裝置的製造方法，其中在進行固化之後，該底膠材料的一導角具有遠離該基底的一上部、接觸該基底的一下部以及位於該上部與該下部之間的一中間部，其中該上部的一第一寬度隨著該上部朝向該基底延伸而持續增加，並且該中間部具有均勻一致的一第二寬度。
  8. 如請求項7之半導體裝置的製造方法，其中該下部的一第三寬度隨著該下部朝向該基底延伸而持續變化。
  9. 一種半導體裝置的製造方法，包括：接合一第一半導體裝置至一基底的一上表面的一第一區域，其中該基底的該上表面具有位於該第一區域附近並接合至其上的複數個被動部件；形成一擋牆結構於圍繞該第一區域的該基底的該上表面上，該擋牆結構設置於該第一半導體裝置與該等被動部件之間，該擋牆結構突出於該基底的該上表面上方；噴塗一底膠材料於該擋牆結構的周界內；固化該噴塗的底膠材料；以及在固化之後去除該擋牆結構。
  10. 如請求項9之半導體裝置的製造方法，其中形成擋牆結構的步驟包括：噴塗一高分子材料於圍繞該第一半導體裝置的該基底的該上表面上；以及在噴塗高分子材料時，透過一紫外線(UV)固化製程固化該高分子材料；以及 調節該UV固化製程中的UV劑量，以控制該擋牆結構的一側壁輪廓。
  11. 一種半導體裝置，包括：一基底；一第一半導體裝置，貼附至該基底的一第一側；以及一底膠材料，圍繞該第一半導體裝置且位於該基底與該第一半導體裝置之間，其中該底膠材料的一導角具有遠離該基底的一第一部以及位於該第一部與該基底之間的一第二部，其中該第一部的一第一寬度隨著該第一部朝向該基底延伸而持續增加，且該第二部的一第二寬度為均勻一致的，其中該底膠材料的該導角更包括一第三部與該基底接觸，該第三部設置於該第二部與該基底之間，其中該第三部的一第三寬度隨著該第三部朝向該基底延伸而持續變化。
  12. 如請求項11之半導體裝置，其中隨著該第三部朝向該基底延伸，該第三部的該第三寬度持續減小。
  13. 如請求項11之半導體裝置，更包括一擋牆結構，位於圍繞該第一半導體裝置的該基底的一第一側上，該底膠材料設置於該擋牆結構的邊界內，該底膠材料自該第一半導體裝置連續地延伸至該擋牆結構。
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