TWI713089B - 積體電路結構的形成方法 - Google Patents

積體電路結構的形成方法 Download PDF

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TWI713089B
TWI713089B TW108137996A TW108137996A TWI713089B TW I713089 B TWI713089 B TW I713089B TW 108137996 A TW108137996 A TW 108137996A TW 108137996 A TW108137996 A TW 108137996A TW I713089 B TWI713089 B TW I713089B
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Taiwan
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layer
hard mask
opening
mask layer
forming
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TW108137996A
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TW202018764A (zh
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鵬 王
黃玉蓮
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台灣積體電路製造股份有限公司
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Abstract

一種方法，包括：形成第一硬遮罩層和於第一硬遮罩層上方的第二硬遮罩層，以及形成三層（tri-layer）包括：底層、中間層、圖案化上層。此方法更包括：蝕刻中間層，以將在圖案化上層中的開口延伸進入中間層，其中開口在中間層中具有第一部分，且第一部分具有第一頂寬度和小於第一頂寬度的第一底寬度；蝕刻底層，以將開口延伸進入底層；以及蝕刻第二硬遮罩層，以將開口延伸進入第二硬遮罩層。在第二硬遮罩層中的開口具有第二部分，且第二部分具有第二頂寬度和小於第二頂寬度的第二底寬度。

Description

積體電路結構的形成方法
本發明實施例是關於半導體元件的形成方法，特別是關於收縮開口寬度的方法。
在積體電路的製造中，使用源極/汲極接觸插塞來連接至源極和汲極區和電晶體的閘極。一般連接源極/汲極接觸插塞至源極/汲極矽化物區，其形成製程包括在層間介電質中形成接觸開口，沉積金屬層，並使其延伸進入接觸開口，接著進行退火以使金屬層和源極/汲極區的矽/鍺進行反應。接著在剩餘的接觸開口中形成源極/汲極接觸插塞。
一種積體電路結構的形成方法，包括：形成第一硬遮罩層；形成第二硬遮罩層於第一硬遮罩層上方；形成三層（tri-layer），三層包括：底層於第二硬遮罩層上方，中間層於底層上方，以及圖案化上層於中間層上方；用圖案化上層作為蝕刻遮罩來蝕刻中間層，以將在圖案化上層中的開口延伸進入中間層，其中開口具有在中間層中的第一部分，且第一部分具有第一頂寬度和小於第一頂寬度的第一底寬度；蝕刻底層，以將開口延伸進入底層，其中在底層中的開口的一部分實質上具有垂直側壁；以及蝕刻第二硬遮罩層，以將開口延伸進入第二硬遮罩層，其中在第二硬遮罩層中的開口具有第二部分，且第二部分具有第二頂寬度和小於第二頂寬度的第二底寬度。
一種積體電路結構的形成方法，包括：形成層間介電質於電晶體的源極/汲極區上方；形成第一硬遮罩層於層間介電質上方；形成三層於第一硬遮罩層上方，包括：形成底層於第一硬遮罩層上方，形成中間層於底層上方，以及形成上層於中間層上方，其中上層具有開口；用上層作為蝕刻遮罩，以蝕刻中間層和底層，其中開口延伸進入中間層和底層，其中開口的寬度從在中間層的頂面層級的第一頂寬度收縮至在底層的底面層級的第一底寬度，且底層實質上具有垂直側壁；蝕刻第一硬遮罩層，其中開口延伸進入第一硬遮罩層，其中開口的寬度從第一底寬度收縮至在第一硬遮罩層的底面層級的第二底寬度；以及使用第一硬遮罩層作為蝕刻遮罩的一部分來蝕刻層間介電質，以將開口延伸進入層間介電質。
一種積體電路結構的形成方法，包括：形成第一硬遮罩層於層間介電質上方；形成第二硬遮罩層於第一硬遮罩層上方；形成三層，三層包括：底層於第二硬遮罩層上方，中間層於底層上方，以及圖案化上層於中間層上方，其中在圖案化上層中形成開口；以及將開口延伸進入中間層、底層、第二硬遮罩層、和第一硬遮罩層，其中在第二硬遮罩層中的開口的第一部分具有第一頂寬度和小於第一頂寬度的第一底寬度，以及在第一硬遮罩層中的開口的部分具有頂寬度和與頂寬度相等的底寬度。
以下揭露提供了許多的實施例或範例，用於實施本發明的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中提及第一部件形成於第二部件之上，可包括形成第一和第二部件直接接觸的實施例，也可包括額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。另外，本發明可在各種範例中重複元件符號及/或字母。這樣重複是為了簡化和清楚的目的，其本身並非主導所討論各種實施例及/或配置之間的關係。
再者，此處可使用空間上相關的用語，如「在…之下」、「下方的」、「低於」、「在…上方」、「上方的」和類似用語可用於此，以便描述如圖所示一元件或部件和其他元件或部件之間的關係。這些空間用語企圖包括使用或操作中的裝置的不同方位。當裝置被轉至其他方位（旋轉90°或其他方位），則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
根據一些實施例，提供包括源極/汲極接觸插塞的電晶體及其形成方式。根據一些實施例，繪示了形成電晶體的中間階段。討論一些實施例的一些變化。綜觀不同視圖和繪示的實施例，使用類似元件符號來標示類似的元件。根據本發明的一些實施例，討論了一種減少源極/汲極接觸開口寬度的方法，使其寬度小於微影製程的極限。藉由減少在用來形成接觸開口的蝕刻遮罩中的對應開口尺寸，以收縮接觸開口的寬度。
根據一些實施例，使用鰭式場效電晶體（Fin Field-Effect Transistors, FinFETs）的形成作為一個範例，以解釋本發明的概念。平面狀電晶體也可採取本發明的概念。再者，根據一些實施例，可使用形成開口的方法，來形成源極/汲極接觸開口以外的開口。舉例來說，可採用本發明的方法，以形成閘極接觸開口、穿矽通孔（through-silicon vias）、金屬走線、和介電層中（如在低k介電層中）的導孔。
第1至8、9A、9B、10A、10B、11、12、13A、13B、14A、14B、15A、15B、16A、16B、16C、17A、17B、17C、18A、18B、和18C圖是根據本發明的一些實施例，在鰭式場效電晶體和源極/汲極接觸插塞的形成中，繪示了中間階段的剖面圖、俯視圖、和透視圖。在製程流程200中，如在第19圖中，繪示了形成製程。
第1圖繪示了在晶圓10上形成的初始結構的透視圖，其晶圓包括基底20。基底20可是半導體基底，其可是矽基底、鍺化矽基底、或以其他半導體材料形成的基底。可以P型或N型雜質摻雜基底20。可形成隔離區22，如淺溝槽隔離（shallow trench isolation, STI）區，以從基底20的頂面延伸進入基底20。介於相鄰淺溝槽隔離區22之間的部分基底20被稱為半導體條（semiconductor strip）24。根據一些實施例，半導體條24的頂面和淺溝槽隔離區22的頂面實質上可與彼此齊平。根據本發明的一些實施例，半導體條24是原先基底20的部分，故半導體條24的材料與基底20的材料相同。根據本發明的替代實施例，半導體條24為替換條，其形成是藉由蝕刻介於淺溝槽隔離區22之間的部分基底20以形成凹槽，並在凹槽中進行磊晶以再成長另一個半導體材料。於是，半導體條24是以不同於基底20的半導體材料所形成。根據一些實施例，半導體條24是以鍺化矽、碳化矽、或一III-V族化合物半導體材料所形成。
淺溝槽隔離區22可包括襯氧化物（未繪出），其可是透過基底20表面層的熱氧化形成的熱氧化物。襯氧化物也可是沉積的矽氧化物層，使用，例如原子層沉積、高密度電漿化學氣相沉積、或化學氣相沉積來形成。淺溝槽隔離區22也包括於襯氧化物上方的介電材料，其中可使用流動性化學氣相沉積、旋轉塗布、或其他類似方法來形成其介電材料。
參考第2圖，凹蝕淺溝槽隔離區22，使半導體條24的頂部凸出高於淺溝槽隔離區22剩餘部分的頂面22A，以形成凸出鰭24’。個別製程繪示於第19圖的製程流程200中的製程202。可使用乾蝕刻製程來進行蝕刻，其中使用HF3 和NH3 作為蝕刻氣體。在蝕刻製程期間，可產生電漿。也可包括氬。根據本發明的替代實施例，使用濕蝕刻製程來進行淺溝槽隔離區22的凹蝕。舉例來說，蝕刻化學品可包括HF。
在上方繪示的實施例中，可藉由任何適合方法圖案化鰭。舉例來說，可使用一或多光微影製程來圖案化鰭，包括雙重圖案化（double-patterning）或多重圖案化（multi-patterning）製程。總體而言，雙重圖案化或多重圖案化製程結合光微影和自我對準製程，允許創造出具有節距的圖案，其節距小於，例如，另外使用單一直接光微影製程可獲得的節距。舉例來說，在一實施例中，使用光微影製程於基底上形成並圖案化犧牲層。使用自我對準製程，沿著圖案化的犧牲層，來形成間隔物。接著，移除犧牲層，則可使用剩餘的間隔物，或芯軸（mandrels），來圖案化鰭。
參考第3圖，形成虛置閘極堆疊30，以延伸在（凸出）鰭24’的頂面和側壁上。個別製程繪示於第19圖的製程流程200中的製程204。虛置閘極堆疊30可包括虛置閘極介電質32和於虛置閘極介電質32上方的虛置閘極電極34。可使用，例如，多晶矽或非晶矽來形成虛置閘極電極34，且也可使用其他材料。各別虛置閘極堆疊30也可包括於對應虛置閘極電極34上方的一個（或複數個）硬遮罩層36。可以矽氮化物、矽氧化物、矽碳氮化物、或類似材料、或其複合層，來形成硬遮罩層36。虛置閘極堆疊30可橫跨單一或複數個凸出鰭24’及/或淺溝槽隔離區22。虛置閘極堆疊30也具有長度方向，其垂直於凸出鰭24’的長度方向。
接著，在虛置閘極堆疊30的側壁上形成閘極間隔物38。個別製程也繪示於第19圖的製程流程200中的製程204。根據本發明的一些實施例，以介電材料，如矽氮化物、矽碳氮化物、或其他類似材料，來形成閘極間隔物38，並可具有單層結構或包括複數個介電層的多層結構。
接著，可進行蝕刻製程，以蝕刻凸出鰭24’沒有被虛置閘極堆疊30和閘極間隔物38覆蓋的部分，所得的結構繪示於第4圖。凹蝕可是異向性（anisotropic），故鰭24’於虛置閘極堆疊30和閘極間隔物38正下方的部分被保護著，沒有被蝕刻。根據一些實施例，凹蝕的半導體條24的頂面可低於淺溝槽隔離區22的頂面22A。相應地在淺溝槽隔離區22之間形成凹槽40。凹槽40置於虛置閘極堆疊30的兩側上。
接著，藉由選擇性地在凹槽40中成長半導體材料，來形成磊晶區（源極/汲極區）42，所得的結構在第5圖中。個別製程繪示於第19圖的製程流程200中的製程206。根據一些實施例，磊晶區42包括鍺化矽、矽、碳化矽、或其他類似材料。根據所得的鰭式場效電晶體是P型鰭式場效電晶體或是N型鰭式場效電晶體，可隨著磊晶的進行，原位（in-situ）摻雜P型或N型雜質。舉例來說，當所得的鰭式場效電晶體是P型鰭式場效電晶體時，可成長SiGeB、GeB、或其他類似材料。相反地，當所得的鰭式場效電晶體是N型鰭式場效電晶體時，可成長SiP、SiCP、或其他類似材料。根據本發明的替代實施例，以III-V族化合物半導體，如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其組合、或其複合層，來形成磊晶區42。在磊晶區42填充凹槽40之後，磊晶區42開始水平地擴張，並可形成晶面。也可形成氣隙43。
在磊晶步驟之後，更可將P型或N型雜質佈植至磊晶區42，以形成源極和汲極區，其也使用元件符號42標示。根據本發明的替代實施例，當在磊晶期間，以P型或N型雜質原位摻雜磊晶區42時，則略過佈植步驟。
第6圖繪示了在接觸蝕刻停止層46和層間介電質48的形成之後的結構的透視圖。個別製程繪示於第19圖的製程流程200中的製程208。可以矽氧化物、矽氮化物、矽碳氮化物、或其他類似材料，且可使用化學氣相沉積、原子層沉積、或其他類似方法，來形成接觸蝕刻停止層46。層間介電質48可包括介電材料，其形成是使用，例如，流動性化學氣相沉積、旋轉塗布、化學氣相沉積、或其他沉積方法。可以含氧介電材料形成層間介電質48，其可是氧化矽為基礎的氧化物，如四乙氧基矽烷氧化物（tetra ethyl ortho silicate oxide）、電漿促進化學氣相沉積氧化物（SiO2）、磷矽酸玻璃、硼矽酸玻璃、硼摻雜磷矽酸玻璃、或其他類似材料。可進行平坦化製程，如化學機械拋光製程或機械研磨製程，來使層間介電質48、虛置閘極堆疊30、和閘極間隔物38的頂面彼此齊平。
接著，以替換閘極堆疊56來取代虛置閘極堆疊30，虛置閘極堆疊30包括硬遮罩層36、虛置閘極電極34、和虛置閘極介電質32。個別製程繪示於第19圖的製程流程200中的製程210。替換閘極堆疊56包括金屬閘極54和閘極介電質52，如第7圖所示。當形成替換閘極堆疊56時，首先以一個或複數個蝕刻步驟移除硬遮罩層36、虛置閘極電極34、和虛置閘極介電質32，如第7圖所示，所得的溝槽/開口是形成在閘極間隔物38之間。凸出的半導體鰭24’的頂面和側壁露出於所得的溝槽。
接著，形成（替換）閘極介電層52，其延伸進入在閘極間隔物38之間的溝槽。根據本發明的一些實施例，各閘極介電層52包括界面層作為其下部，來接觸對應凸出鰭24’的露出面。界面層可包括氧化物層，如矽氧化物層，其透過凸出鰭24’的熱氧化、化學氧化製程、或沉積製程來形成。閘極介電層52也可包括形成於界面層上方的高k介電層。高k介電層可包括高k介電材料，如鉿氧化物、鑭氧化物、鋁氧化物、鋯氧化物、矽氮化物、或其他類似材料。高k介電材料的介電常數（k值）高於3.9，且可高於約7.0。形成高k介電層作為順應層，並延伸於凸出鰭24’的側壁上和閘極間隔物38的側壁上。根據本發明的一些實施例，使用原子層沉積或化學氣相沉積來形成高k介電層。
進一步參考第7圖，於閘極介電質52上方形成閘極電極54，閘極電極54包括導電次層（sub-layers）。雖然次層之間是有可能可以彼此區別的，但次層沒有被分開繪示。可使用順應性沉積方法，如原子層沉積或化學氣相沉積，來進行次層的沉積。
堆疊的導電次層可包括擴散阻障層和於擴散阻障層上方的一（或多個）功函數層（work-function layer）。可以TiN來形成擴散阻障層，TiN可（或可不）被矽摻雜。功函數層決定了閘極的功效，且包括以不同材料形成的至少一層，或複數個層。功函數層的材料的選擇是根據個別鰭式場效電晶體是N型鰭式場效電晶體或是P型鰭式場效電晶體。舉例來說，當鰭式場效電晶體是N型鰭式場效電晶體時，功函數層可包括TaN層和於TaN層上方的TiAl層。當鰭式場效電晶體是P型鰭式場效電晶體時，功函數層可包括TaN層、於TaN層上方的TiN層、和於TiN層上方的TiAl層。在功函數層的沉積之後，形成阻障層，其可為另一TiN層。
形成沉積的閘極介電層和導電層作為順應層來延伸進入溝槽，且包括於層間介電質48上方的一些部分。接著，沉積金屬材料來填充在閘極間隔物38之間的剩餘溝槽。舉例來說，可以鎢或鈷，來形成金屬材料。在後續的步驟中，進行平坦化步驟，如化學機械拋光製程或機械研磨製程，來移除於層間介電質48上方的部分閘極介電層、導電次層、和金屬材料。如此一來，形成金屬閘極電極54和閘極介電質52。閘極電極54和閘極介電質52統稱為替換閘極堆疊56。在此時，替換閘極堆疊56、閘極間隔物38、接觸蝕刻停止層46、和層間介電質48的頂面實質上可為共面性。
根據一些實施例，第7圖也繪示了硬遮罩58的形成。個別製程也繪示於第19圖的製程流程200中的製程210。硬遮罩58的形成可包括：進行蝕刻步驟來凹蝕閘極堆疊56，讓凹槽在閘極間隔物38之間形成；以介電材料填充凹槽；然後進行平坦化製程，如化學機械拋光製程或機械研磨製程，來移除介電材料的多餘部分。可以矽氮化物、矽氧氮化物、矽氧碳氮化物、或其他類似材料來形成硬遮罩58。
接著，參考第8圖，於層間介電質48上方沉積蝕刻停止層47和第二層間介電質49。個別製程繪示於第19圖的製程流程200中的製程212。根據一些實施例，蝕刻停止層47是以，例如矽碳化物、矽氮化物、矽氧化物、或其他類似材料所形成的介電層。層間介電質49形成的材料可選自，和用來形成層間介電質48的候選材料相同的族群。
接著，參考第8圖，於層間介電質49上方形成硬遮罩層60和62。個別製程繪示於第19圖的製程流程200中的製程214。根據本發明的一些實施例，硬遮罩層60是含金屬硬遮罩層，其可以鈦氮化物、鎢碳化物、或其他類似材料來形成。硬遮罩層60可具有介於約150Å和400Å之間的厚度。硬遮罩層62可是氧化物層，其可是在低溫下沉積的低溫氧化物層，例如，低於約100°C。硬遮罩層62可具有介於約300Å和600Å之間的厚度T1。
於硬遮罩層62上方形成蝕刻遮罩64A和64B。個別製程繪示於第19圖的製程流程200中的製程216。蝕刻遮罩64A和64B也個別地和統一地被稱為蝕刻遮罩64。蝕刻遮罩64的厚度可介於約100Å和300Å之間。可以非晶矽形成蝕刻遮罩64，也可使用具有和下方層60和62充足的蝕刻選擇比的其他材料。蝕刻遮罩64A和64B的形成可包括沉積毯覆層（blanket layer），然後圖案化其毯覆層。可使用化學氣相沉積、原子層沉積、或其他類似方法來沉積硬遮罩層60、62、和其他形成蝕刻遮罩64的對應層。
第9A圖繪示了晶圓10一部分的俯視圖。第8圖所示的結構繪示了晶圓10的部分66，如第9A圖所示。在第9A圖中，根據一些實施例，繪示了閘極堆疊56、硬遮罩58、和閘極間隔物38作為平行條（parallel strips）。可在被標記為68的區域中，和在閘極間隔物38之間，形成源極和汲極區42（未繪出）。蝕刻遮罩64A和64B可位在交替的行中。蝕刻遮罩64A和64B可具有不同的長度，其有些比第9圖所示的較長。舉例來說，一些蝕刻遮罩64可延伸橫跨三個或更多個閘極堆疊。第9B圖繪示了在第9A圖中所示的結構的剖面圖，其中剖面圖是從在第9A圖中含B-B線段的垂直平面所獲得。在後續圖示中的後續剖面圖，其圖號具有字母“B”者，除非另外指明，也是從在對應俯視圖中與含B-B線段的垂直平面相同的平面所獲得。
第10A、10B、11、12、13A/13B、和14A/14B圖繪示了第一圖案形成製程，用來形成在硬遮罩層62中的一些接觸插塞的圖案。個別製程繪示於第19圖的製程流程200中的製程218。於是，在全文中，硬遮罩層62被稱作為圖案保留層（pattern-reservation layer）。參考第10B圖，形成三層（tri-layer），其包括底層70、中間層72、和上層74，來覆蓋蝕刻遮罩64。在微影製程中圖案化上層74，以形成開口76。第10A圖繪示了上層74和開口76的俯視圖。開口76形成與蝕刻遮罩64B的一些部分相交的條狀物。根據一些實施例，開口76具有與Y方向平行的長度方向，而個別開口76可橫跨複數個蝕刻遮罩64B的中間部分。
根據一些實施例，以光阻形成上層74，而可以光阻或其他以Six Oy Cz 為基礎的材料來形成底層70（第10B圖）。可以，例如含矽材料，如矽氧氮化物（SiON）或其他類似材料，來形成中間層72。中間層72的厚度T2可介於約200Å和500Å之間。
參考第11圖，使用圖案化的上層74作為蝕刻遮罩來蝕刻中間層72，讓開口76延伸進入中間層72。開口76在中間層72中的部分被稱為開口76A。根據一些實施例，使用異向性蝕刻方法來進行蝕刻。蝕刻方法可選自反應式離子蝕刻，其可使用電感式耦合電漿、電容式耦合電漿、或其他類似方法來執行。製程氣體可包括蝕刻氣體和聚合物形成氣體。根據一些實施例，蝕刻氣體可包括含氟氣體，如CF4 、NF3 、或其組合。聚合物形成氣體可包括碳和氟氣體，如CHF3 、CH2 F2 、CH3 F、C4 F6 、C4 F8 、或其組合。製程氣體的壓力可介於約5mTorr和200mTorr之間。在蝕刻期間的晶圓10的溫度可介於約0°C和50°C之間。在蝕刻製程中，氟與Six Oy Cz 和聚合物形成氣體（如CHF3 、CH2 F2 、CH3 F、C4 F6 、及/或C4 F8 ，其被離子化且分裂為C3 F+ 、C2 F+ 、CF+3 、CF+2 、CF+ 、C4 F- 等）反應，以便產生聚合物Cx Fy Hz 作為在個別開口76A的側壁上的保護層。
調整蝕刻製程的條件，如製程氣體的種類和流速，讓開口76A的側壁傾斜。舉例來說，當導入更多聚合物形成氣體時，開口76A的側壁更加傾斜，且反之亦然，由於形成的聚合物保護中間層72的側壁，隨著蝕刻的進行，造成開口的尺寸越來越小。開口76A側壁的傾斜角度α1可小於約89°，且可介於約85°和30°之間。藉由提供合適的流速比例，其為聚合物形成氣體的流速比蝕刻氣體的流速，可從而達到合適的傾斜角度α1。如此一來，開口76A的底寬度W2小於個別開口76A的頂寬度W1。藉由聚合物形成氣體和蝕刻氣體的比例來影響傾斜角度α1。舉例來說，加入更多聚合物形成氣體，傾斜角度α1變得更小。加入更少的聚合物形成氣體，傾斜角度α1變得更大，並可最終大於90°，若沒有加入聚合物形成氣體。期望底寬度W2小於頂寬度W1，讓後續形成的接觸開口（第17B圖）的寬度減少至小於寬度W1。舉例來說，在上層74中的開口76的最小寬度被微影製程的能力所限制。於是，期望的寬度差（W1-W2）足夠顯著（例如約大於12nm），讓後續形成的接觸開口可顯著地具有較小的寬度。然而，寬度差（W1-W2）不能太大（例如約大於20nm），由於如此會導致製程的困難，和可能地良率流失，基於圖案負載效應（pattern-loading effect）。根據本發明的一些實施例，寬度差（W1-W2）是介於約12nm和20nm之間。根據一些實施例，寬度差（W1-W2）的調整是透過調整流速的流速比例FRPF1 /FREG1 ，其中FRPF1 是聚合物形成氣體的流速，而FREG1 是蝕刻氣體的流速。根據一些實施例，流速比例FRPF1 /FREG1 是介於約0.5和3.0之間。又由於開口76A的側壁是傾斜的，也可藉由選擇中間層72的合適厚度T2，來調整寬度差（W1-W2）。
第12圖繪示了底層70的蝕刻，讓開口76更延伸進入底層70。開口76在底層70中的部分被稱為開口76B。硬遮罩層62因而露出。蝕刻遮罩64B也露出於開口76/76B。開口76B實質上可具有垂直側壁。根據一些實施例，底層70包括Cx Hy Oz 。個別蝕刻氣體可包括氧氣，而聚合物形成氣體可包括SO2 。氧原子與硫原子反應，以形成含硫副產品，其充當為在開口76B側壁上的側壁保護層。藉由選擇合適的流速比例，其為聚合物形成氣體的流速比蝕刻氣體的流速，可達到垂直側壁。
接著，參考第13A和13B圖，使用剩餘的三層作為蝕刻遮罩，來蝕刻硬遮罩層62，且開口76延伸進入硬遮罩層62。開口76在硬遮罩層62中的部分也被稱為開口76C。使用圖案化的中間層72（若有剩餘）和底層70作為蝕刻遮罩，來蝕刻硬遮罩層62。如第13A圖所示，當蝕刻硬遮罩層62時，蝕刻遮罩64B充當部分蝕刻遮罩，讓開口76C被限制在蝕刻遮罩64B的露出部分之間。根據一些實施例，使用異向性蝕刻方法來進行蝕刻。蝕刻方法可選自反應式離子蝕刻（如電感式耦合電漿或電容式耦合電漿）、或其他類似方法。製程氣體可包括蝕刻氣和聚合物形成氣體。根據一些實施例，例如當硬遮罩層62包括矽氧化物時，蝕刻氣體可包括含氟氣體，如CF4 、NF3 、或其組合。聚合物形成氣體可包括CHF3 、CH2 F2 、CH3 F、C4 F6 、C4 F8 、或其組合。製程氣體的壓力可介於約5mTorr和200mTorr之間。在蝕刻期間的晶圓10的溫度可介於約0°C和50°C之間。
也調整蝕刻製程的條件，如製程氣體的種類和流速，讓開口76C的側壁傾斜。開口76C側壁的傾斜角度α2可小於約89°，且可介於約85°和30°之間。藉由選擇合適的流速比例，其為聚合物形成氣體的流速比蝕刻氣體的流速，可達到所欲之傾斜角度α2。如此一來，開口76C的底寬度W4小於個別開口76C的頂寬度W3，其中寬度W3可與寬度W2（第11圖）接近。期望底寬度W4小於頂寬度W3，讓後續形成的接觸開口（第17B圖）的寬度比寬度W3更加減小。寬度差（W1-W2）（第11圖）和（W3-W4）（第13B圖）一起貢獻於所得的接觸開口的尺寸的整體收縮，無須使寬度差（W1-W2）和（W3-W4）中任意一個夠大來導致製程問題。於是，（W3-W4）沒有太大也沒有太小。根據本發明的一些實施例，寬度差（W3-W4）約介於12nm和20nm之間。根據一些實施例，寬度差（W3-W4）的調整是透過調整流速的流速比例FRPF2 /FREG2 ，其中FRPF2 是聚合物形成氣體的流速，而FREG2 是蝕刻氣體的流速。根據一些實施例，流速比例FRPF2 /FREG2 是介於約0.5和3.0之間。此外，藉由選擇硬遮罩層62的合適厚度T1，來調整寬度差（W3-W4）。
在硬遮罩層62的蝕刻之後，移除中間層72，且例如在灰化製程中，移除剩餘的底層70，其使用臭氧或化學溶液，包括NH4 OH、H2 O2 、和H2 O（有時被稱為標準清潔1（Standard Clean 1, SC1）溶液）來進行。第14A和14B圖各別繪示了所得的結構的俯視圖和剖面圖。
也如第14A和14B圖所示，一起使用硬遮罩64B和硬遮罩層62作為蝕刻遮罩來蝕刻硬遮罩層60，讓開口76更延伸進入硬遮罩層60。開口76在底層70中的部分被稱為開口76D。層間介電質49因而露出。開口76D實質上可具有垂直側壁。根據一些實施例，調整蝕刻硬遮罩層60的蝕刻條件，讓開口76D的側壁為垂直的。
硬遮罩60的蝕刻方法可選自反應式離子蝕刻，如電感式耦合電漿、電容式耦合電漿、或其他類似方法。製程氣體可包括蝕刻氣體和聚合物形成氣體。根據一些實施例，例如，當硬遮罩層60包括鎢碳化物，蝕刻氣體可包括含氟氣體，如CF4 、NF3 、或其組合。聚合物形成氣體可包括Cl2 、O2 、或其組合。製程氣體的壓力可介於約5mTorr和200mTorr之間。藉由選擇合適的流動比例，其為聚合物形成氣體的流速比蝕刻氣體的流速，可達到垂直側壁。在蝕刻期間的晶圓10的溫度可介於約0°C和50°C之間。
根據一些實施例，以容易調整聚合物形成的材料，來形成中間層72（第11圖）和硬遮罩層62（第13B圖）。於是，主要是在硬遮罩層62和中間層72中達到開口的收縮。以較不容易調整聚合物形成的材料，來形成底層70（第12圖）和硬遮罩層60（第14B圖）。於是，將在底層70和硬遮罩層60中的開口側壁做為垂直的，來改善製程控制。
第10A/10B至14A/14B圖繪示了，在用來圖案化硬遮罩層62和60的雙重圖案化製程中的第一圖案化製程。第15A、15B、16A、和16B圖繪示了，在用來圖案化硬遮罩層62和60的雙重圖案化製程中的第二圖案化製程。個別製程繪示於第19圖的製程流程200中的製程220。參考第15B圖，形成三層，包括底層80、中間層82、和上層84。底層80、中間層82、和上層84的材料和厚度基本上可各別與底層70、中間層72、和上層74（第10B圖）相同。圖案化上層84，以形成開口86。如第15A和15B圖所示，部分蝕刻遮罩64A在開口86的正下方。第二圖案化製程的細節與第一圖案化製程的細節相似，如第11、12、13A、13B、14A、和14B圖所示，故不在此贅述。所得的結構如第16A、16B、和16C圖所示。在後續圖示中的後續剖面圖，其圖號具有字母“C”者，除非另外指明，也是從在對應俯視圖中與含C-C線段的垂直平面相同的平面所取得。如第16C圖所示，開口76’延伸進入硬遮罩層62和60。開口76’基本上具有相同寬度，其可等同於開口76的寬度W4。
如第16B圖所示，使用硬遮罩層62來保留在雙重圖案化製程的兩個圖案化製程中所形成的圖案。再者，如第16A圖所示，使用蝕刻遮罩64來將長開口76和76’切割至較短的開口，因而將長源極/汲極接觸插塞92（第18A和18B圖）切割至較短的接觸插塞。
第11和15B圖繪示出，在上層74（第11圖）中的開口76和在上層84（第15B圖）中的開口86的寬度為W1。寬度W1可是能使用各別微影製程（包括曝光製程和顯影製程）達到的最小寬度。透過如第11、12、13A/13B、和14A/14B圖所示的製程，減少開口76（和76’）的寬度至W4（第16B圖）。根據一些實施例，寬度差（W1-W4）可介於約29nm和37nm之間。若在單一層中，如中間層72（第11圖）和82（第15B圖），達到寬度的收縮，可能有製程問題，由於達到如此巨大寬度差異可導致顯著的圖案負載效應。根據本發明的一些實施例，收縮量是由兩個以上的層共享，如在三層中的中間層和硬遮罩層62。製程因此更加容易，並減少導致製程問題的可能性。根據本發明的一些實施例，共享收縮量的兩個層的各別層可分攤約總收縮量的1/3和2/3之間，讓兩個層都不會負擔太大的收縮量。
接著，使用圖案化的硬遮罩層62和60作為蝕刻遮罩，來蝕刻於下方的層間介電質49、蝕刻停止層47、層間介電質48、和接觸蝕刻停止層46。個別製程繪示於第19圖的製程流程200中的製程222。所得的結構繪示在第17A、17B、和17C圖中，其中在這些層46至49中的部分開口76和76’是源極/汲極接觸開口。根據本發明的一些實施例，蝕刻遮罩64也充當作為部分蝕刻遮罩。在其他實施例中，在蝕刻這些層46至49之前，移除蝕刻遮罩64。蝕刻遮罩64的移除可是等向性（isotropic）或異向性，且可使用濕蝕刻或乾蝕刻來進行。根據本發明的一些實施例，蝕刻製程是乾蝕刻製程，其進行是使用CF4 、SO2 、HBr-Cl2 -O2 混合物、或HBr-Cl2 -O2 -CF2 混合物等。或者，蝕刻製程是濕蝕刻製程，其進行是使用KOH、四甲銨氫氧化物（tetramethylammonium hydroxide）、CH3 COOH、NH4 OH、H2 O2 、異丙醇（isopropanol, IPA）、或例如HF、HNO3 、和H2 O的溶液。
第18A、18B、和18C圖繪示了在源極/汲極矽化物區90和接觸插塞92的形成中的俯視圖和剖面圖。個別製程繪示於第19圖的製程流程200中的製程224。根據一些實施例，沉積順應金屬層（未繪出），以延伸進入接觸開口76和76’（第17A和17B圖）。可以，例如鈦，來形成金屬層。接者，進行退火製程，讓金屬層位在接觸開口76和76’底部的部分與源極和汲極區42反應，來形成源極/汲極矽化物區90。在退火製程之後，留下金屬層的側壁部分。根據一些實施例，可在退火製程之前，在金屬層上形成額外的導電氮化物層（未繪出），如鈦氮化物。然後以金屬材料填充剩餘的接觸開口，其金屬材料可以鎢、鈷、銅、鋁、或其合金來形成。然後進行平坦化製程，如化學機械拋光製程，將所得的接觸插塞92（包括92A和92B）的頂面齊平，其插塞包括金屬層和金屬材料。如第18A圖所示，接觸插塞92A和92B被蝕刻遮罩64（第10A圖）切短，其遮罩定義了接觸插塞92A和92B的一些末端部分。
參考第18A圖，示意地標記複數個電晶體94（包括94A和94B），其中標註了源極/汲極區42和各別的閘極堆疊56。接觸插塞92（如92A）可充當作為互連一些電晶體的源極/汲極區42和鄰近電晶體的源極/汲極區42的互連結構。
本發明的實施例具有一些有利的特徵。由於開口的收縮，接觸插塞有利地具有小寬度。藉由在複合層中收縮開口的尺寸，所得的開口可具有的寬度，其顯著地小於微影製程最小寬度。本發明實施例的收縮方法導致減少製程問題的可能性，由於在各層中的收縮量沒有過度。
根據本發明的一些實施例，一種方法包括形成第一硬遮罩層；於第一硬遮罩層上方形成第二硬遮罩層；形成三層，其三層包括：於第二硬遮罩層上方的底層，於底層上方的中間層，於中間層上方的圖案化上層；使用圖案化上層作為蝕刻遮罩，來蝕刻中間層，以將在圖案化上層中的開口延伸進入中間層，其中在中間層中的開口具有第一部分，而第一部分具有第一頂寬度和小於第一頂寬度的第一底寬度；蝕刻底層，以將開口延伸進入底層；以及蝕刻第二硬遮罩層，以將開口延伸進入第二硬遮罩層，其中在第二硬遮罩層中的開口具有第二部分，而第二部分具有第二頂寬度和小於第二頂寬度的第二底寬度。在一實施例中，此方法更包括蝕刻第一硬遮罩層，以將開口延伸進入第一硬遮罩層，其中開口在第一硬遮罩層中的一部份實質上具有垂直和筆直側壁；以及蝕刻於第一硬遮罩層下方的下方層，以將開口延伸進入下方層。在一實施例中，此方法更包括填充導電材料進入下方層，以形成接觸插塞。在一實施例中，此方法更包括在形成接觸插塞之後，移除第一硬遮罩層和第二硬遮罩層的剩餘部分。在一實施例中，此方法更包括在形成三層之前，於第二硬遮罩層上方形成圖案化蝕刻遮罩，其中當蝕刻第二硬遮罩層，以將開口延伸進入第二硬遮罩層時，蝕刻遮罩將開口分離成兩個部分。在一實施例中，第一頂寬度和第一底寬度具有第一差值，第二頂寬度和第二底寬度具有第二差值，而第一頂寬度和第二底寬度具有第三差值，且第一差值約在第三差值的1/3和2/3之間。在一實施例中，開口在底層中的一部份實質上具有垂直和筆直側壁。
根據本發明的一些實施例，一種方法包括於電晶體的源極/汲極區上方形成層間介電質；於層間介電質上方形成第一硬遮罩層；於第一硬遮罩層上方形成三層，包括於第一硬遮罩層上方形成底層，於底層上方形成中間層，於中間層上方形成上層，其中上層具有一開口；使用上層作為蝕刻遮罩來蝕刻中間層和底層，其中開口延伸進入中間層和底層，其中開口的寬度從在中間層頂面層級的第一頂寬度收縮至在底層底面層級的第一底寬度；蝕刻第一硬遮罩層，其中開口延伸進入第一硬遮罩層，其中開口的寬度從第一底寬度收縮至在第一硬遮罩層底面層級的第二底寬度；以及使用第一硬遮罩層作為蝕刻遮罩的一部份來蝕刻層間介電質，以將開口延伸進入層間介電質。在一實施例中，此方法更包括在層間介電質中形成接觸插塞，其中電性耦合接觸插塞至源極/汲極區。在一實施例中，此方法更包括於層間介電質上方形成第二硬遮罩層，其中第二硬遮罩層是在第一硬遮罩層下方；以及在蝕刻層間介電質之前，蝕刻第二硬遮罩層，其中開口延伸進入第二硬遮罩層，且開口在第二硬遮罩層中的一部份實質上具有垂直側壁。在一實施例中，中間層包括矽氧氮化物，且使用製程氣體來蝕刻中間層，其氣體包括：含氟氣體選自CF4 、NF3 、和其組合所組成的族群；以及聚合物形成氣體選自CHF3 、CH2 F2 、CH3 F、C4 F6 、C4 F8 、和其組合所組成的族群。在一實施例中，此方法更包括在形成三層前，於第一硬遮罩層上方形成圖案化蝕刻遮罩，其中當蝕刻第一硬遮罩層，以將開口延伸進入第一硬遮罩層時，圖案化的蝕刻遮罩將開口分離成兩部分。在一實施例中，形成圖案化的蝕刻遮罩包括形成矽層。在一實施例中，第一頂寬度和第一底寬度之間的差值約在第一頂寬度和第二底寬度之間的差值的1/3和2/3之間。
根據本發明的一些實施例，一種方法包括於層間介電質上方形成第一硬遮罩層；於第一硬遮罩層上方形成第二硬遮罩層；形成三層，其三層包括：於第二硬遮罩層上方的底層，於底層上方的中間層，以及於中間層上方的圖案化上層，其中在圖案化上層中形成開口，且開口具有頂寬度；以及將開口延伸進入中間層、底層、第二硬遮罩層、和第一硬遮罩層，其中開口在第二硬遮罩層中的一部份具有第一頂寬度和小於第一頂寬度的第一底寬度，以及開口在第一硬遮罩層中的一部分具有頂寬度和與頂寬度相等的底寬度。在一實施例中，此方法更包括使用第一硬遮罩層和第二硬遮罩層之一作為蝕刻遮罩，來蝕刻下方層。在一實施例中，第一底寬度比第一頂寬度小約12nm和20nm之間的差值。在一實施例中，開口在中間層中的一部份具有第二頂寬度和小於第二頂寬度的第二底寬度，且第一頂寬度比第一底寬度大第一差值，第二頂寬度比第二底寬度大第二差值，且第一差值是第一差值和第二差值的總和的約1/3和2/3之間。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能輕易地以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍下，做各式各樣的改變、取代和替換。
10:晶圓 20:基底 22:（淺溝槽）隔離區 22A:頂面 24:半導體條 24’:凸出鰭 30:虛置閘極堆疊 32:虛置閘極介電質 34:虛置閘極電極 36:硬遮罩層 38:閘極間隔物 40:凹槽 42:磊晶區（源極/汲極區） 43:氣隙 46:接觸蝕刻停止層 47:蝕刻停止層 48:層間介電質 49:（第二）層間介電質 52:（替換）閘極介電質 54:金屬閘極電極 56:替換閘極堆疊 58:硬遮罩 60:硬遮罩層 62:硬遮罩層 64:蝕刻遮罩 64A:蝕刻遮罩 64B:蝕刻遮罩 66:部分 68:區域 70:底層 72:中間層 74:上層 76/76A/76B/76C/76D/76’:開口 80:底層 82:中間層 84:上層 86:開口 90:源極/汲極矽化物區 92:源極/汲極接觸插塞 92A:接觸插塞 92B:接觸插塞 94:電晶體 94A:電晶體 94B:電晶體 200:製程流程 202/204/206/208/210/212/214/216/218/220/222/224:製程 T1:厚度 T2:厚度 W1:（第一）頂寬度 W2:（第一）底寬度 W3:（第二）頂寬度 W4:（第二）底寬度 α1:傾斜角度 α2:傾斜角度
以下將配合所附圖式詳述本揭露之各面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。 第1至8、9A、9B、10A、10B、11、12、13A、13B、14A、14B、15A、15B、16A、16B、16C、17A、17B、17C、18A、18B、和18C圖是根據一些實施例繪示了鰭式場效電晶體（Fin Field-Effect Transistors, FinFETs）形成的中間階段的透視圖、俯視圖、和剖面圖。 第19圖是根據一些實施例繪示了形成鰭式場效電晶體的製程流程。
無
10:晶圓
20:基底
38:閘極間隔物
46:接觸蝕刻停止層
47:蝕刻停止層
48:層間介電質
49:(第二)層間介電質
52:(替換)閘極介電質
54:金屬閘極電極
56:替換閘極堆疊
58:硬遮罩
60:(第一)硬遮罩層
62:(第二)硬遮罩層
64:蝕刻遮罩
64A:蝕刻遮罩
70:底層
72:中間層
76:開口
76C:開口
T1:厚度
W3:(第二)頂寬度
W4:(第二)底寬度
α2:傾斜角度

Claims (10)

  1. 一種積體電路結構的形成方法，包括：形成一第一硬遮罩層；形成一第二硬遮罩層於該第一硬遮罩層上方；形成一三層(tri-layer)，該三層包括：一底層於該第二硬遮罩層上方；一中間層於該底層上方；以及一圖案化上層於該中間層上方；用該圖案化上層作為一蝕刻遮罩來蝕刻該中間層，以將在該圖案化上層中的一開口延伸進入該中間層，其中該開口具有在該中間層中的一第一部分，且該第一部分具有一第一頂寬度和小於該第一頂寬度的一第一底寬度；蝕刻該底層，以將該開口延伸進入該底層，其中在該底層中的該開口的一部分實質上具有垂直側壁；以及蝕刻該第二硬遮罩層，以將該開口延伸進入該第二硬遮罩層，其中在該第二硬遮罩層中的該開口具有一第二部分，且該第二部分具有一第二頂寬度和小於該第二頂寬度的一第二底寬度。
  2. 如申請專利範圍第1項所述之積體電路結構的形成方法，更包括：蝕刻該第一硬遮罩層，以將該開口延伸進入該第一硬遮罩層，其中在該第一硬遮罩層中的該開口的一部分實質上具有垂直側壁；蝕刻在該第一硬遮罩層下方的一下方層，以將該開口延伸進入該下方層；以及將一導電材料填入該下方層，以形成一接觸插塞。
  3. 如申請專利範圍第2項所述之積體電路結構的形成方法，更包括在形成該接觸插塞之後，移除該第一硬遮罩層和該第二硬遮罩層的剩餘部分。
  4. 如申請專利範圍第1項所述之積體電路結構的形成方法，更包括在形成該三層前，於該第二硬遮罩層上方形成一圖案化蝕刻遮罩，其中當蝕刻該第二硬遮罩層，以將該開口延伸進入該第二硬遮罩層時，該蝕刻遮罩將該開口分離成兩部分。
  5. 如申請專利範圍第1-4項中任一項所述之積體電路結構的形成方法，其中該第一頂寬度和該第一底寬度具有一第一差值，該第二頂寬度和該第二底寬度具有一第二差值，且該第一頂寬度和該第二底寬度具有一第三差值，且該第一差值是約在該第三差值的1/3和2/3之間。
  6. 一種積體電路結構的形成方法，包括：形成一層間介電質於一電晶體的一源極/汲極區上方；形成一第一硬遮罩層於該層間介電質上方；形成一三層於該第一硬遮罩層上方，包括：形成一底層於該第一硬遮罩層上方；形成一中間層於該底層上方；以及形成一上層於該中間層上方，其中該上層具有一開口；用該上層作為一蝕刻遮罩，以蝕刻該中間層和該底層，其中該開口延伸進入該中間層和該底層，其中該開口的寬度從在該中間層的一頂面層級的一第一頂寬度收縮至在該底層的一底面層級的一第一底寬度，且該底層實質上具有垂直側壁；蝕刻該第一硬遮罩層，其中該開口延伸進入該第一硬遮罩層，其中該開口的寬度從該第一底寬度收縮至在該第一硬遮罩層的一底面層級的一第二底寬度；以及使用該第一硬遮罩層作為一蝕刻遮罩的一部分來蝕刻該層間介電質，以將該開口延伸進入該層間介電質。
  7. 如申請專利範圍第6項所述之積體電路結構的形成方法，更包括：形成一第二硬遮罩層於該層間介電層上方，其中該第二硬遮罩層是在該第一硬遮罩層下方；以及在蝕刻該層間介電層之前，蝕刻該第二硬遮罩層，其中該開口延伸進入該第二硬遮罩層，且在該第二硬遮罩層中的該開口的一部分實質上具有一垂直側壁。
  8. 如申請專利範圍第6項所述之積體電路結構的形成方法，其中該第一硬遮罩層具有在約15nm和60nm之間的厚度，且在該第一硬遮罩層中的該開口的一部分具有小於約89°的傾斜角度。
  9. 如申請專利範圍第6項所述之積體電路結構的形成方法，其中該中間層包括氮氧化矽，且蝕刻該中間層所使用的一製程氣體包括：一含氟氣體，選自CF4、NF3、及其組合所組成的族群；以及一聚合物形成氣體，選自CHF3、CH2F2、CH3F、C4F6、C4F8、及其組合所組成的族群。
  10. 一種積體電路結構的形成方法，包括：形成一第一硬遮罩層於一層間介電質上方；形成一第二硬遮罩層於該第一硬遮罩層上方；形成一三層，該三層包括：一底層於該第二硬遮罩層上方；一中間層於該底層上方；以及一圖案化上層於該中間層上方，其中在該圖案化上層中形成一開口；以及將該開口延伸進入該中間層、該底層、該第二硬遮罩層、和該第一硬遮罩層，其中在該中間層中的該開口的一第一部分具有一第一頂寬度和小於該第一頂寬度的一第一底寬度，在該第二硬遮罩層中的該開口的一第二部分具有一第 二頂寬度和小於該第二頂寬度的一第二底寬度，以及在該第一硬遮罩層中的該開口的一第三部分具有一第三頂寬度和與該第三頂寬度相等的一第三底寬度。
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