TWI705501B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI705501B
TWI705501B TW106117448A TW106117448A TWI705501B TW I705501 B TWI705501 B TW I705501B TW 106117448 A TW106117448 A TW 106117448A TW 106117448 A TW106117448 A TW 106117448A TW I705501 B TWI705501 B TW I705501B
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Taiwan
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layer
interface
source
channel
channel structure
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TW106117448A
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TW201820480A (zh
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葉凌彥
張智勝
蔡惠銘
林佑明
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台灣積體電路製造股份有限公司
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Abstract

一種包括場效電晶體(field effect transistor,FET)元件的半導體元件，包括基材與由二維材料形成的通道結構。於通道結構上形成界面層。於界面層上方形成閘極堆疊，閘極堆疊包含閘極電極層與閘極介電層。於界面層中之開口的上方形成源極/汲極接點。源極/汲極接點具有與界面層接觸之側面接點以及與通道結構接觸之側面接點與表面接點。

Description

半導體元件及其製造方法
此揭露係有關於一種半導體積體電路與其製造方法，且特別是有關於二維元件之原子層製造。
隨著電晶體製程技術的進步，電晶體的尺寸縮小並使積體電路中的電晶體密度因此增加。然而，關閉狀態電流(off-state current)隨電晶體之通道長度縮短而大幅增加，其成因如短通道效應(short channel effect)。對通道長度短於20奈米之電晶體來說，此效應為能否進一步提升電晶體密度之主要挑戰。已知降低通道厚度為抑制短通道效應的方法之一。超薄通道電晶體(Ultra-thin body transistor,UBT)可採用超薄通道半導體材料(ultra-thin semiconductor channel material)來抑制短通道效應。二維半導體被預期來作為超薄通道電晶體中之通道材料。二維材料，諸如過渡金屬二硫族化物(transition metal dichalcogenides,TMD)、石墨烯(graphene)與黑磷(black phosphorus)，皆被視為極具潛力可用於場效電晶體(field-effect transistor,FET)元件中電晶體通道的候選材料。傳統場效電晶體元件的製造方法可能無法在 原子級的精準度下控制層厚與界面組成，而此為未來奈米級電子元件製程世代的首要重點。
目前亟需能於閘極介電層與具有超薄型通道厚度之二維通道材料之間達成所欲之界面的解決方法，通道厚度可小於各閘極寬度的四分之一(如，20奈米)。
依據本揭露之多個實施方式，一種半導體元件製造方法包含：沉積二維材料於基材上方以形成通道結構；形成具有第一厚度之鈍化結構於該通道結構上方；形成分隔結構以定義元件區；藉由使用原子層蝕刻(atomic layer etch,ALE)程序，自每一元件區內之鈍化結構移除預定數量之層，以形成薄型鈍化結構；形成閘極堆疊於每一薄型鈍化結構上方；以及形成源極/汲極接點於元件區中，源極/汲極接點具有與通道結構接觸之側面接點。
依據本揭露之多個實施方式，一種製造半導體元件的方法，包含於基材上方形成通道結構；於通道結構上方形成界面結構；形成穿過基材的多個分隔結構，以定義出多個元件區；移除界面結構的受損層；通過原子層蝕刻製程，自各元件區的界面結構中移除預定數量的層，以形成多個分隔薄型界面結構；形成閘極堆疊於分隔薄型界面結構上方；通過移除部分的分隔結構以及分隔薄型界面結構，形成多個源極/汲極接點於元件區內，並使源極/汲極接點具有與通道結構及分隔薄型界面結構接觸的側面接點。
依據本揭露之多個實施方式，一種半導體元件包含場效電晶體元件，場效電晶體元件包含基材；由二維材料形成的通道結構；形成於通道結構上的界面層；形成於界面層上方的閘極堆疊，閘極堆疊包含閘極電極層與閘極介電層；以及多個源極/汲極接點形成於界面層的多個開口上方，其中界面層連續且完全地覆蓋通道結構，通道結構在源極/汲極接點之間延伸，源極/汲極接點接觸界面層的側面，以及源極/汲極接點接觸通道結構的側面以及頂面。
100:流程圖
S101-S106:步驟
202:基材
204:通道結構
200A、200B、200C、200D、200E、200F、200G、200H:X軸切圖
206:鈍化結構
208:分隔結構
210:元件區
211:受損層部分
212、214:薄型鈍化結構
213:乾淨鈍化結構
216:閘極介電層
220:閘極堆疊
222:閘極電極層
224:高k值介電材料
226:間隔
230:源極/汲極接點
232、234:側面接點
236:表面接點
240:金屬層
100:流程圖
300:半導體元件
t:厚度
t1:厚度
第1圖為繪示依據本揭露之一或多個實施方式之例示性流程圖，用以描述二維半導體元件的原子層製造。
第2A圖至第2H圖為繪示依據本揭露之一或多個實施方式的例示性二維視圖，用以描述於原子層製造不同階段的二維半導體元件。
第3圖為繪示依據本揭露之一或多個實施方式之二維金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)元件的簡化圖，用以描述二維金氧半場效電晶體元件之結構細節。
應理解，以下揭示內容提供用於實施本揭露之不同特徵之諸多不同實施例或實例。下文描述組件及排列之特定 實施例或實例以簡化本揭露。當然，此等僅係示例性且並非意欲為限制性。舉例而言，部件之尺寸不限於所揭示範圍或值，而是可取決於元件之製程條件及/或所期望性質。此外，隨後之描述中在第二特徵上方或在第二特徵上形成第一特徵可包含其中第一特徵及第二特徵直接接觸形成之實施例且亦可包含其中可插入第一特徵及第二特徵地形成額外特徵以使得第一特徵及第二特徵可不直接接觸之實施例。為簡單且清晰起見，各特徵可按不同比例而任意繪製。
進一步而言，為了便於描述，本文可使用諸如「下面」、「下方」、「下部」、「上方」、「上部」及類似者等空間相對性術語來描述如圖中所圖示之一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了圖中所描繪之定向外，空間相對性術語意欲囊括使用或操作中之元件之不同定向。設備可經其他方式定向(旋轉90度或處於其他定向)且因此可同樣解讀本文所使用之空間相對性描述詞。另外，術語「由…製成」可意指「包括」或「由…組成」。
依據本揭露之一或多個實施方式，第1圖為例示性流程圖100，用以描述二維半導體元件如金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)之原子層製造。流程圖100僅僅說明整體製造程序之相應部分。應了解於可於第1圖所示作業之前、中及後加入額外作業，且於下文描述的一些作業可因本方法之額外實施方式而被替換或是刪除。作業/程序之順序可互相調換。
於第1圖之S101中，將二維材料形成於基材202 上方以形成通道結構204，如第2A圖中之X軸切圖200A所示。依據一些實施方式，舉例而言，基材202可為p型矽基材，有介於約1×1015cm-3至約3×1015cm-3的雜質濃度。於其他實施方式中，基材202為n型矽基材，有介於約1×1015cm-3至約3×1015cm-3的雜質濃度。在一些實施方式中，矽基材晶向為(100)。
可選擇的，基材可包含其他元素型半導體(elemental semiconductor)如鍺，化合物半導體(compound semiconductor)，包括IV-IV族化合物半導體諸如SiC及SiGe，以及III-V族化合物半導體諸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或以上之任意組合。在一或多個實施方式中，基材可為絕緣體上矽(silicon-on-insulator,SOI)基材之矽層。非晶基材諸如非晶矽或非晶碳化矽，或絕緣材料如氧化矽，亦可用來作為基材。基材可包括多種適當摻雜雜質(如，p型或n型導電性)的區域。
在一些實施方式中，於X軸切圖200A中所示之通道結構204，係由二維材料所形成，且隨後形成為場效電晶體之通道、延伸及源極/汲極區。二維材料通常僅為幾層厚且以一種強鍵結層的形式存在，而層與層間僅具有微弱的凡得瓦力(Van der Waals force)，能藉機械或化學的方法將其剝離為單獨、原子級薄度之層。二維材料為超薄通道電晶體之通道材料極具潛力之候選。二維材料之例子如石墨烯(graphene)、石墨炔(graphyne)、硼烯(borophene)、矽烯(silicene)、鍺烯 (germanene)、過渡金屬二硫族化物(transition metal dichalcogenides,TMD)、黑磷及類似物。某些面向中，所揭露的二維通道可為包括TMD之二維半導體(如二硫化鉬)、黑磷或石墨烯。在一些實施方式中二維半導體可包括一或多層，且其厚度可介於約0.5奈米至100奈米之間。僅幾層之二維半導體的其中一項優勢特徵為其高電子遷移率(electron mobility,μe)，其值介於約50cm2/V-sec至1000cm2/V-sec之間或甚至更高。應了解，當把整塊矽切至與一般二維材料薄膜同一量級的厚度(如，約2奈米)時，其遷移率會劇烈衰降。
應了解，廣泛用於許多積體電路(integrated-circuit,IC)中MOSFET元件的閘極長度不斷被縮小與降低，以增加積體電路中電晶體的封裝密度與增快其執行速度。然而，大幅下降的閘極長度招致了不樂見的短通道效應，如變高的關閉狀態逸漏電流。抑制短通道效應的方法之一為採用降低厚度之半導體通道，即為超薄通道電晶體(Ultra-thin body transistor,UTB transistor)。舉例而言，要有效抑制閘極長度小於約20奈米之電晶體的短通道效應，其中一種方法即採用降低厚度(如，小於5奈米)之半導體通道。若一電晶體之半導體通道厚度小於其閘極長度的三分之一或四分之一，則該電晶體通常被稱為超薄型通道電晶體。超薄通道電晶體可採用超薄型通道材料。
二維材料，為僅具幾層原子之晶型材料，為極具潛力的超薄通道之候選材料。其中一種具有高遷移率之二維材料為黑磷。黑磷為層化材料而單一層之黑磷稱為黑磷烯 (phosphorene)。黑磷為半導體，其直接能隙(direct band gap)單一層時約1.5電子伏特，至五層時於布里昂區(Brillouin zone)之Γ點(center point of Brillouin zone)處之約為0.59電子伏特之間。
在一些實施方式中，可藉由二維材料(如黑磷)與此處描述之原子層沉積(atomic layer deposition,ALD)來形成通道結構204。沉積方法之描述僅為示例，且除非特別指明，並無意限制未討論之事項。舉一例而言，正交系(orthorhombic)黑磷可由紅磷(red phosphorus)經由使用錫及/或錫碘化物作為添加物的短程化學轉移反應(short-way transport reaction)生長而成。在另一例中，黑磷可於約攝氏200度至250度之溫度與約13,000,kg/cm2的高壓下由白磷(white phosphorus)合成。二維材料之厚度可由沉積時間控制。在一實施方式中，一段期間所沉積出的多層(以單一層為例)黑磷烯之厚度約為0.53奈米。在一些實施方式中，厚度可介於1個單一層至20個單一層(如，厚度約10.6奈米)之間。如下所討論，在一些實施方式中，不同區域(如通道區與源極/汲極區)之厚度可能有所變化。在一些實施方式中，主動區(active region)之厚度變化可具有連續性。在其他實施方式中，厚度介於約1個單一層至10個單一層(如，厚度約5.3奈米)之間。
第1圖之S102中，具有第一厚度t的鈍化結構206形成於通道結構204上方，如第2B圖中之X軸切圖200B所示。鈍化結構206為界面層，用以促進閘極介電層與具有超薄通道厚度之二維通道材料層接合。習知方法大體上無法在原子級精 準度下準確控制層厚與界面組成，而其對未來奈米電子元件技術世代而言相當關鍵。此外，如何在二維材料上形成高品質且具低有效氧化物厚度(effective oxide thickness,EOT)之閘極介電質亦為一大挑戰。此肇因於此材料之二維特性，即缺乏成核點。因此，多數元件之製造若非使用較厚的氧化層，則無可避免得誘發懸浮鍵(dangling bond)以促進成核使氧化層生長。
此技術之鈍化結構206可解決以上問題，並讓介電層與通道結構204間得以具有所希望之無懸浮鍵界面。在一些實施方式中，鈍化結構206可由原子層沉積或化學氣相沉積程序沉積。在一些實施方式中，鈍化結構206為二維絕緣材料，如六方氮化硼(hexagonal boron nitride,h-BN)。舉例而言，當通道結構204使用二硫化鉬時，鈍化結構可為氮化硼。氮化硼為寬能隙之化合物，具有良好的物理特性與化學穩定度。六方氮化硼包含交錯排列為蜂巢狀的硼原子與氮原子，包含由sp2軌域鍵結之二維層。每一層之六方氮化硼具有強共價鍵所鍵結之硼原子與氮原子，而各層間則由弱凡得瓦力拉住，與石墨中之情況類似。因此，可藉微機械剝離(micromechanical cleavage)由整塊氮化硼結晶撥下六方氮化硼薄膜，並將其作為介電層。亦可對氮化硼粒子進行超聲波處理(ultrasonication)與高能電子束輻照(high-energy electron beam irradiation)來形成少數層的六方氮化硼。
在第1圖的S103中，如第2C圖中之X軸切圖200C所示，形成分隔結構208以定義出複數個元件區210。分隔結 構208之形成為已知之程序。舉例而言，分隔結構208可為淺凹槽分隔(shallow trench isolation,STI)結構。製造分隔結構208之步驟包含：於製程中之元件(例如，第2B圖中之200B)中蝕刻出凹槽樣式；沉積一或更多介電層材料(如二氧化矽)以填充凹槽；以及藉由化學機械平坦化(chemical-mechanical planarization,CMP)，移除多餘之介電質。分隔結構208可包含一或多層藉由低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)、電漿化學氣相沉積(plasma-enhanced chemical vapor deposition)或可流動式化學氣相沉積(flowable chemical vapor deposition)所沉積的絕緣材料，諸如氧化矽、氮氧化矽或氮化矽。於可流動式化學氣相沉積中，沉積之材料為可流動式介電材料，而非氧化矽。可流動式介電材料，正如其名，可在沉積過程中流動，以填充高縱橫比之間隙或空間。一般來說，會在含矽的前體(precursor)中加入多種化學物質以使沉積之膜得以流動。在一些實施方式中，加入氮氫鍵結。可流動式介電質前體，特別是可流動式氧化矽前體，舉例而言包含silicate、siloxane、methyl silsesquioxane(MSQ)、hydrogen silsesquioxane(HSQ)、MSQ/HSQ、perhydrosilazane(TCPs)、perhydropolysilazane(PSZ)、tetraethyl orthosilicate(TEOS)或sily-amine(如trisilylamine,TSA)。這些可流動式氧化矽材料由多個作業程序形成。沉積完可流動式膜後，將其固化並退火以移除不需要的元素以形成氧化矽。當不需要的元素被移除時，可流動式膜 收縮且密度變高。在一些實施方式中，執行多道退火程序。可流動式膜經過不只一次的固化與退火。可於可流動式膜中摻雜硼及/或磷化物。在一些實施方式中，分隔結構208由一或多層之自旋玻璃(spin on glass,SOG)、SiO2、SiON、SiOCN及/或摻氟矽玻璃(fluorine-doped silicate glass,FSG)所形成。
使用化學機械平坦化技術以移除多餘介電質的步驟使分隔結構208之上表面與鈍化結構206之上表面切齊。然而，形成分隔結構的過程中可能會傷害到鈍化結構。可由原子層蝕刻(atomic layer etch,ALE)技術清除受損的鈍化結構206。舉例而言，如第2D圖中的X軸切圖200D所示，由虛線標示出包含受損層的部分211，將該部分移除以形成具有厚度t1的乾淨鈍化結構213。
回到第1圖中的流程圖100，於S104中，從每個元件區210中的鈍化結構206中移除預定數量之層，以形成薄型鈍化結構(如，212與214)，如第2E圖中之X軸切圖200E所示。第一厚度t已經因受損層之移除而降至厚度t1，然此厚度仍需進一步降低以達成各元件對鈍化結構厚度的要求。此步驟之執行乃因為位於二維通道上之鈍化層(如，二維介電界面)經常必須是超薄厚度，且一晶片之不同元件各有不同之所欲厚度。原子層蝕刻方法可移除任何不需要的殘餘物，並協助對元件結構進行圖案化(pattern)/蝕刻以達到高效能。
舉例而言，可藉由原子層蝕刻程序在原子級的精準度下使鈍化結構206變薄，使其厚度t1降低。因移除所形成的薄型鈍化結構可達成多種多閘極氧化物(multi-gate oxide) 應用的規範。舉例而言，薄型鈍化結構212與214可應用於兩種不同的電晶體(如，核心(core)電晶體和輸入/輸出(I/O)電晶體)，兩種電晶體具有不同的閘極氧化物厚度(如，介於約1-100層之間，每層約為0.5奈米)。薄型鈍化結構212與214為閘極氧化物的一部分，閘極高k值介電質形成於這些鈍化結構上，將如於此處之說明。
於第1圖的S105中，閘極堆疊220形成於每個薄型鈍化結構212與214上方，如第2F圖中之X軸切圖200F所示。在一些實施方式中，閘極堆疊200為已知之結構並包含閘極介電層、閘極電極層222以及間隔226，且閘極堆疊200形成於各個薄型鈍化結構(如，212與214)上方。在一些實施方式中，閘極介電層包含高k值介電材料224以及薄型鈍化結構212與214(如，界面層)。高k值介電材料224可包含金屬氧化物。用於高k值介電材料224之金屬氧化物，可包含各種金屬之氧化物，舉例而言，所述金屬包含：Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu及/或以上之任意混和。在一些實施方式中，閘極介電層之厚度介於約0.5奈米至約10奈米之間。在另一實施方式中，閘極堆疊220包含閘極電極層222以及間隔226，且閘極堆疊220形成於各個薄型鈍化結構(如，212與214)上方。在此實施方式之中，位於閘極電極下方之薄型鈍化結構(212與214)作為閘極介電質，於其上方形成高k值介電質。
在一些實施方式中，閘極電極層222為多晶矽。 在一些實施方式中，藉由使用包含氮化矽層與氧化物層之硬遮罩(hard mask)來對多晶矽層進行圖案化。於其他實施方式之中，閘極電極層222包含單層或多層之結構。進一步而言，閘極電極層222可為摻雜之多晶矽，其可為均勻摻雜或不均勻摻雜。在一些其他的實施方式中，閘極電極層222包含金屬，諸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi以及其他功函數與基材材料相容的導電材料，或以上之任意組合。用於閘極電極層222之電極層可由適當之程序形成，諸如原子層沉積、化學氣相沉積、物理氣相沉積、電鍍或以上之任意組合。在一些實施方式中，閘極電極層222(沿X軸方向)之寬度介於約30奈米至約60奈米之間。
第1圖的S106中，源極/汲極接點230形成於元件區中，如第2G圖中之X軸切圖200G所示。對分隔結構208與薄型鈍化結構212及214進行圖案化與蝕刻後，形成源極/汲極接點230，使得源極/汲極接點230具有與薄型鈍化結構212及214接觸之側面接點以及與通道結構204接觸之側面接點及表面接點。此為本技術具優勢之特徵，此特徵提供了電晶體之源極/汲極接點230更大的接觸面積，而使接觸電阻降低。
在一或更多個實施方式中，可用作源極/汲極接點230之範例材料包含Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi以及其他具有適當功函數之導電材料，或以上之任意組合。在一些實施方式中，源極/汲極接點230可由諸如原子層沉積、化學氣相沉積、物理氣相沉積或其他適當之沉積技術沉積而成。在一些實施方式中，可執行一選擇性的退火 程序，舉例而言，可執行約介於250度至350度攝氏間的退火程序以改善金屬至源極/汲極間的接觸電阻。上述所提之程序概念可整合進現有之MOSFET製造程序，且可施行於多種技術節點，諸如但不限於10奈米、7奈米、5奈米的技術節點。
下一步驟，如第2H圖之X軸切圖200H所示，為在閘極電極222以及源極/汲極接點230上方形成金屬層240。金屬層240之形成包含對金屬層(如，鋁、鎢以及類似物)進行圖案化與沉積，舉例而言，藉由已知的沉積程序，諸如化學氣相沉積、原子層沉積、物理氣相沉積或以上之任意組合。金屬層240作為晶片上不同元件之連接層(interconnect)。
依據此揭露的一或多個實施方式，第3圖為闡釋半導體元件300細部結構之簡圖。半導體元件300之一例包含場效電晶體元件，如MOSFET元件。半導體元件300包含基材202、通道結構204、薄型鈍化結構212與214、閘極堆疊220以及源極/汲極接點230。通道結構204由二維材料形成，如前述所解釋。電晶體的實際通道為一部分的通道結構204，其位於閘極堆疊220的下方。薄型鈍化結構212與214如上述所討論且由二維介電材料所形成。閘極堆疊220包含閘極電極層222，且閘極介電層216形成於薄型鈍化結構層212與214上方以作為界面層。在一些實施方式中，閘極介電層216由位於薄型鈍化結構212與214及閘極電極層222間的薄型鈍化結構212與214所形成。在一些實施方式中，閘極介電層216可包含高k值介電質。源極/汲極接點230形成於閘極介電層216與分隔結構208的開口上方。
在一些實施方式中，源極/汲極接點230具有與閘極介電層216接觸之側面接點232以及與通道結構204接觸之側面接點234及表面接點236，如前述參照第2G圖中之描述。與通道結構204接觸之表面接點236沿與側面接點234垂直之第一方向(X軸方向)延伸。通道結構204包含二維半導體，諸如二硫化鉬、黑磷以及石墨烯。於一實施方式中，界面層包含二維絕緣材料，諸如六方氮化硼。閘極堆疊包含高k值介電材料及上述所討論之閘極電極。
應了解，此處並無必要討論到所有優點，就所有實施方式及範例而言，並不必要具有特定之優點，且其他實施方式及範例可提供不同之優點。
依據本揭露之一面向，一種半導體元件的製造方法包含於基材上方形成二維材料以形成通道結構。於通道結構上方形成具有第一厚度的鈍化結構。形成分隔結構以定義出複數個元件區。藉由原子層蝕刻程序自每個元件區中的鈍化結構移除預定數量之層以形成多個薄型鈍化結構。閘極堆疊形成於每個薄型鈍化結構上方，且源極/汲極接點形成於元件區中。在一些實施方式中，源極/汲極接點具有與二維半導體材料及二維介電材料接觸之側面接點。
在一些實施方式中，二維材料包含半導體二維材料，包含黑磷；且鈍化結構包含二維絕緣材料，包含氮化硼。此方法可進一步使用原子層沉積程序形成通道結構及鈍化結構。在一些實施方式中，第一厚度可介於約100-200層之間。二維材料包含半導體二維材料，包含二硫化鉬；且鈍化結構包 含二維絕緣材料，包含氧化鋁。移除一部分的分隔結構及薄型鈍化結構，以使源極/汲極接點具有與通道結構及薄型鈍化結構接觸之側面接點。在一些實施方式中，二維材料包含二維半導體諸如TMD(包含二硫化鉬)、黑磷或graphene。閘極堆疊包含形成於薄型鈍化結構上方之高k值氧化物。在一些實施方式中，每一薄型鈍化結構具有不同的厚度，該厚度介於約1-100層的二維半導體材料之間。此外，基材的材料包含：Si、SiO2、Ge或覆有介電材料的矽(silicon on insulator)等。
依據本揭露的另一面向，一種製造半導體的方法包含於基材上方形成通道結構。於通道結構上方形成界面結構。形成穿過基材的分隔結構以定義出元件區。移除界面結構之受損層。藉由原子層蝕刻程序，自各個元件區之界面結構中移除所欲之層數，以形成分隔薄型界面結構。閘極堆疊形成於每一薄型界面結構上方。藉由移除部分的分隔結構以及分隔薄型界面結構，形成源極/汲極接點於元件區內，並使源極/汲極接點具有與通道結構及分隔薄型鈍化結構接觸之側面接點。
依據本揭露之又一面向，半導體元件包含場效電晶體元件，如MOSFET。場效電晶體元件包含基材以及由二維材料形成的通道結構。於通道結構上形成界面層。於界面層上方形成閘極堆疊，閘極堆疊包含閘極電極層與閘極介電層。源極/汲極接點形成於界面層的開口上方。源極/汲極接點具有與界面層接觸的側面接點以及與通道結構接觸的側面接點及表面接點。
上文概述數個實施例或實例之特徵以使熟習此項 技術者可較佳地理解本揭露之態樣。熟習此項技術者應瞭解，其可容易地使用本揭露作為一基礎來設計或修改用於實施本文所引入之實施例或實例之相同目的及/或達成其相同優點之其他製程及結構。熟習此項技術者亦應認識到，此等等效構造並不背離本揭露之精神及範疇，且其可在不背離本揭露之精神及範疇之情況下做出各種改變、替代及變更。
202:基材
204:通道結構
208:分隔結構
212、214:薄型鈍化結構
216:閘極介電層
220:閘極堆疊
222:閘極電極層
226:間隔
230:源極/汲極接點
232、234:側面接點
236:表面接點
300:半導體元件

Claims (10)

  1. 一種半導體元件製造方法，包含：沉積一二維材料於一基材上方以形成一通道結構；形成具有一第一厚度之一鈍化結構於該通道結構上方；形成複數個分隔結構以定義複數個元件區；藉由使用一原子層蝕刻(atomic layer etch,ALE)程序，自每一該些元件區內之該鈍化結構移除一預定數量之層，以形成複數個薄型鈍化結構；形成一閘極堆疊於每一該些薄型鈍化結構上方；以及形成複數個源極/汲極接點於該些元件區中，該些源極/汲極接點具有與該通道結構接觸之複數個側面接點。
  2. 如請求項1所述之方法，更包含在使用該原子層蝕刻製程之前以及在該些分隔結構形成之後，移除該鈍化結構的受損層。
  3. 如請求項1所述之方法，其中該二維材料包含一半導體二維材料，該半導體二維材料包括黑磷，該鈍化結構包含一二維絕緣材料，該二維絕緣材料包括氮化硼。
  4. 如請求項1所述之方法，更包含移除部分的分隔結構與部分的薄型鈍化結構，以允許該些源極/汲極接點具有與該通道結構及該些薄型鈍化結構接觸的該些側面接點。
  5. 如請求項1所述之方法，其中形成該閘極堆疊包含在各該薄型鈍化結構上方形成高k值氧化物。
  6. 一種製造半導體元件的方法，包含：於一基材上方形成一通道結構；於該通道結構上方形成一界面結構；形成穿過該基材的多個分隔結構，以定義出多個元件區；移除該界面結構的受損層；通過一原子層蝕刻製程，自各該元件區的該界面結構中移除一預定數量的層，以形成多個分隔薄型界面結構；形成一閘極堆疊於各該分隔薄型界面結構上方；通過移除部分的該些分隔結構以及該些分隔薄型界面結構，形成多個源極/汲極接點於該些元件區內，並使該些源極/汲極接點具有與該通道結構及該些分隔薄型界面結構接觸的側面接點。
  7. 如請求項6所述之方法，其中移除該界面結構的受損層是執行於形成該些分隔區之後。
  8. 如請求項6所述之方法，更包含通過一原子層沉積製程形成該通道結構與該界面結構。
  9. 如請求項6所述之方法，其中該界面結構包 含一二維絕緣材料，該二維絕緣材料包括氧化鋁或六方氮化硼。
  10. 一種半導體元件，包含：一場效電晶體元件，包含：一基材；由一二維材料形成的一通道結構；形成於該通道結構上的一界面層；形成於該界面層上方的一閘極堆疊，該閘極堆疊包含一閘極電極層與一閘極介電層；以及多個源極/汲極接點形成於該界面層的多個開口上方，其中該界面層連續且完全地覆蓋該通道結構，該通道結構在該些源極/汲極接點之間延伸，該些源極/汲極接點接觸該界面層的側面，以及該些源極/汲極接點接觸該通道結構的側面以及頂面。
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