CN106558500B - 包含鳍式结构的半导体装置及其制造方法 - Google Patents
包含鳍式结构的半导体装置及其制造方法 Download PDFInfo
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- Thin Film Transistor (AREA)
Abstract
本发明是关于包含鳍式结构的半导体装置及其制造方法。根据一实施例的用于制造半导体装置的方法包含在衬底上方形成鳍式结构。所述鳍式结构具有顶表面及侧表面,并且所述顶表面定位于从所述衬底测量的高度H0处。在所述鳍式结构及所述衬底上方形成绝缘层。在第一凹陷中,使所述绝缘层凹陷到从所述衬底起的高度T1,使得所述鳍式结构的上部部分从所述绝缘层暴露。在所述已暴露上部部分上方形成半导体层。在形成所述半导体层之后,在第二凹陷中,使所述绝缘层凹陷到从所述衬底起的高度T2,使得所述鳍式结构的中间部分从所述绝缘层暴露。在所述鳍式结构的具有所述半导体层的所述上部部分以及所述已暴露中间部分上方形成栅极结构。
Description
技术领域
本发明是有关于半导体集成电路,并且更明确地说是有关于具有鳍式结构的半导体装置及其制造过程。
背景技术
由于半导体工业已发展到追求更高装置密度、更高性能及更低成本的纳米技术过程节点,因此来自制造及设计问题两方面的挑战已导致三维设计(例如鳍式场效应晶体管(鳍式FET))的开发。鳍式FET装置通常包含具有高纵横比且其中形成有半导体晶体管的沟道及源极/漏极区的半导体鳍状物。栅极在鳍式装置的侧面上方并且沿着鳍式装置的侧面形成(例如,缠绕),从而利用沟道及源极/漏极区的增加的表面积的优点产生更快、更可靠且更好控制的半导体晶体管装置。在鳍式FET装置中,鳍式结构的上部部分充当沟道,同时鳍式结构的下部部分充当阱。
发明内容
本发明提供一种用于制造半导体装置的方法,其包括:
在衬底上方形成鳍式结构,所述鳍式结构具有顶表面及侧表面,所述顶表面定位于从所述衬底测量的高度H0处;
在所述鳍式结构及所述衬底上方形成绝缘层;
使所述绝缘层第一凹陷到从所述衬底测量的高度T1,使得所述鳍式结构的上部部分从所述绝缘层暴露;
在所述鳍式结构的所述已暴露上部部分上方形成半导体层;
在形成所述半导体层之后,使所述绝缘层第二凹陷到从所述衬底测量的高度T2,使得所述鳍式结构的中间部分从所述绝缘层暴露;以及
在所述鳍式结构的具有所述半导体层的所述上部部分以及所述已暴露中间部分上方形成栅极结构。
附图说明
将从结合附图阅读的以下详细描述最佳地理解本发明。应强调的,根据工业中的标准操作,各种特征未按比例绘制并且仅用于说明目的。事实上,为了讨论清楚起见,各种特征的尺寸可任意地增加或减小。
图1到6展示说明根据本发明的一个实施例的用于制造鳍式FET装置的顺序过程的示例性横截面图。
图7到9展示说明根据本发明的另一实施例的用于制造鳍式FET装置的顺序过程的示例性横截面图。
图10到12为根据本发明的各种实施例的鳍式FET装置的示例性横截面图。
具体实施方式
将理解,以下揭示内容提供用于实施本发明的不同特征的许多不同实施例或实例。组件及布置的具体实施例或实例在下文进行描述以简化本发明。当然,这些仅为实例并且不欲为限制性的。举例来说,元件的尺寸不限于所揭示范围或值,而可能取决于装置的过程条件及/或所要性质。此外,以下描述中的第一特征形成于第二特征上方或上可能包含第一特征及第二特征以直接接触方式形成的实施例,并且也可能包含额外特征以插入第一特征及第二特征的方式形成,以使得第一特征及第二特征可不直接接触的实施例。为简单及清楚起见,各种特征可以不同比例任意地绘制。
此外,为了使描述容易,空间相关术语(例如,“在……之下”、“在……以下”、“低于”、“……以上”、“上部”及类似术语)可用于本文中以描述如图式中所说明的一个元件或特征与另一元件或特征的关系。所述空间相关术语意欲涵盖除图式中所描绘的定向之外的使用中或操作中装置的不同定向。设备可另外定向(旋转90度或处于其它定向)并且本文中所使用的空间相关描述词可同样地加以相应地解释。另外,术语“由……制成”可意谓“包括”或“由……组成”。
图1到6展示说明根据本发明的一个实施例的用于制造鳍式FET装置的顺序过程的示例性横截面图。应理解,对于所述方法的额外实施例,额外操作可在图1到6所示的过程之前、期间或之后提供,并且下文所描述的操作中的一些可被替换或消除。所述操作/过程的次序可互换。
如图1中所示,通过(例如)热氧化过程及/或化学气相沉积(CVD)过程在衬底10上方形成遮罩层100。在一个实施例中,衬底10为(例如)杂质浓度在约5×1014cm-3与约5×1015cm-3的范围中的p型硅衬底。在其它实施例中,衬底10为杂质浓度在约5×1014cm-3与约5×1015cm-3的范围中的n型硅衬底。替代地,衬底10可包括:另一基本半导体,例如锗;化合物半导体,包含IV-IV化合物半导体(例如SiC及SiGe)、UI-V化合物半导体(例如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP);或其组合。在一个实施例中,衬底10为SOI(绝缘体上硅)衬底的硅层。当使用SOI衬底时,鳍式结构可从SOI衬底的硅层突出或可从SOI衬底的绝缘体层突出。在后一情况下,SOI衬底的硅层用以形成鳍式结构。非晶衬底(例如非晶Si或非晶SiC)或绝缘材料(例如氧化硅)也可用作为衬底10。衬底10可包含已合适地掺杂有杂质(例如,p型或n型传导性)的各种区。
在一些实施例中,遮罩层100包含(例如)衬垫氧化物(例如,氧化硅)层105及氮化硅遮罩层110。衬垫氧化物层105可通过使用热氧化或CVD过程而形成。氮化硅遮罩层110可通过例如溅射方法的物理气相沉积(PVD)、CVD、等离子增强型化学气相沉积(PECVD)、大气压力化学气相沉积(APCVD)、低压CVD(LPCVD)、高度等离子CVD(HDPCVD)、原子层沉积(ALD)及/或其它过程而形成。
在一些实施例中,衬垫氧化物层105的厚度在约2nm到约15nm的范围中,并且氮化硅遮罩层110的厚度在约2nm到约50nm的范围中。在遮罩层100上方另外形成遮罩图案120。遮罩图案120为(例如)通过光刻法形成的光阻图案。
通过使用遮罩图案120作为蚀刻遮罩,形成衬垫氧化物层105及氮化硅遮罩层100的硬式遮罩图案。在一些实施例中,硬式遮罩图案的宽度在约5nm到约20nm的范围中。在特定实施例中,硬式遮罩图案的宽度在约7nm到约12nm的范围中。
如图2中所示,通过使用硬式遮罩图案作为蚀刻遮罩,通过使用干式蚀刻方法及/或湿式蚀刻方法的沟槽蚀刻将衬底10图案化成鳍式结构20。鳍式结构20的高度H0在约100nm到约300nm的范围中。在特定实施例中,高度H0在约50nm到约100nm的范围中。当所述鳍式结构的高度不均匀时,从衬底起的高度H0可从对应于所述鳍式结构的平均高度的平面测量。
在图2中,三个鳍式结构20安置于衬底10上方且在X方向上延伸且在Y方向上布置。然而,鳍式结构的数目不限于三个。所述数目可小至一个,或为四个或四个以上。另外,一或多个假鳍式结构可相邻鳍式结构20的两侧安置以改进图案化过程中的图案保真。在一些实施例中,多个鳍式结构的间距为恒定的。
在这个实施例中,块体硅片被用作为起始材料且构成衬底10。然而,在一些实施例中,其它类型的衬底被用作为衬底10。举例来说,绝缘体上硅(SOI)晶片可被用作为起始材料,并且SOI晶片的绝缘体层构成衬底10,并且SOI晶片的硅层用于鳍式结构20。
在图2中,高度H1对应于所述鳍式FET的所述沟道区从所述鳍式结构的顶部测量的高度。如下文所描述,高度H1为所述鳍式结构的顶部到所述隔离绝缘层的表面之间的距离,沿着垂直(Z)方向。H1也可由H0-T2定义,其中T2为所述隔离绝缘层的表面的高度(水平)。高度H2为从所述鳍式结构的顶部起的高度H1的约50%,并且高度H3为从所述鳍式结构的顶部起的高度H1的约25%。当所述隔离绝缘层的表面不平坦时,高度H1是由隔离绝缘层30的表面的平均高度定义。在其它实施例中,H2可为H1的约40%到60%,并且H3可为H1的约20%到30%。
在形成鳍式结构之后,鳍式结构在高度H1处的宽度W1在一些实施例中在约10nm到20nm的范围中,或在其它实施例中在约12nm到约18nm的范围中。鳍式结构在高度H2处的宽度W2在一些实施例中在约9nm到18nm的范围中,或在其它实施例中在约10nm到约16nm的范围中。鳍式结构在高度H3处的宽度W3在一些实施例中在约8nm到16nm的范围中,或在其它实施例中在约9nm到约15nm的范围中。鳍式结构在靠近鳍式结构的顶部处的宽度W4在一些实施例中在约6nm到15nm的范围中,或在其它实施例中在约8nm到约14nm的范围中。
如图3中所示,在衬底10及鳍式结构20上方形成隔离绝缘层30(或所谓的“浅沟槽隔离(STI)”层)。在衬底10上方形成绝缘(或介电)材料的毯覆层,使得鳍式结构20完全嵌入于所述毯覆绝缘层中,并且接着执行平面化操作(例如,化学机械抛光(CMP)过程或回蚀过程)以便暴露鳍式结构的顶表面。在平面化操作期间,移除硬式遮罩图案。
隔离绝缘层30由(例如)通过LPCVD(低压化学气相沉积)、等离子CVD或可流动CVD形成的二氧化硅制成。在可流动CVD中,沉积可流动介电材料而非氧化硅。可流动介电材料如其名称所暗示能够在沉积期间“流动”以填充具有高纵横比的间隙或空间。通常,各种化学物品被添加到含硅前体以允许沉积膜流动。在一些实施例中,添加氮氢键。可流动介电质前体、明确地说可流动氧化硅前体的实例包含硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢聚硅氮烷(PSZ)、正硅酸四乙酯(TEOS),或例如三甲硅烷基胺(TSA)的甲硅烷基胺。这些可流动氧化硅材料是在多操作过程中形成。在沉积可流动膜之后,所述膜固化且接着经退火以移除非所要元素以形成氧化硅。当非所要元素经移除时,可流动膜变得致密且收缩。在一些实施例中,进行多个退火过程。隔离绝缘层30可通过使用SOG而形成。在一些实施例中,SiO、SiON、SiOCN或氟掺杂硅酸盐玻璃(FSG)可用作为隔离绝缘层30。在形成隔离绝缘层30之后,可执行例如退火过程的热过程以改进隔离绝缘层30的质量。
接下来,如图4中所示,隔离绝缘层30的厚度通过(例如)回蚀过程而减小到高度H2或从衬底测量的高度T1。所述回蚀过程可通过使用NF3及NH3气体的远端等离子蚀刻来执行。通过调整蚀刻时间,能够获得隔离绝缘层130的所要厚度。通过减小隔离绝缘层30的厚度,鳍式结构的上部部分(沟道区的约50%)暴露。
在隔离绝缘层30的形成及凹陷隔离绝缘层30期间,鳍式结构20稍微失去其宽度。举例来说,在隔离绝缘层30凹陷之后,鳍式结构在高度H1处的宽度W1在一些实施例中在约8nm到18nm的范围中,或在其它实施例中在约10nm到约16nm的范围中。鳍式结构在高度H2处的宽度W2在一些实施例中在约7nm到16nm的范围中,或在其它实施例中在约8nm到约14nm的范围中。鳍式结构在高度H3处的宽度W3在一些实施例中在约5nm到13nm的范围中,或在其它实施例中在约6nm到约12nm的范围中。鳍式结构在靠近鳍式结构的顶部处的宽度W4在一些实施例中在约4nm到12nm的范围中,或在其它实施例中在约5nm到约10nm的范围中。
接着,如图5中所示,在鳍式结构20的已暴露上部部分上方形成磊晶层40。在一个实施例中,在所述已暴露上部部分上方形成Si磊晶层40,所述Si磊晶层的厚度在约0.5nm到约2nm的范围中。在其它实施例中,所述Si磊晶层的厚度在约0.8nm到约1.2nm的范围中。
Si磊晶层40可使用SiH4、Si2H6及/或SiH2Cl2作为源气体通过CVD、ALD或MBE(分子束磊晶)形成。磊晶层40掺杂有例如C、B、P或As的适当掺杂剂,或在其它实施例中为本征的。在一些实施例中,鳍式结构20的上部部分由Ge或SiGe制成。在其它实施例中,磊晶层40包含Ge或SiGe。
如图6中所示,隔离绝缘层30的厚度进一步减小到高度H1。如图6中所示,鳍式结构的上部部分的横截面大体上为卵形,并且鳍式结构的整个横截面形状类似于“保龄球瓶(bowling pin)”。隔离绝缘层的上表面以上的鳍式结构将变为鳍式FET的沟道区50,鳍式结构沿着Y方向的宽度如下所述地变化。在隔离绝缘层的上表面附近的水平处(实质上处于高度H1),鳍式结构具有宽度W1。鳍式结构的宽度随着与隔离绝缘层的上表面的距离增加(向上方向)而减小,并且在从具有磊晶层40的鳍式结构20的顶部测量的水平(或高度)H4处具有最小宽度W5。接着,随着与隔离绝缘层的上表面的距离朝着鳍式结构的顶部进一步增加,宽度在从具有磊晶层40的鳍式结构20的顶部测量的水平H5处变为最大值W6。在一个实施例中,W5<W1≤W6,并且在其它实施例中,W5<W6≤W1,并且在这一情况下,W6为H4以上的局部最大值。在一些实施例中,W6/W5在约1.1到约1.5的范围中且在其它实施例中在约1.15到1.3的范围中。
在一些实施例中,在第一凹陷之后从衬底到绝缘层的表面测量的高度T1在如下范围中:在第二凹陷之后从衬底到绝缘层的表面测量的高度T2加上鳍式结构的顶表面的高度H0与第二凹陷之后的绝缘层的高度T2之间的差的40%到60%。换句话说,T1在T2加上(H0-T2)的40%到60%的范围中。在特定实施例中,T1在T2加上(H0-T2)的70%到80%的范围中。
水平H4在一些实施例中定位于从沟道区的顶部起的总沟道高度Hc的约20%到约60%处,并且在其它实施例中定位于从顶部起的Hc的约25%到50%处。水平H5在一些实施例中定位于从沟道区的顶部起的总沟道高度Hc的约5%到约50%处,并且在其它实施例中定位于从顶部起的Hc的约10%到40%处。Hc也可由Ht-T2定义,其中T2为剩余隔离绝缘层的表面的高度(水平)且Ht为鳍式结构从衬底起的总高度。
鳍式结构在隔离绝缘层经第二次凹陷之后的高度H1处的宽度W1在一些实施例中在约8nm到18nm的范围中,或在其它实施例中在约10nm到约16nm的范围中。鳍式结构在水平H4处的最小宽度W5在一些实施例中在约6nm到14nm的范围中,或在其它实施例中在约8nm到约12nm的范围中。鳍式结构的宽度W6在一些实施例中在约7nm到18nm的范围中,或在其它实施例中在约8nm到约14nm的范围中。
图7到9展示说明根据本发明的另一实施例的用于制造鳍式FET装置的顺序过程的示例性横截面图。相同或相似于图1到6的结构、材料、配置、操作以及过程的结构、材料、配置、操作以及过程可适用于这一实施例,并且详细解释可省略。
尽管在图4中,隔离绝缘层30凹陷到高度H2,但在图7中,隔离绝缘层30凹陷到高度H3,以便暴露鳍式结构20的上部部分。
在使隔离绝缘层30凹陷之后,鳍式结构在高度H1处的宽度W1在一些实施例中在约8nm到18nm的范围中,或在其它实施例中在约10nm到约16nm的范围中。鳍式结构在高度H2处的宽度W2在一些实施例中在约6nm到17nm的范围中,或在其它实施例中在约9nm到约15nm的范围中。鳍式结构在高度H3处的宽度W3在一些实施例中在约5nm到13nm的范围中,或在其它实施例中在约6nm到约12nm的范围中。鳍式结构在靠近鳍式结构的顶部处的宽度W4在一些实施例中在约4nm到12nm的范围中,或在其它实施例中在约5nm到约10nm的范围中。
类似于图5,在鳍式结构20的已暴露上部部分上方形成磊晶层40,如图8中所示。
接着,类似于图6,隔离绝缘层30的厚度进一步减小到高度H1,如图9中所示。鳍式结构的上部部分的横截面大体上为卵形,并且鳍式结构的整个横截面形状类似于“保龄球瓶”。类似于图6,隔离绝缘层的上表面以上的鳍式结构将变成鳍式FET的沟道区50,鳍式结构沿着Y方向的宽度变化,具有高度H1处的宽度W1、水平(或高度)H4'处的最小宽度W5'及水平H5'处的最大值W6',如图9中所示。在一个实施例中,W5'<W1<W6',并且在其它实施例中,W5'<W6'<W1,并且在这一情况下,W6'为H4'以上的局部最大值。在一些实施例中,W6'/W5'在约1.1到约1.5的范围中并且在其它实施例中在约1.15到1.3的范围中。
水平H4'在一些实施例中定位于从沟道区的顶部起的总沟道高度Hc'的约10%到约40%处,并且在其它实施例中定位于从顶部起的Hc'的约15%到30%处。水平H5'在一些实施例中定位于从沟道区的顶部起的总沟道高度Hc'的约5%到约30%处,并且在其它实施例中定位于从顶部起的Hc'的约10%到20%处。
在隔离绝缘层第二次凹陷之后,鳍式结构在高度H1处的宽度W1在一些实施例中在约8nm到18nm的范围中,或在其它实施例中在约10nm到约16nm的范围中。鳍式结构在水平H4'处的最小宽度W5'在一些实施例中在约5nm到13nm的范围中,或在其它实施例中在约7nm到约11nm的范围中。鳍式结构的宽度W6'在一些实施例中在约7nm到17nm的范围中,或在其它实施例中在约8nm到约13nm的范围中。
在于图6或9中暴露沟道区50之后,在鳍式结构20上方形成栅极结构。图10到12为在形成栅极结构200之后根据本发明的各种实施例的鳍式FET装置的示例性横截面图。
栅极结构200可通过“先栅极(gate-first)”过程或“后栅极(gate-last)”(或替换栅极)过程形成。图10到12展示“后栅极”过程的情况。
在后栅极过程中,在沟道区上方形成包含假栅极介电层及假栅极电极层的假栅极结构,并且接着使未被假栅极结构覆盖的栅极结构凹陷到隔离绝缘层以下。接着,在凹陷部分中形成源极及漏极结构(未图示)以在隔离绝缘层上方延伸。在假栅极结构及源极漏极结构上方形成作为层间介电(ILD)层(未图示)的介电层。在对ILD层的平面化操作之后,移除假栅极结构以形成栅极空间,在所述栅极空间中,鳍式结构的沟道区暴露。接着,在已暴露沟道区上形成界面层210,并且在界面层210(及隔离绝缘层30)上方形成栅极介电层220。此外,在栅极介电层220上方形成功函数调整层230,且接着在功函数调整层230上方形成栅极电极层240(参见图10)。
界面层210包含由(例如)氧化硅制成的厚度为约1nm到3nm的薄绝缘层。所述界面层可省略。
栅极介电层220可包含以下各者的一或多个层:氧化硅、氮化硅、氮氧化硅或高k介电材料。高k介电材料包括金属氧化物。用于高k介电质的金属氧化物的实例包含以下各者的氧化物:Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu及/或其混合物。在一些实施例中,使用以下各者的一或多个层作为高k介电材料:HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-矾土(HfO2-Al2O3)合金。栅极介电层220的厚度在约1nm到7nm的范围中。
功函数调整层230包含以下各者的一或多个层:TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC。对于n沟道鳍式FET,TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi的一或多个层可用作功函数调整层,并且对于p沟道鳍式FET,TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co的一或多个层被用作功函数调整层。功函数调整层可通过ALD、PVD、CVD、电子束蒸发、电镀或其它合适过程形成。此外,功函数调整层可针对可使用不同金属层的n沟道鳍式FET及p沟道鳍式FET单独形成。功函数调整层可省略。
栅极电极层240包含例如以下各者的导电材料的一或多个层:多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAIN、TaCN、TaC、TaSiN、金属合金、其它合适材料及/或其组合。栅极电极层240可通过ALD、PVD、CVD、电子束蒸发、电镀或其它合适过程形成。
功函数调整层230的厚度可改变。图10展示其中功函数调整层230的厚度相对小的实施例。在一些实施例中,功函数调整层230的厚度在约5nm到约10nm的范围中。在图10中,相邻鳍式结构20的间距PI相对大,例如在约3×W6(或W6')到约6×W6(或W6')的范围中。在这一情况下,功函数调整层230能够保形地形成于沟道区50上方,并且栅极电极层240能够填充相邻沟道区之间的空间。在图10中,由于功函数调整层230能够保形地形成于沟道区50上方,因此底部栅极电极层240定位于水平H4(或H4')以下。
图11及12展示功函数调整层230的厚度变得更厚及/或间距PI变得更小的情况。
在图11及12中,功函数调整层230的厚度在约4nm到约25nm的范围中,并且相邻鳍式结构20的间距PI在约2×W6(或W6')到约4×W6(或W6')的范围中。在这一情况下,功函数调整层230形成垂悬物(overhang)并且可形成相邻沟道区之间的空隙250,如图11中所示。在特定实施例中,间距PI从约20nm变到约50nm。在其它实施例中,功函数调整层230完全填充相邻沟道区之间的空间,并且功函数调整层230的侧面合并在一起,如图12中所示。在图11及12中,由于相邻沟道区之间的空间经功函数调整层230填充,因此底部栅极电极层240定位于水平H4(或H4')以上。
本文中所描述的各种实施例或实例提供相对于现有技术的若干优点。举例来说,在本发明中,由于鳍式结构中的沟道区的上部部分具有卵形或保龄球瓶形状,因此有效沟道面积能够减小,并且FET性能可得到改进。此外,沟道区的圆角形状也能够防止可能在锐角转角处发生的电场集中。
将了解,并非全部优点已必定在本文中讨论,没有特定优点是所有实施例或实例所需要的,并且其它实施例或实例可提供不同优点。
根据本发明的一个方面,一种用于制造半导体装置的方法包含在衬底上方形成鳍式结构。所述鳍式结构具有顶表面及侧表面,并且所述顶表面定位于从所述衬底测量的高度H0处。在所述鳍式结构及所述衬底上方形成绝缘层。在第一凹陷中,使所述绝缘层凹陷到从所述衬底测量的高度T1,使得所述鳍式结构的上部部分从所述绝缘层暴露。在所述鳍式结构的所述已暴露上部部分上方形成半导体层。在形成所述半导体层之后,在第二凹陷中,使所述绝缘层凹陷到从所述衬底测量的高度T2,使得所述鳍式结构的中间部分从所述绝缘层暴露。在所述鳍式结构的具有所述半导体层的所述上部部分以及所述已暴露中间部分上方形成栅极结构。
根据本发明的另一方面,一种半导体装置包含鳍式场效应晶体管(鳍式FET)。所述鳍式FET包括安置于衬底上方的鳍式结构、隔离绝缘层以及栅极结构。所述鳍式结构包含所述鳍式FET的沟道区。所述隔离绝缘层安置于所述衬底上方且覆盖所述鳍式结构的下部部分。所述鳍式FET的所述沟道区从所述隔离绝缘层突出。所述栅极结构安置于所述沟道区上方。所述沟道区具有所述隔离绝缘层的表面水平处的第一宽度W1、所述表面水平以上的第一水平处的最小宽度W5以及所述第一水平以上的第二水平处的所述第一水平以上的所述沟道区的最大宽度W6。
根据本发明的另一方面,一种半导体装置包含鳍式场效应晶体管(鳍式FET)。所述鳍式FET包括至少两个鳍式结构、隔离绝缘层以及栅极结构。所述鳍式结构安置于衬底上方,并且所述鳍式结构分别包含所述鳍式FET的沟道区。隔离绝缘层安置于所述衬底上方并且覆盖所述鳍式结构的下部部分。所述鳍式FET的沟道区从隔离绝缘层突出。所述栅极结构安置于所述沟道区上方。与隔离绝缘层的上表面的距离在向上方向上增加,所述沟道区的宽度减小,在第一水平处达到最小宽度,接着增加并且达到最大宽度(其为所述第一水平以上的最大宽度)。所述栅极结构包含安置于所述沟道区上方的栅极介电层、安置于所述栅极介电层上方的功函数调整层以及安置于所述功函数调整层的栅极电极层。所述沟道区之间的栅极电极层的下部部分定位于所述第一水平以上。
前述内容概述若干实施例或实例的特征,使得所属领域的技术人员可更好地理解本发明的方面。所属领域的技术人员应了解,所述技术人员可容易地使用本发明作为用于设计或修改用于实现本文中所引入的实施例或实例的相同目的及/或达成相同优点的其它过程及结构的基础。所属领域的技术人员也应认识到,这些等效构造不脱离本发明的精神及范围,并且所述技术人员可进行其中的各种变化、替代及更改而不脱离本发明的精神及范围。普通新申請案若缺少小標題下的內容,仍應保留上面的小標題,但務必通知本所。
Claims (17)
1.一种用于制造半导体装置的方法,其包括:
在衬底上方形成复数鳍式结构,所述复数鳍式结构具有顶表面及侧表面,所述顶表面定位于从所述衬底测量的高度H0处;
在所述复数鳍式结构及所述衬底上方形成绝缘层;
使所述绝缘层第一凹陷到从所述衬底测量的高度T1,使得所述复数鳍式结构的上部部分从所述绝缘层暴露;
在所述复数鳍式结构的已暴露的所述上部部分上方形成半导体层;
在形成所述半导体层之后,使所述绝缘层第二凹陷到从所述衬底测量的高度T2,使得所述复数鳍式结构的中间部分从所述绝缘层暴露;
在所述复数鳍式结构的具有所述半导体层的所述上部部分以及已暴露的所述中间部分上方形成栅极介电层;以及
在所述栅极介电层上方保形地形成功函数调整层,使在相邻的所述复数鳍式结构之间的空间,所述功函数调整层的侧面合并在一起。
2.根据权利要求1所述的方法,其中T1在T2加上(H0-T2)的40%到60%的范围中。
3.根据权利要求1所述的方法,其中T1在T2加上(H0-T2)的70%到80%的范围中。
4.根据权利要求2所述的方法,其中所述半导体层的厚度在0.5nm到2nm的范围中。
5.根据权利要求3所述的方法,其中所述半导体层的厚度在0.5nm到2nm的范围中。
6.根据权利要求2所述的方法,其中:
所述复数鳍式结构的具有所述半导体层的所述上部部分以及已暴露的所述中间部分构成沟道区,
所述沟道区具有在所述绝缘层在所述第二凹陷之后的表面水平以上的第一水平处的最小宽度,以及在所述第一水平以上的第二水平处的所述第一水平以上的最大宽度。
7.根据权利要求6所述的方法,其中所述第一水平定位于比所述沟道区的顶部低所述沟道区的高度的20%到60%处,所述沟道区的高度是从所述表面水平开始测量。
8.根据权利要求3所述的方法,其中:
所述复数鳍式结构的具有所述半导体层的所述上部部分以及已暴露的所述中间部分构成沟道区,
所述沟道区具有在所述绝缘层在所述第二凹陷之后的表面水平以上的第一水平处的最小宽度,以及在所述第一水平以上的第二水平处的所述第一水平以上的最大宽度。
9.根据权利要求8所述的方法,其中所述第一水平定位于比所述沟道区的顶部低所述沟道区的高度的10%到40%处,所述沟道区的高度是从所述表面水平开始测量。
10.一种包含鳍式场效应晶体管鳍式FET的半导体装置,所述鳍式FET包括:
安置于衬底上方的复数鳍式结构,所述复数鳍式结构包含所述鳍式FET的沟道区;
安置于所述衬底上方且覆盖所述鳍式结构的下部部分的隔离绝缘层,所述鳍式FET的所述沟道区从所述隔离绝缘层突出;
安置于所述沟道区上方的栅极结构,所述栅极结构包含功函数调整层,其中:
所述沟道区具有所述隔离绝缘层的表面水平处的第一宽度W1、所述表面水平以上的第一水平处的最小宽度W5以及所述第一水平以上的第二水平处的所述第一水平以上的所述沟道区的最大宽度W6;
在相邻的所述复数鳍式结构之间的空间,所述功函数调整层的侧面合并在一起。
11.根据权利要求10所述的半导体装置,其中所述第一水平以上的所述沟道区的上部部分的横截面具有卵形形状。
12.根据权利要求10所述的半导体装置,其中所述沟道区的横截面具有保龄球瓶形状。
13.根据权利要求10所述的半导体装置,其中W5<W1<W6。
14.根据权利要求10所述的半导体装置,其中W6/W5在1.1到1.5的范围中。
15.根据权利要求10所述的半导体装置,其中所述第一水平定位于比所述沟道区的顶部低所述沟道区的高度的20%到60%处,所述沟道区的高度是从所述表面水平开始测量。
16.根据权利要求10所述的半导体装置,其中所述第一水平定位于比所述沟道区的顶部低所述沟道区的高度的10%到40%处,所述沟道区的高度是从所述表面水平开始测量。
17.一种包含鳍式场效应晶体鳍式FET的半导体装置,所述鳍式FET包括:
安置于衬底上方的至少两个鳍式结构,所述鳍式结构分别包含所述鳍式FET的沟道区;
安置于所述衬底上方且覆盖所述鳍式结构的下部部分的隔离绝缘层,所述鳍式FET的所述沟道区从所述隔离绝缘层突出;
安置于所述沟道区上方的栅极结构,其中:
随着与所述隔离绝缘层的上表面的距离在向上方向上增加,所述沟道区的宽度减小,在第一水平处达到最小宽度,然后增加且达到最大宽度,所述最大宽度为所述第一水平以上的最大宽度,
所述栅极结构包含安置于所述沟道区上方的栅极介电层、安置于所述栅极介电层上方的功函数调整层以及安置于所述功函数调整层上方的栅极电极层,
在所述沟道区之间的所述栅极电极层的最低部分定位于该第一水平以上,
所述功函数调整层完全填充所述沟道区之间的低于所述第一水平的空间。
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