CN108122733A - 半导体元件制造方法 - Google Patents

半导体元件制造方法 Download PDF

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Publication number
CN108122733A
CN108122733A CN201710386591.4A CN201710386591A CN108122733A CN 108122733 A CN108122733 A CN 108122733A CN 201710386591 A CN201710386591 A CN 201710386591A CN 108122733 A CN108122733 A CN 108122733A
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layer
slim
channel
passivating
channel design
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CN108122733B (zh
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叶凌彦
张智胜
蔡惠铭
林佑明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体元件制造方法。包括场效晶体管(field effect transistor,FET)元件的半导体元件，包括基材与由二维材料形成的通道结构。于通道结构上形成界面层。于界面层上方形成栅极堆叠，栅极堆叠包含栅极电极层与栅极介电层。于界面层中的开口的上方形成源极/漏极接点。源极/漏极接点具有与界面层接触的侧面接点以及与通道结构接触的侧面接点与表面接点。

Description

半导体元件制造方法
技术领域
此揭露是有关于一种半导体集成电路，且特别是有关于二维元件的原子层制造。
背景技术
随着晶体管制程技术的进步，晶体管的尺寸缩小并使集成电路中的晶体管密度因此增加。然而，关闭状态电流(off-state current)随晶体管的通道长度缩短而大幅增加，其成因如短通道效应(short channel effect)。对通道长度短于20纳米的晶体管来说，此效应为能否进一步提升晶体管密度的主要挑战。已知降低通道厚度为抑制短通道效应的方法之一。超薄通道晶体管(Ultra-thin body transistor,UBT)可采用超薄通道半导体材料(ultra-thin semiconductor channel material)来抑制短通道效应。二维半导体被预期来作为超薄通道晶体管中的通道材料。二维材料，诸如过渡金属二硫族化物(transitionmetal dichalcogenides,TMD)、石墨烯(graphene)与黑磷(black phosphorus)，皆被视为极具潜力可用于场效晶体管(field-effect transistor,FET)元件中晶体管通道的候选材料。传统场效晶体管元件的制造方法可能无法在原子级的精准度下控制层厚与界面组成，而此为未来纳米级电子元件制程世代的首要重点。
目前亟需能于栅极介电层与具有超薄型通道厚度的二维通道材料之间达成所欲的界面的解决方法，通道厚度可小于各栅极宽度的四分之一(如，20纳米)。
发明内容
依据本揭露的多个实施方式，一种半导体元件制造方法包含：沉积二维材料于基材上方以形成通道结构；形成具有第一厚度的钝化结构于该通道结构上方；形成分隔结构以定义元件区；通过使用原子层蚀刻(atomic layer etch,ALE)程序，自每一元件区内的钝化结构移除预定数量的层，以形成薄型钝化结构；形成栅极堆叠于每一薄型钝化结构上方；以及形成源极/漏极接点于元件区中，源极/漏极接点具有与通道结构接触的侧面接点。
附图说明
图1为绘示依据本揭露的一或多个实施方式的例示性流程图，用以描述二维半导体元件的原子层制造；
图2A至图2H为绘示依据本揭露的一或多个实施方式的例示性二维视图，用以描述于原子层制造不同阶段的二维半导体元件；
图3为绘示依据本揭露的一或多个实施方式的二维金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)元件的简化图，用以描述二维金氧半场效晶体管元件的结构细节。
具体实施方式
应理解，以下揭示内容提供用于实施本揭露的不同特征的诸多不同实施例或实例。下文描述组件及排列的特定实施例或实例以简化本揭露。当然，此等仅是示例性且并非意欲为限制性。举例而言，部件的尺寸不限于所揭示范围或值，而是可取决于元件的制程条件及/或所期望性质。此外，随后的描述中在第二特征上方或在第二特征上形成第一特征可包含其中第一特征及第二特征直接接触形成的实施例且亦可包含其中可插入第一特征及第二特征地形成额外特征以使得第一特征及第二特征可不直接接触的实施例。为简单且清晰起见，各特征可按不同比例而任意绘制。
进一步而言，为了便于描述，本文可使用诸如“下面”、“下方”、“下部”、“上方”、“上部”及类似者等空间相对性术语来描述如图中所图示的一个元件或特征与另一元件(或多个元件)或特征(或多个特征)的关系。除了图中所描绘的定向外，空间相对性术语意欲囊括使用或操作中的元件的不同定向。设备可经其他方式定向(旋转90度或处于其他定向)且因此可同样解读本文所使用的空间相对性描述词。另外，术语“由…制成”可意指“包括”或“由…组成”。
依据本揭露的一或多个实施方式，图1为例示性流程图100，用以描述二维半导体元件如金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)的原子层制造。流程图100仅仅说明整体制造程序的相应部分。应了解于可于图1所示作业之前、中及后加入额外作业，且于下文描述的一些作业可因本方法的额外实施方式而被替换或是删除。作业/程序的顺序可互相调换。
于图1的S101中，将二维材料形成于基材202上方以形成通道结构204，如图2A中的X轴切图200A所示。依据一些实施方式，举例而言，基材202可为p型硅基材，有介于约1×1015cm-3至约3×1015cm-3的杂质浓度。于其他实施方式中，基材202为n型硅基材，有介于约1×1015cm-3至约3×1015cm-3的杂质浓度。在一些实施方式中，硅基材晶向为(100)。
可选择的，基材可包含其他元素型半导体(elemental semiconductor)如锗，化合物半导体(compound semiconductor)，包括IV-IV族化合物半导体诸如SiC及SiGe，以及III-V族化合物半导体诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或以上的任意组合。在一或多个实施方式中，基材可为绝缘体上硅(silicon-on-insulator,SOI)基材的硅层。非晶基材诸如非晶硅或非晶碳化硅，或绝缘材料如氧化硅，亦可用来作为基材。基材可包括多种适当掺杂杂质(如，p型或n型导电性)的区域。
在一些实施方式中，于X轴切图200A中所示的通道结构204，是由二维材料所形成，且随后形成为场效晶体管的通道、延伸及源极/漏极区。二维材料通常仅为几层厚且以一种强键结层的形式存在，而层与层间仅具有微弱的凡得瓦力(Van der Waals force)，能藉机械或化学的方法将其剥离为单独、原子级薄度的层。二维材料为超薄通道晶体管的通道材料极具潜力的候选。二维材料的例子如石墨烯(graphene)、石墨炔(graphyne)、硼烯(borophene)、硅烯(silicene)、锗烯(germanene)、过渡金属二硫族化物(transitionmetal dichalcogenides,TMD)、黑磷及类似物。某些面向中，所揭露的二维通道可为包括TMD的二维半导体(如二硫化钼)、黑磷或石墨烯。在一些实施方式中二维半导体可包括一或多层，且其厚度可介于约0.5纳米至100纳米之间。仅几层的二维半导体的其中一项优势特征为其高电子迁移率(electron mobility,μe)，其值介于约50cm2/V-sec至1000cm2/V-sec之间或甚至更高。应了解，当把整块硅切至与一般二维材料薄膜同一量级的厚度(如，约2纳米)时，其迁移率会剧烈衰降。
应了解，广泛用于许多集成电路(integrated-circuit,IC)中MOSFET元件的栅极长度不断被缩小与降低，以增加集成电路中晶体管的封装密度与增快其执行速度。然而，大幅下降的栅极长度招致了不乐见的短通道效应，如变高的关闭状态逸漏电流。抑制短通道效应的方法之一为采用降低厚度的半导体通道，即为超薄通道晶体管(Ultra-thin bodytransistor,UBT transistor)。举例而言，要有效抑制栅极长度小于约20纳米的晶体管的短通道效应，其中一种方法即采用降低厚度(如，小于5纳米)的半导体通道。若一晶体管的半导体通道厚度小于其栅极长度的三分之一或四分之一，则该晶体管通常被称为超薄型通道晶体管。超薄通道晶体管可采用超薄型通道材料。
二维材料，为仅具几层原子的晶型材料，为极具潜力的超薄通道的候选材料。其中一种具有高迁移率的二维材料为黑磷。黑磷为层化材料而单一层的黑磷称为黑磷烯(phosphorene)。黑磷为半导体，其直接能隙(direct band gap)单一层时约1.5电子伏特，至五层时于布里昂区(Brillouin zone)的Γ点(center point of Brillouin zone)处的约为0.59电子伏特之间。
在一些实施方式中，可通过二维材料(如黑磷)与此处描述的原子层沉积(atomiclayer deposition,ALD)来形成通道结构204。沉积方法的描述仅为示例，且除非特别指明，并无意限制未讨论的事项。举一例而言，正交系(orthorhombic)黑磷可由红磷(redphosphorus)经由使用锡及/或锡碘化物作为添加物的短程化学转移反应(short-waytransport reaction)生长而成。在另一例中，黑磷可于约摄氏200度至250度的温度与约13,000,kg/cm2的高压下由白磷(white phosphorus)合成。二维材料的厚度可由沉积时间控制。在一实施方式中，一段期间所沉积出的多层(以单一层为例)黑磷烯的厚度约为0.53纳米。在一些实施方式中，厚度可介于1个单一层至20个单一层(如，厚度约10.6纳米)之间。如下所讨论，在一些实施方式中，不同区域(如通道区与源极/漏极区)的厚度可能有所变化。在一些实施方式中，主动区(active region)的厚度变化可具有连续性。在其他实施方式中，厚度介于约1个单一层至10个单一层(如，厚度约5.3纳米)之间。
图1的S102中，具有第一厚度t的钝化结构206形成于通道结构204上方，如图2B中的X轴切图200B所示。钝化结构206为界面层，用以促进栅极介电层与具有超薄通道厚度的二维通道材料层接合。已知方法大体上无法在原子级精准度下准确控制层厚与界面组成，而其对未来纳米电子元件技术世代而言相当关键。此外，如何在二维材料上形成高品质且具低有效氧化物厚度(effective oxide thickness,EOT)的栅极介电质亦为一大挑战。此肇因于此材料的二维特性，即缺乏成核点。因此，多数元件的制造若非使用较厚的氧化层，则无可避免得诱发悬浮键(dangling bond)以促进成核使氧化层生长。
此技术的钝化结构206可解决以上问题，并让介电层与通道结构204间得以具有所希望的无悬浮键界面。在一些实施方式中，钝化结构206可由原子层沉积或化学气相沉积程序沉积。在一些实施方式中，钝化结构206为二维绝缘材料，如六方氮化硼(hexagonalboron nitride,h-BN)。举例而言，当通道结构204使用二硫化钼时，钝化结构可为氮化硼。氮化硼为宽能隙的化合物，具有良好的物理特性与化学稳定度。六方氮化硼包含交错排列为蜂巢状的硼原子与氮原子，包含由sp2轨域键结的二维层。每一层的六方氮化硼具有强共价键所键结的硼原子与氮原子，而各层间则由弱凡得瓦力拉住，与石墨中的情况类似。因此，可藉微机械剥离(micromechanical cleavage)由整块氮化硼结晶拨下六方氮化硼薄膜，并将其作为介电层。亦可对氮化硼粒子进行超声波处理(ultrasonication)与高能电子束辐照(high-energy electron beam irradiation)来形成少数层的六方氮化硼。
在图1的S103中，如图2C中的X轴切图200C所示，形成分隔结构208以定义出多个元件区210。分隔结构208的形成为已知的程序。举例而言，分隔结构208可为浅凹槽分隔(shallow trench isolation,STI)结构。制造分隔结构208的步骤包含：于制程中的元件(例如，图2B中的200B)中蚀刻出凹槽样式；沉积一或更多介电层材料(如二氧化硅)以填充凹槽；以及通过化学机械平坦化(chemical-mechanical planarization,CMP)，移除多余的介电质。分隔结构208可包含一或多层通过低压化学气相沉积(low pressure chemicalvapor deposition,LPCVD)、等离子化学气相沉积(plasma-enhanced chemical vapordeposition)或可流动式化学气相沉积(flowable chemical vapor deposition)所沉积的绝缘材料，诸如氧化硅、氮氧化硅或氮化硅。于可流动式化学气相沉积中，沉积的材料为可流动式介电材料，而非氧化硅。可流动式介电材料，正如其名，可在沉积过程中流动，以填充高纵横比的间隙或空间。一般来说，会在含硅的前体(precursor)中加入多种化学物质以使沉积的膜得以流动。在一些实施方式中，加入氮氢键结。可流动式介电质前体，特别是可流动式氧化硅前体，举例而言包含silicate、siloxane、methyl silsesquioxane(MSQ)、hydrogen silsesquioxane(HSQ)、MSQ/HSQ、perhydrosilazane(TCPs)、perhydropolysilazane(PSZ)、tetraethyl orthosilicate(TEOS)或sily-amine(如trisilylamine,TSA)。这些可流动式氧化硅材料由多个作业程序形成。沉积完可流动式膜后，将其固化并退火以移除不需要的元素以形成氧化硅。当不需要的元素被移除时，可流动式膜收缩且密度变高。在一些实施方式中，执行多道退火程序。可流动式膜经过不只一次的固化与退火。可于可流动式膜中掺杂硼及/或磷化物。在一些实施方式中，分隔结构208由一或多层的自旋玻璃(spin on glass,SOG)、SiO2、SiON、SiOCN及/或掺氟硅玻璃(fluorine-doped silicate glass,FSG)所形成。
使用化学机械平坦化技术以移除多余介电质的步骤使分隔结构208的上表面与钝化结构206的上表面切齐。然而，形成分隔结构的过程中可能会伤害到钝化结构。可由原子层蚀刻(atomic layer etch,ALE)技术清除受损的钝化结构206。举例而言，如图2D中的X轴切图200D所示，由虚线标示出包含受损层的部分211，将该部分移除以形成具有厚度t1的干净钝化结构213。
回到图1中的流程图100，于S104中，从每个元件区210中的钝化结构206中移除预定数量的层，以形成薄型钝化结构(如，212与214)，如图2E中的X轴切图200E所示。第一厚度t已经因受损层的移除而降至厚度t1，然此厚度仍需进一步降低以达成各元件对钝化结构厚度的要求。此步骤的执行乃因为位于二维通道上的钝化层(如，二维介电界面)经常必须是超薄厚度，且一晶片的不同元件各有不同的所欲厚度。原子层蚀刻方法可移除任何不需要的残余物，并协助对元件结构进行图案化(pattern)/蚀刻以达到高效能。
举例而言，可通过原子层蚀刻程序在原子级的精准度下使钝化结构206变薄，使其厚度t1降低。因移除所形成的薄型钝化结构可达成多种多栅极氧化物(multi-gate oxide)应用的规范。举例而言，薄型钝化结构212与214可应用于两种不同的晶体管(如，核心(core)晶体管和输入/输出(I/O)晶体管)，两种晶体管具有不同的栅极氧化物厚度(如，介于约1-100层之间，每层约为0.5纳米)。薄型钝化结构212与214为栅极氧化物的一部分，栅极高k值介电质形成于这些钝化结构上，将如于此处的说明。
于图1的S105中，栅极堆叠220形成于每个薄型钝化结构212与214上方，如图2F中的X轴切图200F所示。在一些实施方式中，栅极堆叠200为已知的结构并包含栅极介电层、栅极电极层222以及间隔226，且栅极堆叠200形成于各个薄型钝化结构(如，212与214)上方。在一些实施方式中，栅极介电层包含高k值介电材料224以及薄型钝化结构212与214(如，界面层)。高k值介电材料224可包含金属氧化物。用于高k值介电材料224的金属氧化物，可包含各种金属的氧化物，举例而言，所述金属包含：Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu及/或以上的任意混和。在一些实施方式中，栅极介电层的厚度介于约0.5纳米至约10纳米之间。在另一实施方式中，栅极堆叠220包含栅极电极层222以及间隔226，且栅极堆叠220形成于各个薄型钝化结构(如，212与214)上方。在此实施方式之中，位于栅极电极下方的薄型钝化结构(212与214)作为栅极介电质，于其上方形成高k值介电质。
在一些实施方式中，栅极电极层222为多晶硅。在一些实施方式中，通过使用包含氮化硅层与氧化物层的硬遮罩(hard mask)来对多晶硅层进行图案化。于其他实施方式之中，栅极电极层222包含单层或多层的结构。进一步而言，栅极电极层222可为掺杂的多晶硅，其可为均匀掺杂或不均匀掺杂。在一些其他的实施方式中，栅极电极层222包含金属，诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi以及其他功函数与基材材料相容的导电材料，或以上的任意组合。用于栅极电极层222的电极层可由适当的程序形成，诸如原子层沉积、化学气相沉积、物理气相沉积、电镀或以上的任意组合。在一些实施方式中，栅极电极层222(沿X轴方向)的宽度介于约30纳米至约60纳米之间。
图1的S106中，源极/漏极接点230形成于元件区中，如图2G中的X轴切图200G所示。对分隔结构208与薄型钝化结构212及214进行图案化与蚀刻后，形成源极/漏极接点230，使得源极/漏极接点230具有与薄型钝化结构212及214接触的侧面接点以及与通道结构204接触的侧面接点及表面接点。此为本技术具优势的特征，此特征提供了晶体管的源极/漏极接点230更大的接触面积，而使接触电阻降低。
在一或更多个实施方式中，可用作源极/漏极接点230的范例材料包含Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi以及其他具有适当功函数的导电材料，或以上的任意组合。在一些实施方式中，源极/漏极接点230可由诸如原子层沉积、化学气相沉积、物理气相沉积或其他适当的沉积技术沉积而成。在一些实施方式中，可执行一选择性的退火程序，举例而言，可执行约介于250度至350度摄氏间的退火程序以改善金属至源极/漏极间的接触电阻。上述所提的程序概念可整合进现有的MOSFET制造程序，且可施行于多种技术节点，诸如但不限于10纳米、7纳米、5纳米的技术节点。
下一步骤，如图2H的X轴切图200H所示，为在栅极电极222以及源极/漏极接点230上方形成金属层240。金属层240的形成包含对金属层(如，铝、钨以及类似物)进行图案化与沉积，举例而言，通过已知的沉积程序，诸如化学气相沉积、原子层沉积、物理气相沉积或以上的任意组合。金属层240作为晶片上不同元件的连接层(interconnect)。
依据此揭露的一或多个实施方式，图3为阐释半导体元件300细部结构的简图。半导体元件300的一例包含场效晶体管元件，如MOSFET元件。半导体元件300包含基材202、通道结构204、薄型钝化结构212与214、栅极堆叠220以及源极/漏极接点230。通道结构204由二维材料形成，如前述所解释。晶体管的实际通道为一部分的通道结构204，其位于栅极堆叠220的下方。薄型钝化结构212与214如上述所讨论且由二维介电材料所形成。栅极堆叠220包含栅极电极层222，且栅极介电层216形成于薄型钝化结构层212与214上方以作为界面层。在一些实施方式中，栅极介电层216由位于薄型钝化结构212与214及栅极电极层222间的薄型钝化结构212与214所形成。在一些实施方式中，栅极介电层216可包含高k值介电质。源极/漏极接点230形成于栅极介电层216与分隔结构208的开口上方。
在一些实施方式中，源极/漏极接点230具有与栅极介电层216接触的侧面接点232以及与通道结构204接触的侧面接点234及表面接点236，如前述参照图2G中的描述。与通道结构204接触的表面接点236沿与侧面接点234垂直的第一方向(X轴方向)延伸。通道结构204包含二维半导体，诸如二硫化钼、黑磷以及石墨烯。于一实施方式中，界面层包含二维绝缘材料，诸如六方氮化硼。栅极堆叠包含高k值介电材料及上述所讨论的栅极电极。
应了解，此处并无必要讨论到所有优点，就所有实施方式及范例而言，并不必要具有特定的优点，且其他实施方式及范例可提供不同的优点。
依据本揭露的一面向，一种半导体元件的制造方法包含于基材上方形成二维材料以形成通道结构。于通道结构上方形成具有第一厚度的钝化结构。形成分隔结构以定义出多个元件区。通过原子层蚀刻程序自每个元件区中的钝化结构移除预定数量的层以形成多个薄型钝化结构。栅极堆叠形成于每个薄型钝化结构上方，且源极/漏极接点形成于元件区中。在一些实施方式中，源极/漏极接点具有与二维半导体材料及二维介电材料接触的侧面接点。
在一些实施方式中，半导体元件制造方法进一步包含在使用原子层蚀刻程序之前以及在分隔结构形成之后，移除钝化结构的受损层。
在一些实施方式中，二维材料包含半导体二维材料，其包括黑磷(blackphosphorus)，钝化结构包含二维绝缘材料，其包括氮化硼(boron nitride)。
在一些实施方式中，半导体元件制造方法进一步包含使用原子层沉积(atomiclayer deposition,ALD)程序形成通道结构与钝化结构，其中第一厚度介于约100层至约200层之间。
在一些实施方式中，二维材料包含二维半导体材料，其包括二氧化钼(Molybdenumdioxide,MoS2)，钝化结构包含二维绝缘材料，其包括氧化铝(alumina,Al2O3)。
在一些实施方式中，半导体元件制造方法进一步包含移除部分的隔离结构与部分的薄型钝化结构，以允许源极/漏极接点具有与通道结构及薄型钝化结构接触的侧面接点。
在一些实施方式中，二维材料包含二维半导体，其中二维半导体包含过渡金属二硫族化物(transition metal dichalcogenide,TMD)、黑磷或石墨烯(graphene)，过渡金属二硫族化物包括二硫化钼(MoS2)。
在一些实施方式中，半导体元件制造方法中的形成栅极堆叠包含在各个薄型钝化结构上方形成高k值氧化物。
在一些实施方式中，基材包含硅(Si)、二氧化硅(SiO2)、锗(Ge)或覆有介电材料的硅。每一薄型钝化结构具有不同的厚度，介于二维绝缘材料的约1层至约100层之间。
依据本揭露的另一面向，一种制造半导体的方法其特征在于包含于基材上方形成通道结构。于通道结构上方形成界面结构。形成穿过基材的分隔结构以定义出元件区。移除界面结构的受损层。通过原子层蚀刻程序，自各个元件区的界面结构中移除所欲的层数，以形成分隔薄型界面结构。栅极堆叠形成于每一薄型界面结构上方。通过移除部分的分隔结构以及分隔薄型界面结构，形成源极/漏极接点于元件区内，并使源极/漏极接点具有与通道结构及分隔薄型钝化结构接触的侧面接点。
在一些实施方式中，半导体元件制造方法中移除介面结构的受损层是执行于形成分隔区之后。
在一些实施方式中，半导体元件制造方法中的通道结构包含二维材料，其中二维材料包含半导体二维材料，其包括黑磷；以及界面结构包含二维绝缘材料，其包括氮化硼。
在一些实施方式中，半导体元件制造方法进一步包含通过原子层沉积程序形成通道结构与界面结构。
在一些实施方式中，二维材料包含二维半导体，且其中该二维半导体包含过渡金属二硫族化物、黑磷与石墨，过渡金属二硫族化物包括二硫化钼。
在一些实施方式中，界面结构包含二维绝缘材料，其包括氧化铝或六方氮化硼(hexagonal boron nitride)。
在一些实施方式中，半导体元件制造方法中的形成栅极堆叠包含在分隔薄型界面结构各自上方形成高k值氧化物。
依据本揭露的又一面向，半导体元件其特征在于包含场效晶体管元件，如MOSFET。场效晶体管元件包含基材以及由二维材料形成的通道结构。于通道结构上形成界面层。于界面层上方形成栅极堆叠，栅极堆叠包含栅极电极层与栅极介电层。源极/漏极接点形成于界面层的开口上方。源极/漏极接点具有与界面层接触的侧面接点以及与通道结构接触的侧面接点及表面接点。
在一些实施方式中，半导体元件中与通道结构接触的表面接点沿垂直于该侧面接点的第一方向延伸，且其中通道结构包含二维半导体，其包含过渡金属二硫族化物、黑磷与石墨，过渡金属二硫族化物包括二硫化钼。
在一些实施方式中，半导体元件中的界面层包含二维绝缘材料，二维绝缘材料包括氧化铝以及六方氮化硼中的至少一者，其中栅极堆叠包括高k值介电材料与栅极电极。
上文概述数个实施例或实例的特征以使熟悉此项技术者可较佳地理解本揭露的态样。熟悉此项技术者应了解，其可容易地使用本揭露作为一基础来设计或修改用于实施本文所引入的实施例或实例的相同目的及/或达成其相同优点的其他制程及结构。熟悉此项技术者亦应认识到，此等等效构造并不背离本揭露的精神及范畴，且其可在不背离本揭露的精神及范畴的情况下做出各种改变、替代及变更。

Claims (1)

1.一种半导体元件制造方法，其特征在于，包含：
沉积一二维材料于一基材上方以形成一通道结构；
形成具有一第一厚度的一钝化结构于该通道结构上方；
形成多个分隔结构以定义多个元件区；
通过使用一原子层蚀刻程序，自每一所述元件区内的该钝化结构移除一预定数量的层，以形成多个薄型钝化结构；
形成一栅极堆叠于每一所述薄型钝化结构上方；以及
形成多个源极/漏极接点于所述多个元件区中，所述多个源极/漏极接点具有与该通道结构接触的多个侧面接点。
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