TWI691046B - 微發光二極體顯示器組裝體 - Google Patents
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Abstract
本發明關於半導體結構，特別是關於微發光二極體顯示器組裝體及製造方法。結構包含一中介層以及複數個微發光二極體陣列，其中每一微發光二極體陣列包含將複數個微發光二極體陣列的畫素連接至中介層的複數個貫穿孔。
Description
本發明關於半導體結構，特別是關於微發光二極體顯示器組裝體及製造方法。
無機發光二極體(ILED)為由半導體材料製成的發光二極體。使用ILED有可能產生各種不同的顏色，包含紅、綠、黃及藍。操作上，當施加順向偏壓於半導體材料的P-N接面時，ILED會發光。
用於顯示器系統的LED裝置在大表面上需要高畫素放置密度。然而，傳統的LEDs製造方法要滿足產量要求是個挑戰，特別是針對較大的顯示器尺寸。再者，由於較差的晶圓面積利用率，下一代顯示器的成本將更高。關於後面這點，使用單一晶粒用於大型LED顯示器及影像感測器陣列將在部分場區域中的晶圓邊緣周圍留下大量未使用的空間。
在本發明的一態樣中，結構包含：一中介層；以及複數個微發光二極體陣列，其每一個包含將複數個微發光二極體陣列的畫素連接至中介層的複數個貫穿孔。
在本發明的一態樣中，結構包含：包含複數個貫穿孔的一中介層；複數個微發光二極體陣列，其每一個包含連接至複數個微發光二極體陣列的每一畫素的複數個貫穿孔；以及一後段製程佈線結構(back-end of the line wiring scheme)，其將每一畫素的貫穿孔連接至中介層的貫穿孔。
在本發明的一態樣中，方法包含：在一基板中形成連接至微發光二極體陣列的畫素的複數個貫穿孔；以及以與中介層的連接對齊的貫穿孔將複數個微發光二極體陣列中的每一個的畫素連接至一單一中介層。
10‧‧‧畫素
12‧‧‧電極
14a‧‧‧子畫素
14b‧‧‧子畫素
14c‧‧‧子畫素
14d‧‧‧子畫素
16‧‧‧奈米線
20‧‧‧微發光二極體組裝體
22‧‧‧基板
24‧‧‧貫穿矽通孔
24a‧‧‧貫穿矽通孔
26‧‧‧金屬墊
26a‧‧‧金屬墊
28‧‧‧覆蓋層
30‧‧‧導電端子層(圖2)/中介層(圖4、5)
35‧‧‧BEOL佈線
45‧‧‧微柱互連
50‧‧‧貫穿矽通孔
55‧‧‧焊接連接
100a‧‧‧nGaN
100b‧‧‧InGaN
100c‧‧‧pGaN
100d‧‧‧端子層
100e‧‧‧磷層
100f‧‧‧彩色濾光器
下文的詳細說明將經由本發明例示性具體實施例的非限制性範例並參考所述複數個圖式來描述本發明。
圖1顯示根據本發明的態樣的一畫素設計。
圖2顯示根據本發明一態樣的微發光二極體組裝體及相應製造程序的橫截面。
圖3顯示根據本發明的態樣的另一結構及相應製造程序。
圖4顯示根據本發明的態樣的微發光二極體顯示器組裝體的橫截面。
圖5顯示根據本發明的態樣的微發光二極體顯示器組裝體的透視圖。
圖6顯示根據本發明的態樣的製造程序的流程圖。
本發明關於半導體結構，特別是關於微發光二極體顯示器組裝體及製造方法。更特別地，本發明關於由使用貫穿矽通孔技術放置於較大陣列中的多個小的微發光二極體陣列所組成的微發光二極體顯示器組裝體。亦即，微發光二極體顯示器組裝體使用在一陣列中的多個小晶粒來取代一個大的陣列。微發光二極體顯示器組裝體可與例如2.5D及3D技術一起使用。
在具體實施例中，每一小的微發光二極體陣列包含貫穿矽通孔(through silicon via，TSV)技術，用以架置於一基板上以形成較大的顯示器組裝體。在具體實施例中，TSVs連接至每一個別的微發光二極體(例如畫素)。TSV微發光二極體陣列裝置可使用矽或玻璃中介層、或直接地連接至畫素驅動器。在具體實施例中，矽中介層允許畫素驅動電路的直接整合；然而，玻璃中介層將需要獨立的畫素驅動器。在具體實施例中，多個小微發光二極體陣列提供高密度的佈線至每一個TSV/微發光二極體連接。
有利地，相較於使用單一、較大的畫素陣列，微發光二極體顯示器組裝體針對大顯示器尺寸提供了改良的(例如高的)收益。這是由於以下事實：可組裝多個小晶粒以共同地形成較大的LED陣列；而非單一的大晶粒。更特別地，若在單一大晶粒上發現一失效，將需要捨棄整個晶粒；然而，如本文所揭露，若在較小的晶粒上發現單一失效，將只需捨棄單一個較小的晶粒。這將顯著地降低成本並改善收益，因為在畫素失效時，捨棄較小的晶粒比捨棄較大晶粒更省費用。
此外，更有效率地使用晶圓上的空間可顯著地降低製造成本。舉例來說，使用較小的晶粒有可能更有效率地利用晶圓邊緣周圍的未使用空間。此外，本文所描述的微發光二極體顯示器組裝體藉由使用中介層而提高了可靠性，其作用為電路板與微發光二極體晶粒之間的應力緩衝器。
本發明的微發光二極體顯示器組裝體可使用多種不同的工具以多種方式來製造。然而，一般而言，方法及工具係用以形成尺寸在微米及奈米等級的結構。用以製造本發明的微發光二極體顯示器組裝體的方法(即技術)已從積體電路(IC)技術採用。舉例來說，微發光二極體顯示器組裝體建立於晶圓上且實現於在晶圓頂部上由光學微影製程所圖案化的材料 薄膜中。特別地，晶圓焊墊結構的製造使用三個基本的構件：(i)基板上材料的薄膜的沉積，(ii)藉由光學微影成像施加圖案化光罩於薄膜頂部，以及(iii)選擇性地蝕刻薄膜至光罩。
圖1顯示用於根據本發明的態樣的一微發光二極體組裝體中的一單一畫素。熟此技藝者應理解到，圖1(及本文所述的其他圖式)也可代表任何可重複設計結構(例如記憶體胞陣列等)的佈局圖案。在圖1中，畫素10包含具有四個子畫素14a-14d的接觸板或電極12。在具體實施例中，舉例來說，接觸板或電極12可為由不透明材料(如金屬)所組成的奈米線接觸及反射器板，以最大化來自子畫素14a-14d的光發射。
在具體實施例中，畫素10具有6.35μm x 6.35μm的尺寸，且子畫素14a-14d具有3.175μm x 3.175μm的尺寸；然而本文也可考慮其他尺寸。如熟此技藝者所應理解，這些畫素10中的多個可形成於於根據本發明態樣的一單一微發光二極體組裝體上。舉例來說，本文所實施的微發光二極體組裝體可包含1000畫素乘1000畫素；然而本文可考慮其他畫素數目，其取決於組裝的技術或工具。
仍參考圖1，在一說明性範例中，子畫素14a-14d包含用於無機發光二極體(ILED)中的RGB畫素設計。在具體實施例中，子畫素14a-14d的每一個可具有不同數量的奈米線16，其由不同的材料組成以發射特定的顏色(例如波長)。在非限制性的範例中，(i)針對綠光，可有四個奈米線16用於子畫素14a、14d，(ii)針對藍光，可有九個奈米線16用於子畫素14b，以及(iii)針對紅光，可有四個奈米線用於子畫素14c。雖然子畫素14d顯示為子畫素14a的冗餘，但應理解到子畫素14d可為子畫素14a-14c中任一者的冗餘。或者，子畫素14d可為空的，例如沒有任何奈米線。
雖然對本發明的理解並不重要，但奈米線16可由不同材料組成以提供不同的波長。舉例來說，以下的表格1顯示可用於奈米線的半導體材料的範例組合。
圖2顯示根據本發明一態樣的微發光二極體組裝體及相應製造程序的橫截面。如圖2所示，微發光二極體組裝體20包含子畫素14a、14b，其每一者具有複數個奈米線16。在所示範例中，微發光二極體組裝體20的橫截面顯示每一畫素10a、10b的子畫素14a、14b。
如圖2進一步顯示，微發光二極體組裝體20更包含基板22，其具有複數個TSVs 24連接至與每一畫素10a、10b(例如子畫素14a、14b)電連接的金屬墊26(例如銅墊)。如所示，每一畫素使用單一TSV 24，其中TSV 24的直徑約為畫素節距的1/2。舉例來說，在說明性的具體實施例中，對節距約為6μm的畫素，TSV 24可具有約小於3μm的直徑/寬度；然而對較薄的晶粒可能有較小的尺寸。在具體實施例中，墊26可與pGaN子畫素14a、14b直接電通訊，且所有畫素共享覆蓋層nGaN連接28，反之亦然。在這個表示中，墊26a與TSVs 24a可連接至導電端子層30。如此，針對每一畫素，不需要有獨立的TSV或導電端子。
圖3顯示根據本發明態樣的另一結構及相應製造程序。在此結構中，畫素10係示意性地表示為由複數個層100a-100f所組成的堆疊結構，其每一者連接至形成於基板22中的TSV 24。在具體實施例中，層包含：nGaN 100a、InGaN 100b、pGaN 100c、端子層100d、磷層100e及彩色濾光器100f。應認識到，這些層係提供作為說明性範例且不應視作本發明的限制性特徵。為了簡化說明，並未顯示連線到獨立TSVs的共同pGaN端子。
在圖2及圖3的每一表示圖中，ILED晶圓係個別地形成，並藉著連結至TSV乘載晶圓(例如晶圓22)。再者，TSVs 24的形成可經由傳統的背面研磨製程並接著經由深矽蝕刻(如Bosch蝕刻)以形成與形成於晶圓前側上的墊對齊並將其暴露的通孔(且其與畫素電性接觸)。通孔接著塗佈介電質襯層，例如無機材料(像是SiO2)。在具體實施例中，介電質襯層將沉積至約200nm的厚度；然而本文可考慮其他厚度。障壁金屬(例如Ta或TiN)可形成於介電質襯層上以避免銅擴散至氧化層及晶圓。晶種層可濺鍍至障壁金屬上，並接著進行電鍍製程，例如銅電鍍製程。任何剩餘的材料可由化學機械研磨步驟移除。應理解到，元件符號24表示通孔本身內的不同材料。
圖4顯示根據本發明態樣的微發光二極體顯示器組裝體的橫截面。更特別地，圖4顯示架置在中介層30上的複數個微發光二極體組裝體20。在具體實施例中，中介層30可為由積體ILED畫素驅動電路所組成的矽中介層。在其他具體實施例中，中介層30可為玻璃中介層或主動晶粒。在具體實施例中，複數個微發光二極體組裝體20(例如包含TSV互連的至少兩個ILED晶粒)等距地放置於中介層30上，如本文所進一步描述。
後段製程(BEOL)佈線35位在(例如黏合於)複數個微發光二極體組裝體20與中介層30之間。在具體實施例中，BEOL佈線35包含將複數個微發光二極體組裝體20的每一畫素10電性連接至中介層30的佈線結構。更特別地，每一微發光二極體組裝體20的每一畫素的TSVs 24的每一者係連接至一微柱互連(micropillar interconnect)45，其又連接至BEOL佈線35的佈
線結構。在具體實施例中，微柱互連45的節距將與TSVs 24匹配，例如5-10μm節距。熟此技藝者應理解到，微柱互連45可為傳統的受控覆晶接合(C4)焊料互連。在其他具體實施例中，複數個微發光二極體組裝體20可群焊至BEOL佈線35。
仍參考圖4，BEOL佈線35的佈線結構連接至中介層30的複數個TSVs 50。中介層30的TSVs 50可由與微發光二極體組裝體20的每一畫素的TSVs 24相同的方法來製造。在具體實施例中，當連接中介層30的複數個TSVs 50時，跨晶粒畫素節距/間距“X”較佳等於晶粒內畫素節距/間距“X’’’，以免破壞整體畫素陣列的顯示。在其他具體實施例中，中介層30包含與中介層30的TSVs 50電性連接的焊接連接55。如此，焊接連接55為微發光二極體組裝體20提供外部互連。
圖5顯示根據本發明態樣的微發光二極體顯示器組裝體的透視圖。更特別地，圖5顯示架置在中介層30上的複數個微發光二極體組裝體20。在具體實施例中，複數個微發光二極體組裝體20(例如至少兩個ILED晶粒)每一包含具有TSV互連的複數個發光二極體畫素10，其等距地放置於中介層30上。BEOL中介層35位在複數個微發光二極體組裝體20與中介層30之間。中介層30包含焊接連接55以對微發光二極體組裝體20提供外部互連。
圖6顯示根據本發明態樣的製造程序的流程圖。特別地，為製造圖2至圖5所示的結構，在步驟600中使用傳統的CMOS製程在晶圓上製造LED裝置(如畫素10)。在步驟605，將晶圓翻轉並執行背面研磨製程。在具體實施例中，背面研磨製程可將晶圓(例如矽)薄化至約50微米。在步驟610，晶圓的背面接著進行深矽蝕刻(即Bosch蝕刻)以形成通孔，其與形成於晶圓前側上的墊對齊並將其暴露(且其與畫素電性接觸)。在步驟S615，在通孔中形成介電質襯層。介電質襯層可例如為有機旋塗式材料(SiCOH)或聚亞醯胺材料。在具體實施例中，介電質襯層將沉積至約200nm的厚度。在步驟620，障壁金屬可形成於介電質襯層上以避免銅擴散至氧化層及晶圓。在具體實施例中，障壁金屬可為由濺鍍化學氣相沈積製程所沉積的Ta或TiN。在步驟625，執行電鍍製程。舉例來說，將晶種層濺鍍至障壁金屬上，並接著以電鍍製程(例如銅電鍍製程)填充通孔。在步驟630，可由化學機械研磨(CMP)製程從晶圓的背面表面移除任何剩餘的材料。在步驟635，可形成與TSV的金屬材料直接電性連接的互連。在步驟640，舉例來說，可藉由將每一微發光二極體陣列連接至中介層而將微發光二極體陣列組裝成一較大的陣列。
上述的方法係用於積體電路晶片的製造。所形成的積體電路晶片可由製造者以原始晶片的形式(亦即作為具有多個未封裝晶片的單一晶圓)作為裸晶粒分送、或以封裝形式分送。在後者情況下，晶片被架置在單一晶片封裝(例如塑料載體，具有附著至主機板或其他更高層級載體的引線)中或在多晶片封裝(例如具有表面互連或埋置互連之其中一者或兩者的陶瓷載體)中。在任何情況下，晶片接著與其他晶片、分立電路元件、及/或其他信號處理裝置整合作為(a)中間產品(如主機板)或(b)最終產品的一部份。最終產品可為包含積體電路晶片的任何產品，其範圍從玩具或其他低階應用到具有顯示器、鍵盤或其他輸入裝置、及中央處理器的高級電腦產品。
本發明的各種具體實施例的描述已呈現用於說明目的，但並非窮盡的或受限於所揭露的具體實施例。在不偏離所述具體實施例的範疇及精神下，許多修改及變化對本領域的普通技術人員將為顯而易見的。本文所使用的術語係選擇以最佳地解釋具體實施例的原理、實際應用或對市場中所發現技術的技術改良、或使本領域中的其他普通技術人員能理解本文所揭露的具體實施例。
10‧‧‧畫素
20‧‧‧微發光二極體組裝體
24‧‧‧貫穿矽通孔
30‧‧‧中介層
35‧‧‧BEOL佈線
45‧‧‧微柱互連
50‧‧‧貫穿矽通孔
55‧‧‧焊接連接
Claims (20)
- 一種半導體結構，包含：一中介層；複數個微發光二極體陣列，每一個微發光二極體陣列包含複數個畫素，其由多個子畫素所組成；以及複數個貫穿孔，其由一介電質襯層、一障壁金屬與一電鍍金屬所組成，該複數個貫穿孔的每一者直接在該複數個微發光二極體陣列的每一者的該複數個畫素的每一者的下方且藉由一金屬墊連接至該複數個微發光二極體陣列的每一者的該複數個畫素的每一者，該金屬墊實體接觸該各個畫素且直接位於該各個畫素的下方，其中該複數個貫穿孔的每一者更連接至該中介層且每個畫素使用一單一的貫通孔。
- 如申請專利範圍第1項所述之結構，其中該中介層為具有多個驅動電路的一矽中介層。
- 如申請專利範圍第1項所述之結構，其中該中介層為一玻璃中介層。
- 如申請專利範圍第1項所述之結構，其中該等貫穿孔為貫穿矽通孔。
- 如申請專利範圍第4項所述之結構，其中各該畫素藉由該等貫穿矽通孔的其中之獨立一者而連接至該中介層。
- 如申請專利範圍第1項所述之結構，其中該等畫素由GaN組成，且該等貫穿孔為與該等畫素整合至相同的一晶粒中的銅貫穿矽通孔。
- 如申請專利範圍第1項所述之結構，其中該等貫穿孔藉由與該等貫穿孔的一節距匹配的多個微柱(micro-pillar)而連接至該中介層。
- 如申請專利範圍第1項所述之結構，其中該複數個微發光二極體陣列在該中介層上等距地間隔開。
- 如申請專利範圍第8項所述之結構，其中一跨晶粒畫素節距等於在該複數個微發光二極體陣列之每一者內的一畫素節距。
- 如申請專利範圍第1項所述之結構，其中該等貫穿孔的一直徑約為一畫素節距的二分之一。
- 一種半導體結構，包含：一中介層，包含複數個貫穿孔；複數個微發光二極體陣列，每一個微發光二極體陣列包含複數個貫穿孔與複數個畫素，其中該複數個畫素的每一者由多個子畫素所組成，該複數個貫穿孔由一介電質襯層、一障壁金屬與一電鍍金屬所組成，該複數個貫穿孔的每一者直接在該複數個畫素其中之一獨立畫素的下方且藉由一金屬墊連接至該複數個畫素其中之該獨立畫素，該金屬墊實體接觸該獨立畫素且直接位於該獨立畫素的下方；以及一後段製程佈線結構，其位於且藉由複數個微柱連接在該中介層與該複數個微發光二極體陣列之間，其中該複數個微柱的每一者對齊且藉由該複數個貫穿孔的個別一者連接至該複數個畫素其中之該獨立畫素，使得每個單一的畫素分別使用只有一個單一的微柱。
- 如申請專利範圍第11項所述之結構，其中， 該複數個微發光二極體陣列係等距地間隔開；以及一跨晶粒畫素節距等於在該複數個微發光二極體陣列之每一者內的一畫素節距。
- 如申請專利範圍第12項所述之結構，其中該等畫素由GaN組成，且該複數個微發光二極體陣列的該等貫穿孔為與該等畫素整合至相同的一晶粒中的銅貫穿矽通孔。
- 如申請專利範圍第13項所述之結構，其中該等貫穿矽通孔藉由該等微柱(micro-pillars)而連接至該後段製程佈線結構。
- 如申請專利範圍第14項所述之結構，其中該等微柱為焊接連接。
- 如申請專利範圍第14項所述之結構，其中該等微柱與該等貫穿矽通孔的一節距匹配。
- 如申請專利範圍第13項所述之結構，其中該複數個微發光二極體陣列的每一貫穿孔的一直徑約為一畫素節距的二分之一。
- 如申請專利範圍第11項所述之結構，其中該中介層為具有多個驅動電路的一矽中介層。
- 如申請專利範圍第11項所述之結構，其中該中介層為一玻璃中介層。
- 如申請專利範圍第1項所述之結構，更包含一後段製程佈線結構，其插入在該中介層與該複數個微發光二極體陣列之間，該後段製程佈線 結構藉由獨立的多個微柱連接該等畫素之每一者的該複數個貫穿孔之每一者與該中介層，該等微柱對齊該等畫素之每一者的該複數個貫穿孔的每一者。
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Also Published As
| Publication number | Publication date |
|---|---|
| US10770440B2 (en) | 2020-09-08 |
| TW201839952A (zh) | 2018-11-01 |
| CN108630717A (zh) | 2018-10-09 |
| CN108630717B (zh) | 2023-02-21 |
| US20180269191A1 (en) | 2018-09-20 |
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