US20100181589A1 - Chip package structure and method for fabricating the same - Google Patents
Chip package structure and method for fabricating the same Download PDFInfo
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- US20100181589A1 US20100181589A1 US12/636,657 US63665709A US2010181589A1 US 20100181589 A1 US20100181589 A1 US 20100181589A1 US 63665709 A US63665709 A US 63665709A US 2010181589 A1 US2010181589 A1 US 2010181589A1
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- hole
- package structure
- chip package
- carrier substrate
- cavity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
Abstract
The invention provides a chip package structure and method for fabricating the same. The chip package structure includes a carrier substrate. A plurality of isolated conductive layers is disposed on the carrier substrate. At least one chip is disposed on the carrier substrate, wherein the chip has a plurality of electrodes. The electrodes are electrically connected to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminating holes.
Description
- The present invention relates to a chip package structure and method for forming the same, and in particular relates to a light emitted chip package structure and method for forming the same.
- The chip packaging process is one of the important processes for forming chips. A chip package structure, not only provides an interface for connecting chips to electronic elements, but also provides protection for chips from environmental contaminants, along with other functions.
- With increasing development of the semiconductor fabrication process, chips are being formed in smaller and smaller dimensions. However, due to the ever-decreasing size and the ever-increasing density of the chips, number and density of the input/output (I/O) connections of chips have increased. Therefore, the chip area for conductive paths between chips and outside features formation is not enough. The fabrication cost can not be reduced due to a huge amount of the golden wires using as I/O connections between chip arrays and outside features, especially in package structure composed by optoelectronic chips.
- Thus, a novel package structure for improving the package structure of chips and method for forming the same is desired.
- An exemplary embodiment of a method for fabricating a chip package structure is provided. The chip package structure comprises a carrier substrate having a cavity. A plurality of isolated conductive layers is disposed on the carrier substrate; at least one chip disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminated holes.
- An exemplary embodiment of a method for fabricating a chip package structure is provided. The method for fabricating a chip package structure comprises providing a carrier substrate. A first hole is formed from a first surface of the carrier substrate. A second hole is formed from a second surface of the carrier substrate, connected and disposed corresponding to the first hole. A cavity is formed on the second surface of the carrier substrate. A conductive path is formed in the first hole and the second hole. A plurality of conductive layers is formed isolated from each other, electrically connected to the conductive path. At least one chip is disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers.
- The following description is of a mode for carrying out the invention. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice of the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense.
- Embodiments of the package structure for chips of the invention packaged by a wafer level packaging (WLP) process may be applied to active or passive devices, or electronic components with digital or analog circuits, such as optoelectronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, and physical sensors for detecting heat, light, or pressure. Particularly, a wafer level packaging (WLP) process may be applied to package semiconductor chips, such as image sensor devices, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave devices, pressure sensors, or ink printer heads. The wafer level packaging process herein mainly means that after the packaging process is accomplished during a wafer stage, a wafer with chips is cut to obtain separate independent packages. However, in an embodiment of the invention, separate independent chips may be redistributed overlying a supporting wafer and then be packaged, which may also be referred to as a wafer level packaging process. In addition, the wafer level packaging process may also be adapted to form electronic device packages of multi-layered integrated circuit devices by stacking a plurality of wafers having integrated circuits together.
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FIGS. 1A-1F are cross sections showing the steps for fabricating achip package structure 500 according to an embodiment of the invention. - As shown in
FIG. 1A firstly, acarrier substrate 200 having anupper surface 200 a and an oppositelower surface 200 b is provided. Thecarrier substrate 200 may comprise a silicon substrate, a semiconductor substrate, a compound semiconductor substrate, a semiconductor wafer, a sapphire substrate or combinations thereof. - Next, still referring to
FIG. 1A ,holes 202 a′ and 202 b′ penetrating through a portion of thecarrier substrate 200 are formed from thelower surface 200 b of thecarrier substrate 200. Thecarrier substrate 200 is exposed from the bottom of theholes 202 a′ and 202 b′. In one embodiment, deposition of the holes may be selectively arranged. For example, the holes may be located outside of a cavity formed in thecarrier substrate 200 when a chip is disposed on thecarrier substrate 200 in a following step. Forming through-holes stepwise instead of forming through-holes in a single process may reduce process difficulty and increase product yield. - Next, referring to
FIG. 1B ,insulating layers 204 a′ and 204 b′ are selectively formed on sidewalls of theholes 202 a′ and 202 b′ and a portion of thecarrier substrate 200. Theinsulating layers 204 a′ and 204 b′ may be made of non-organic materials comprising silicon oxide, silicon nitride, silicon oxinitride, metal oxide or combinations thereof, or organic materials comprising polyimide, BCB.TM. Theinsulating layers 204 a′ and 204 b′ may be formed by a spin coating or spray coating method, or may be formed by other suitable deposition methods, such as a chemical vapor deposition, low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition process. In one embodiment, photo insulating materials may be selectively used to serve as theinsulating layers 204 a′ and 204 b′ to facilitate patterning of theinsulating layers 204 a′ and 204 b′. Additionally, if the carrier substrate is made of an insulating substrate, the step of depositing the insulating layer before forming a conductive layer on the carrier substrate can be omitted. - Next, still referring to
FIG. 1B ,hole conducting layers 206 a′ and 206 b′ are formed on the sidewalls of theholes 202 a′ and 202 b′. The hole conductinglayers 206 a′ and 206 b′ further extend on thelower surface 200 b of thecarrier substrate 200 to serve as conductive paths between the chip package structure and an outside feature. For example, thehole conducting layers 206 a′ and 206 b′ extending on thelower surface 200 b of thecarrier substrate 200 may further electrically connect to an outside feature such as printed circuit board through solder balls or bumps. The hole conductinglayers 206 a′ and 206 b′ may be made of metal materials including, conductive polymer materials, conductive ceramic materials or combinations thereof. The hole conductinglayers 206 a′ and 206 b′ may be formed by using, for example, a physical vapor deposition, chemical vapor deposition or chemical electroplating process. Next, a photolithography/etching process is performed to pattern thehole conducting layers 206 a′ and 206 b′. In this embodiment, thehole conducting layers 206 a′ and 206 b′ are preferably formed in the same step. That is, thehole conducting layers 206 a′ and 206 b′ are preferably formed by patterning a single conductive layer. - Next, still referring to
FIG. 1B ,filling layers 208 a′ and 208 b′ are selectively formed on thehole conducting layers 206 a′ and 206 b′ in theholes 202 a′ and 202 b′. Thefilling layers 208 a′ and 208 b′ may comprise polymer materials, for example, solder masks, polyimides, or polyimide-like materials, which can serve as permanent materials or combinations thereof. Thefilling layers 208 a′ and 208 b′ may be formed by using, for example, an electroplating, spin coating, spray coating, curtain coating process or combinations thereof. - Next, as shown in
FIG. 1C , holes 202 a″ and 202 b″ are formed from theupper surface 200 a of thecarrier substrate 200 by methods such as an etching or laser drilling process. Theholes 202 a″ and 202 b″ substantially align with theunderlying holes 202 a′ and 202 b′. In one embodiment, theholes 202 a″ and 202 b″ are formed by an etching process, wherein the lateralhole conducting layers 206 a′ and 206 b′ on the bottom of theholes 202 a′ and 202 b′ may respectively serve as etching stop layers during formation of theholes 202 a″ and 202 b″ during an etching process. Therefore, thehole conducting layers 206 a′ and 206 b′ are respectively exposed from the bottom of theholes 202 a″ and 202 b″. In one embodiment, the insulatinglayers 204 a′ and 204 b′ on the bottoms of theholes 202 a′ and 202 b′ are also removed when forming theholes 202 a″ and 202 b″. Additionally, in one embodiment, top surfaces of the previously formed holes, for example, the lower-level holes 202 a′ and 202 b′, may be larger than top surfaces of the subsequently formed holes, for example, the upper-level holes 202 a″ and 202 b″, thereby facilitating etching alignment. - Next, still referring to
FIG. 1C , acavity 203 is formed from theupper surface 200 a of thecarrier substrate 200 with extending into thecarrier substrate 200. A bottom of thecavity 203 is used for chips to be disposed thereon. In one embodiment, thecavity 203 and theholes 202 a″ and 202 b″ are preferably formed in the same step, thus reducing additional fabrication processes. In one embodiment, if the chip disposed on thecavity 203 is a light emitted diode (LED) chip, a reflection layer may be further formed on sidewalls and/or a bottom of thecavity 203 to increase emitting brightness. - Next, as shown in
FIG. 1D , insulatinglayers 204 a″ and 204 b″ are selectively formed on sidewalls and a bottom of theholes 202 a″ and 202 b″. The insulatinglayers 204 a″ and 204 b″ further extend on theupper surface 200 a of thecarrier substrate 200 and the sidewalls and the bottom of thecavity 203. The insulatinglayers 204 a″ and 204 b″ may have the same materials and formation processes as the insulatinglayers 204 a′ and 204 b′. - Next, as shown in
FIG. 1E , the insulatinglayers 204 a″ and 204 b″ on the bottom of theholes 202 a″ and 202 b″ are removed to expose thehole conducting layers 206 a′ and 206 b′. The method for removing the insulatinglayers 204 a″ and 204 b″ may comprise, for example, a photolithography and etching process or a laser removing process. Next,conductive layers 206 a″, 206 b″ and 202 c″ are conformably formed on the sidewalls and the bottoms of theholes 202 a″ and 202 b″ and thecavity 203. The hole conducting layers 206 a″ and 206 b″ may further extend from theupper surface 200 a of thecarrier substrate 200. In one embodiment, an LED array may be disposed on the bottom of thecavity 203. Preferably, a reflection layer may be formed on the sidewalls and the bottom of thecavity 203 to increase emitting efficiency of the LED array. In one embodiment, the reflection layer and thehole conducting layers 206 a″ and 206 b″ may be formed in the same step. The hole conducting layers 206 a″ and 206 b″ may have the same materials and formation processes as thehole conducting layers 206 a′ and 206 b′. The reflection layer may be made of metal materials having reflectivity, and the formation process thereof may be the same to thehole conducting layers 206 a″ and 206 b″. In this embodiment, the reflection layer may be formed by thehole conducting layers 206 a″, 206 b″ and 202 c″ extending on the sidewalls and the bottoms of thecavity 203. - Next, filling
layers 208 a″ and 208 b″ are selectively formed on thehole conducting layers 206 a″ and 206 b″ in theholes 202 a″ and 202 b″. The filling layers 208 a″ and 208 b″ may have the same materials and formation processes as the fillinglayers 208 a′ and 208 b′. - In this embodiment, the vertically laminated
holes 202 a′ and 202 a″ and thehole conducting layers 206 a′ and 206 a″ on the sidewalls of theholes 202 a′ and 202 a″ may construct a firstconductive path 320 a. Similarly, the vertically laminatedholes 202 b′ and 202 b″ and thehole conducting layers 206 b′ and 206 b″ on the sidewalls of theholes 202 b′ and 202 b″ may construct a secondconductive path 320 b. Additionally, in one embodiment as shown inFIG. 1E , an insulating layer comprising the insulatinglayers 204 a′, 204 a″, 204 b′ and 204 b″ is preferably between the firstconductive path 320 a/the secondconductive path 320 b and thecarrier substrate 200. The filling layers 208 a′, 208 a″, 208 b′ and 208 b″ may fill on the hole conducting layers of the firstconductive path 320 a and the secondconductive path 320 b. - Embodiments of the invention may further have many other variations. For example, the hole conducting layers of the first
conductive path 320 a and the secondconductive path 320 b may substantially fill the holes. A lateral conductive layer may be between the two laminated holes to electrically connect to the hole conducting layers. The other variations are dependant upon application and fabrication processes. - In this embodiment, the formation of the laminated holes comprise forming the upper holes and the upper conductive layers and then forming the lower holes and the lower conductive layers, but the invention is not limited thereto. Alternatively, the formation of the laminated holes may comprise forming lower holes and the lower conductive layers and then forming the upper holes and the upper conductive layers. Additionally, the cavity for the chip disposed thereon and the upper holes may be formed at the same step.
- Next, as shown in
FIG. 1F , achip array 301 comprising at least one chip, for example, a plurality ofchips chips carrier substrate 200 through anadhesive layer 324 such as a silver paste. In one embodiment, thechip array 301 may comprise an array constructed by light emitting components such as LEDs or laser diodes (LDs), but the invention is not limited thereto. Thechips first electrodes second electrodes first electrodes second electrodes chips chips first electrodes second electrodes first electrodes second electrodes conductive path 320 a and the secondconductive path 320 b through the hole conducting layer 206″. For example, thefirst electrode 310 a and thesecond electrode 310 b of thechip 302 a respectively electrically connect to thehole conducting layers 206 a″ and 206 c″. Thefirst electrode 311 a and thesecond electrode 311 b of thechip 302 b respectively electrically connect to thehole conducting layers 206 b″ and 206 c″. Therefore, thechips - As shown on
FIG. 1F , in other embodiments of the light emitting chips, afluorescent layer 336 having a uniform thickness may selectively conformably cover the light emittingchip array 301. Further, in other embodiments, alens structure 338 may be selectively formed on thechip array 301. Thelens structure 338 may be disposed as required. - The exemplary embodiments of the
chip package structure 500 have the following advantages. For example, the chip package structure is fabricated by a wafer level package process to package the chip array. Therefore, the chip package structure has much smaller dimensions than that of the conventional wire-bonding type chip package structure. When the chip package structure is arranged in a pixel array for illumination or display, an exemplary embodiment of the chip package structure may allow the pixel array to have a smaller pitch between each light emitting device. Therefore, improving pixel continuity and visual effect. Additionally, the conductive path is constructed by laminated the upper and lower holes, wherein the upper and lower holes further comprise a lateral conductive layer therebetween to increase conductive area of the hole conducting layers. - While the invention has been described by way of example and in terms of the embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
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FIGS. 1A-1F are cross sections showing the steps for fabricating a chip package structure according to an embodiment of the invention. -
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- 500˜chip package structure;
- 200˜carrier substrate;
- 200 a, 200 b˜surface;
- 202 a′, 202 b′, 202 a″, 202 b″˜hole;
- 203˜cavity;
- 204 a′, 204 b′, 204 a″, 204 b″˜insulating layer;
- 206 a′, 206 b′, 206 a″, 206 b″, 206 c″˜hole conducting layer;
- 208 a′, 208 b′, 208 a″, 208 b″˜filling layer;
- 301˜chip array;
- 302 a, 302 b˜chip;
- 310 a, 311 a˜first electrode;
- 310 b, 311 b˜second electrode;
- 320 a˜first conductive path;
- 320 b˜second conductive path;
- 324˜adhesive layer;
- 336˜fluorescent layer;
- 338˜lens structure.
Claims (20)
1. A chip package structure, comprising:
a carrier substrate having a cavity;
a plurality of isolated conductive layers disposed on the carrier substrate;
at least one chip disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers; and
a conductive path disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminated holes.
2. The chip package structure as claimed in claim 1 , further comprising an insulating layer isolating the conductive layers and the carrier substrate or the conductive path and the carrier substrate from each other.
3. The chip package structure as claimed in claim 1 , wherein the conductive layers are conformably disposed on sidewalls and a bottom portion of the cavity.
4. The chip package structure as claimed in claim 1 , wherein the carrier substrate is a silicon substrate.
5. The chip package structure as claimed in claim 1 , further comprising a reflection layer disposed on sidewalls and a bottom portion of the cavity.
6. The chip package structure as claimed in claim 1 , wherein the conductive path passes through the carrier substrate.
7. The chip package structure as claimed in claim 6 , wherein the conductive path comprises a plurality of vertically laminated holes and the conductive layers extend on a sidewall of the cavity.
8. The chip package structure as claimed in claim 7 , wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein the first hole and the second hole comprise a lateral conductive plate therebetween, wherein the lateral conductive plate electrically connects to the conductive layers extended on the sidewall of the cavity.
9. The chip package structure as claimed in claim 7 , wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.
10. The chip package structure as claimed in claim 7 , wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole, wherein the first hole and the second hole comprise a lateral conductive plate therebetween, wherein the lateral conductive plate electrically connects to the conductive layers extending on the sidewall of the cavity.
11. The chip package structure as claimed in claim 10 , wherein the first hole is a lower-level hole and the second hole is an upper-level hole.
12. The chip package structure as claimed in claim 11 , wherein a depth of the upper-level hole is the same to that of the cavity.
13. A method for fabricating a chip package structure, comprising:
providing a carrier substrate;
forming a first hole from a first surface of the carrier substrate;
forming a second hole from a second surface of the carrier substrate, connected and disposed corresponding to the first hole;
forming a cavity on the second surface of the carrier substrate;
forming a conductive path in the first hole and the second hole and forming a plurality of conductive layers isolated from each other, electrically connected to the conductive path; and
disposing at least one chip in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers.
14. The method for fabricating a chip package structure as claimed in claim 13 , further comprising forming an insulating layer on the carrier substrate to isolate the conductive layers from the conductive path.
15. The method for fabricating a chip package structure as claimed in claim 14 , wherein the first hole and the second hole comprise a lateral conductive plate therebetween.
16. The method for fabricating a chip package structure as claimed in claim 14 , wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.
17. The method for fabricating a chip package structure as claimed in claim 14 , wherein the first hole and the second hole comprise a lateral conductive plate therebetween, and a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.
18. The method for fabricating a chip package structure as claimed in claim 14 , wherein the first hole is a lower-level hole and the second hole is an upper-level hole.
19. The method for fabricating a chip package structure as claimed in claim 18 , wherein the upper-level hole and the cavity are formed in the same step.
20. The method for fabricating a chip package structure as claimed in claim 19 , wherein the upper-level hole and the lower-level hole are formed at different steps.
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US12/636,657 US20100181589A1 (en) | 2008-12-11 | 2009-12-11 | Chip package structure and method for fabricating the same |
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US12188008P | 2008-12-11 | 2008-12-11 | |
US12/636,657 US20100181589A1 (en) | 2008-12-11 | 2009-12-11 | Chip package structure and method for fabricating the same |
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US12/636,660 Active 2029-12-24 US8237187B2 (en) | 2008-12-11 | 2009-12-11 | Package structure for chip and method for forming the same |
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Also Published As
Publication number | Publication date |
---|---|
CN101794853A (en) | 2010-08-04 |
US20100148210A1 (en) | 2010-06-17 |
CN101853842A (en) | 2010-10-06 |
TW201114003A (en) | 2011-04-16 |
CN101853842B (en) | 2012-03-21 |
US8237187B2 (en) | 2012-08-07 |
TW201023313A (en) | 2010-06-16 |
TWI484606B (en) | 2015-05-11 |
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