TWI698941B - Two-sided stacked die package and packaging method thereof - Google Patents

Abstract

The present invention relates to a two-sided die package and packaging method thereof. A plurality of first dies and second dies are respectively stacked on two opposite sides of a first RDL and electrically connected to the RDL by wires. A first encapsulation encapsulates the first dies and a second encapsulation encapsulates the second dies. A plurality of metal posts are formed inside the second encapsulation and a second RDL is formed on the second encapsulation. Each metal post is electrically connected between the first and second RDLs. Therefore, in the two-sided die package of the present invention, a plurality of first and second pads of the first RDL are not limited to form on only one of dies only and an amount of the dies is not limited.

Description

Double-sided stacked chip packaging structure and manufacturing method thereof

The invention relates to a stacked chip packaging structure and a manufacturing method thereof, in particular to a double-sided stacked chip packaging structure and a manufacturing method thereof.

With the increasing demand for terminal product applications and the evolution of technology trends, the bandwidth, capacity, and work efficiency required for components have also increased. The number of chips required has increased. Within a certain number of chips, a stacked chip package structure can provide good The semiconductor component packaging yield rate.

For semiconductor components exceeding a certain number of chips, a double-sided stacked chip package structure 80 as shown in FIG. 4 can be adopted, that is, a chip set 82 is partially stacked on the upper surface 811 and the lower surface 812 of an interposer 81. , 83, and through the existing wire bonding process steps, the plurality of chips 831 of the chip set 83 located on the upper surface 811 are electrically connected with the contacts of the upper surface 811, and the plurality of chips 83 located on the lower surface 812 The chip 831 is electrically connected to the contacts of the lower surface 812, and the lowermost chip of the chip set 83 (hereinafter referred to as the signal transmission chip 831') stacked on the lower surface 812 is further formed with a plurality of external pads 832. Exposed outside the gel 84. Therefore, the external pad 832 of the signal transmission chip 831' must be connected to the signal contacts of other chips 821 and 831 in addition to being electrically connected to its own signal contacts.

In other words, the signal contacts of all the chips in the upper and lower chipset must be integrated to the signal transmission chip to be electrically connected to the corresponding external pad; therefore, due to a certain chip area, it is bound to be limited The number of external pads naturally limits the number of chips that can be packaged by this double-sided stacked chip package structure, and it is necessary to further improve it.

In view of the disadvantages of the aforementioned double-sided stacked chip package structure, the main purpose of the present invention is to provide a new double-sided stacked chip package structure.

The main technical means used to achieve the above objective is to make the double-sided stacked chip package structure include: a first redistribution layer having a first surface and a second surface, and a plurality of second surfaces are formed on the first surface A contact, and a plurality of second contacts and a plurality of third contacts are formed on the second surface; a plurality of first chips are partially stacked on the first surface of the first redistribution layer, each of the first chips has Exposed first metal contacts, each of the first metal contacts is electrically connected to the first contact corresponding to the first surface by a first metal wire; a plurality of second chips are partially stacked on the first On the second surface of the redistribution layer, each of the second chips has exposed second metal contacts, and each of the second metal contacts is electrically connected to the second contact corresponding to the second surface by a second metal wire Points; a plurality of metal pillars, the common end of which is respectively electrically connected to the third contact on the second surface of the first redistribution layer, and the height of each metal pillar is higher than the height of the second metal wires; A first molding compound is formed on the first surface of the first redistribution layer to cover the first chip set and the first metal wires; a second molding compound is formed on the first On the second surface of the redistribution layer, the second chip set, the second metal wires and the metal pillars are covered; wherein the other end of the metal pillars is exposed to an outside of the second sealing compound Surface; and A second redistribution layer has a third surface formed on the outer surface of the second encapsulant body and electrically connected to the exposed side of the metal pillars, and a fourth surface is formed with a plurality of external pads.

It can be seen from the above description that the double-sided stacked chip packaging structure of the present invention is mainly used to package two sets of chips on both sides of the first redistribution layer, and a metal pillar is directly formed on one of the sides, and the metal pillar is an electrical The second redistribution layer connected to the outer surface of the second encapsulant; in this way, the double-sided stacked chip package structure of the present invention does not need to concentrate the first and second contacts of the first redistribution layer on one chip The number of stacked wafers is not limited.

The main technical means used to achieve the above-mentioned purpose is to make the manufacturing method of the double-sided stacked chip package structure include: (a) preparing a carrier board on which a first redistribution layer is formed; (b) placing a plurality of first The chips are sequentially partially stacked on a first surface of the first redistribution layer, and the first metal contacts of each first chip and a plurality of first contacts on the first surface are exposed; (c) each The first metal contact is wire-bonded and electrically connected to the corresponding first contact, so that a first metal wire is connected between each first metal contact and the corresponding first contact; (d) at the first metal contact A first molding compound is formed on the first surface of a redistribution layer to cover the first chips and the first metal wires; (e) inverting the carrier board to make the carrier board from the first A second surface of the redistribution layer is detached, so that the plurality of second contacts and the plurality of third contacts of the second surface are exposed; (f) a metal pillar is respectively formed on the exposed third contacts; (g) ) A plurality of second chips are sequentially partially stacked on the second surface of the first redistribution layer, and the second metal contacts of each second chip and the plurality of second contacts on the second surface are exposed; (h) Wire each of the second metal contacts to the corresponding second contacts; (i) A second molding compound is formed on the second surface of the first redistribution layer to cover the second chips, the second metal wires and the metal pillars, one end of each metal pillar It is exposed on an outer surface of the second encapsulant body; (j) a second redistribution layer is formed on the outer surface of the encapsulant body; and (k) a plurality of external pads are formed on the second redistribution layer.

It can be seen from the above description that the manufacturing method of the double-sided stacked chip packaging structure of the present invention is mainly used for packaging the two-sided double-sided chips of the first redistribution layer, so that a metal pillar is directly formed on one side, and the metal pillar is Electrically connected to the second redistribution layer on the outer surface of the second encapsulant; in this way, the double-sided stacked chip package structure of the present invention does not need to concentrate the first and second contacts of the first redistribution layer on one of them On the wafer, there is no limit to the number of stacked wafers.

The main technical means used to achieve the above purpose is to make another manufacturing method of the double-sided stacked chip package structure include: (a) preparing a carrier board on which a first redistribution layer is formed; (b) combining plural The first chips are partially stacked on a first surface of the first redistribution layer in sequence, and the first metal contacts of each first chip and the plurality of first contacts on the first surface are exposed; (c) Wire each of the first metal contacts to the corresponding first contacts; (d) forming a first sealing compound on the first surface of the first redistribution layer to cover the first A chip and the first metal wires; (e) after reversing the carrier board, the carrier board is separated from a second surface of the first redistribution layer, so that a plurality of second contacts and a plurality of second contacts on the second surface The third contact is exposed; (f) a plurality of second chips are sequentially partially stacked on the second surface of the first redistribution layer, and the second metal contacts of each second chip and the second surface The plurality of second contacts of are exposed; (g) wire each of the second metal contacts to the corresponding second contacts; (h) A second molding compound is formed on the second surface of the first redistribution layer to cover the second chips and the second metal wires; (i) corresponding to each of the second molding compound A through hole is formed at the third contact position, and a metal pillar is plated in each through hole, so that one end of each metal pillar is exposed on an outer surface of the second sealing compound; (j) on the sealing body A second redistribution layer is formed on the outer surface of, and (k) a plurality of external pads are formed on the second redistribution layer.

It can be seen from the above description that the manufacturing method of the double-sided stacked chip package structure of the present invention is mainly used to package the two groups of double-sided chips of the first redistribution layer, one of which is directly electrically connected with a metal pillar, and the metal The pillar is electrically connected to the second redistribution layer on the outer surface of the second encapsulant; in this way, the double-sided stacked chip package structure of the present invention does not need to concentrate the first and second contacts of the first redistribution layer in it There is no limit to the number of stacked chips on one chip.

10: The first heavy wiring layer

101: first surface

102: second surface

11: The first contact

12: second contact

13: Third contact

14: Dielectric body

15: Internal connection line

20: The first chip

21: The first metal contact

22: The first metal wire

221: first straight line segment

222: The second upright segment

30: second chip

31: The second metal contact

32: The second metal wire

40, 40’: Metal pillar

501: outer surface

51: The first sealant

52: The second sealant

60: second wiring layer

601: Third Surface

602: Fourth Surface

603: external pad

611: tin ball

62: The third wiring layer

621: Fourth Contact

622: Internal connection line

70: carrier board

80: Double-sided stacked chip package structure

81: Intermediary layer

811: upper surface

812: lower surface

82: Chipset

821: chip

83: Chipset

831: Chip

831’: Signal transmission chip

832: external pad

84: sealant

Fig. 1: A cross-sectional view of the first embodiment of the double-sided stacked chip package structure of the present invention.

2A to 2H: the packaging flow chart of the first embodiment of the manufacturing method of the double-sided stacked chip packaging structure of the present invention.

Figures 2-1A to 2-1D: the packaging flow chart of the second embodiment of the manufacturing method of the double-sided stacked chip packaging structure of the present invention.

3A to 3D: a partial packaging flow chart of the third embodiment of the manufacturing method of the double-sided stacked chip packaging structure of the present invention.

Figure 4: A cross-sectional view of an existing double-sided stacked chip package structure.

The present invention proposes an improvement to the double-sided stacked chip package structure, so that the number of chips that can be packaged by the double-sided stacked chip package structure is not limited to the chip size. The following is a detailed description of the technology of the present invention with a plurality of embodiments and drawings. content.

First, please refer to FIG. 1, which is a double-sided stacked chip package structure of the present invention. It includes a first redistribution layer 10, a plurality of first chips 20, a plurality of second chips 30, a plurality of metal pillars 40, and a first sealing compound. 51. A second sealing compound 52 and a second rewiring layer 60.

The first redistribution layer 10 includes two opposite first surfaces 101 and a second surface 102. A plurality of first contacts 11 are formed on the first surface 101, and a plurality of first contacts 11 are formed on the second surface 102. The second contact 12 and a plurality of third contacts 13; in this embodiment, the first redistribution layer 10 is formed with a plurality of inner connecting wires 15 in a dielectric body 14, and the inner connecting wires 15 are used The first contacts 11 are electrically connected with the second contacts 12 and the third contacts 13, and the third contacts 13 are located outside the second contacts 12.

The aforementioned first chips 20 are partially stacked on the first surface 101 of the first redistribution layer 10 in sequence, and the first metal contacts 21 of each first chip 20 are exposed, and each of the first metal contacts The point 21 is electrically connected to the corresponding first contact 11 on the first surface 101 of the first redistribution layer 10 by a first metal wire 22. In the embodiment, the partial stacking method of the first wafers 20 is a pick-and-place method, which is partially stacked one after another in a step offset, stagger, tower, etc.; and The number of the first chips 20 is greater than or equal to two, but the invention does not limit the number of the first chips.

The aforementioned second chips 30 are also partially stacked on the second surface 102 of the first redistribution layer 10 in sequence, and the second metal contacts 31 of each second chip 30 are exposed, and each of the second metal contacts The point 31 is electrically connected to the corresponding second contact point 12 on the second surface 102 of the first redistribution layer 10 by a second metal wire 32. In the embodiment, the partial stacking method of the second wafers 30 is a pick-and-place method, one after another in a step offset, staggered, tower, etc. The rows are partially stacked; and the number of the second wafers 30 is greater than or equal to two, but the invention does not limit the number of the first wafers.

The common ends of the plurality of metal pillars 40 are respectively electrically connected to the third contacts 13 on the second surface 102 of the first redistribution layer 10, and the height of each metal pillar 40 is higher than the second metal The height of line 32.

The first encapsulant 51 is formed on the first surface 101 on the first redistribution layer 10 to cover the first chips 20; and the second encapsulant 52 is formed on the first redistribution layer On the second surface 102 of 10, the second chips 30 and the metal pillars 40 are covered; the other end of the metal pillars 40 is exposed on an outer surface 501 of the second sealing compound 52; preferably Ground, the other end of the metal pillars 40 is flush with the outer surface 501 of the second sealing compound 52.

The second redistribution layer 60 includes a third surface 601 and a fourth surface 602 opposed to each other. The fourth surface 602 is formed on the outer surface 501 of the second molding compound 52 and is connected to the metal pillars 40. The exposed side is electrically connected, and the third surface 601 is formed with a plurality of external pads 603. In this embodiment, the external pads 603 are further formed with solder balls 61 or bumps, respectively.

Based on the above description of the structure of the double-sided stacked chip package structure of the present invention, various manufacturing methods for completing the double-sided stacked chip package structure are further described below.

First, please refer to FIG. 2A to FIG. 2H, a first embodiment of a double-sided stacked chip packaging method of the present invention; in this embodiment, the packaging process method is the RDL first process, which It includes the following steps (a) to (k).

As shown in step (a) of FIG. 2A, first prepare a carrier 70 on which the first rewiring layer 10 is formed, so the second contacts can be formed on the carrier 70 in sequence 12 and the third contact 13, the dielectric body 14, the inner connecting wires 15, and the first contacts 11; in this step (a), the first contacts 11 are exposed upward.

As shown in step (b) of FIG. 2B, the first chips 20 are sequentially partially stacked on a first surface 101 of the first redistribution layer 10, and the first metal of each first chip 20 is The contact 21 and the plurality of first contacts 11 on the first surface 101 are all exposed. In this embodiment, the partial stacking of the first wafers 20 is a pick-and-place method, which is partially stacked one after another in a step offset, staggered, tower, etc.; and The number of the first chips 20 is greater than or equal to four, but the invention does not limit the number of the first chips.

As shown in step (c) of FIG. 2C, the first metal contacts 21 of each of the first chips 20 are electrically connected to the corresponding first contacts 11, so that each of the first metal contacts 21 and The first metal wire 22 is connected between the corresponding first contacts 11.

As shown in step (d) of FIG. 2D, a first molding compound 51 is formed on the first surface 101 of the first redistribution layer 10 to cover the first chips 20 and the first metal wires twenty two.

In the above step (e), after the carrier board 70 of FIG. 2D is reversed, the carrier board 70 is separated from a second surface 102 of the first redistribution layer 10, as shown in FIG. 2E, The plurality of second contacts 12 and the plurality of third contacts 13 of the two surfaces 102 are exposed upward.

As shown in step (f) of FIG. 2E, a metal pillar 40 is formed on the exposed third contacts 13 respectively.

As shown in step (g) of FIG. 2F, a plurality of second chips 30 are sequentially partially stacked on the second surface 102 of the first redistribution layer 10, and the second metal connection of each second chip 30 is The points 31 and the plurality of second contacts 12 on the second surface 102 are all exposed upward; in the embodiment, the partial stacking of the second wafers 30 is a pick-and-place method, one Then, they are partially stacked one by one in a step offset, staggered, tower-like manner, etc.; and the number of the second wafers 30 is greater than or equal to four, but the present invention does not limit the number of the first wafers.

In step (h) shown in FIG. 2F, the second metal contacts 31 of each second chip 30 are electrically connected to the corresponding second contacts 12, so that each of the second metal contacts 31 corresponds to The second connection The second metal wire 32 is connected between the points 12. The height of each metal pillar 40 is higher than the height of the highest point of the second metal line 32 corresponding to the first redistribution layer 10.

In step (i) as shown in FIG. 2G, a second molding compound 52 is formed on the second surface 102 of the first redistribution layer 10 to cover the second chips 30 and the second metal wires 32 and the metal posts 40, one end of each metal post 40 is exposed on an outer surface 501 of the second sealing compound 52, that is, one end of each metal post 40 is connected to the outer surface 501 of the second sealing compound 52 Flush. That is, when the second molding compound 52 covers all the second metal wires 32, the metal pillar 40 is exposed on the outer surface 501 of the second molding compound 52.

As shown in step (j) of FIG. 2H, the second rewiring layer 60 is formed on the outer surface 501 of the second molding compound 52.

In step (k) as shown in FIG. 2H, bumps or solder balls 61 are formed on the plurality of external pads 603 on the second rewiring layer 60, respectively.

As can be seen from the first embodiment disclosed above, the metal pillars 40 can be directly formed on the third contact 13 before the second sealing compound 52 is formed, and then flush with the continuously formed second sealing compound 52.

Please refer to FIGS. 2-1A to 2-1D, a second embodiment of a double-sided stacked chip packaging method of the present invention; this embodiment is roughly the same as the first embodiment, except that shown in FIGS. 2C and 2D The illustrated process steps are replaced by FIGS. 2-1A to 2-1C, that is, as shown in FIG. 2-1A, the first metal contacts 21 of each first chip 20 are also wired and electrically connected to the corresponding The first contact 11, therefore, the first metal wire 22 is connected between each first metal contact 21 and the corresponding first contact 11; however, the height of each first metal wire is higher than the stacked ones. The height of the first chip 20; then a first encapsulant 51 is formed on the first surface 101 of the first redistribution layer 10 to cover the first chips 20 and the first metal wires 22; then . Next, as shown in FIG. 2-1B, grind the first molding compound 51 to a certain height, so that each of the first metal wires remains connected to the first straight line segment 221 of the first metal contact 21 of each first chip 20 , And connected to the second metal line segment 222 corresponding to the first contact 11; wherein the first and second upright line segments 221, 222 is perpendicular to the first chips 20 and the first redistribution layer 10, and the free ends of the first and second vertical line segments 221 and 222 are exposed outside the first sealing compound 51.

As shown in FIG. 2-1C, a third redistribution layer 62 is formed on the first encapsulant 51, and the first straight line segments 221 and the inner connecting lines 621 of the third redistribution layer 62 The second vertical line segments 222 are correspondingly connected to form a loop on the third redistribution layer 62, and the first metal contact 21 of each first chip 20 is electrically connected to the corresponding first connection through the third redistribution layer 62 Point 11. The next steps are as shown in FIGS. 2E to 2G of the first embodiment, and finally the double-sided stacked chip package structure shown in FIG. 2-1D is formed.

Please refer to FIG. 3A to FIG. 3D, which is a second embodiment of a double-sided stacked chip packaging manufacturing method of the present invention, which also includes steps (a) to (h) after the next steps, but Steps (a) to (e) and steps (a) to (e) of the first embodiment are shown in Figures 2A to 2D, so they will not be repeated here; the following further describes step (f) of this embodiment ) To step (k).

First, please refer to FIG. 2D. When the carrier 70 is separated from a second surface 102 of the first redistribution layer 10, the second surface 102 has a plurality of second contacts 12 and a plurality of third contacts 13 facing 3A, step (f) shown in FIG. 3A, a plurality of second chips 30 are sequentially partially stacked on the second surface 102 of the first redistribution layer 10, and each second chip 30 is The two metal contacts 31 and the plurality of second contacts 12 on the second surface 102 are exposed upward.

As shown in step (g) of FIG. 3A, the second metal contacts 31 of each second chip 30 are electrically connected to the corresponding second contacts 12, so that each second metal contact 31 corresponds to The second metal wire 32 is connected between the second contacts 12.

In step (h) as shown in FIG. 3A, a second molding compound 52 is formed on the second surface 102 of the first redistribution layer 10 to cover the second chips 30 and the second metal wires 32.

As shown in step (i) of FIG. 3B, through holes 521 are formed in the second sealing compound 52 corresponding to the positions of the third contacts 13, and then as shown in FIG. 3C, a through hole 521 is plated Metal pillar 40', so that one end of each metal post 40' is exposed on the outer surface 501 of the second sealant body 52, that is, is also flush with the outer surface 501 of the second sealant body 52.

As shown in step (j) in FIG. 3D, the second rewiring layer 60 is formed on the outer surface 501 of the second molding compound 52.

As shown in step (k) in FIG. 3D, bumps or solder balls 61 are formed on the plurality of external pads 603 of the second rewiring layer 60, respectively.

As can be seen from the second embodiment disclosed above, after the second sealing compound body 52 is formed, a plurality of through holes 521 can be opened in the second sealing compound body 52 and aligned with the third contact 13 so that the third The contact 13 is exposed, and then a metal pillar 40' is formed in the through hole 521 by electroplating.

In summary, the double-sided stacked chip packaging structure of the present invention is mainly used to package two sets of chips on both sides of the first redistribution layer, and a metal pillar is directly formed on one of the sides, and the metal pillar is electrically conductive The second redistribution layer connected to the outer surface of the second encapsulant; in this way, the double-sided stacked chip package structure of the present invention does not need to concentrate the first and second contacts of the first redistribution layer on one of the chips , Does not limit the number of stacked chips; the first and second embodiments of the packaging process method adopt the re-wiring priority process to directly form the first re-wiring layer on the carrier board without using pre-made and molded interposers , Has easy alignment, high flatness and better surface conditions; in addition, it further discloses the different forming methods of the metal pillars electrically connected to the first rewiring layer, which will not increase the difficulty of the manufacturing process and is easy to implement.

The above are only the embodiments of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field, Without departing from the scope of the technical solution of the present invention, when the technical content disclosed above can be used to make slight changes or modification into equivalent embodiments with equivalent changes, but any content that does not deviate from the technical solution of the present invention is based on the technical essence of the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solutions of the present invention.

10: The first heavy wiring layer

101: first surface

102: second surface

11: The first contact

12: second contact

13: Third contact

14: Dielectric body

15: Internal connection line

20: The first chip

21: The first metal contact

22: The first metal wire

30: second chip

31: The second metal contact

32: The second metal wire

40: metal column

50: sealant

501: outer surface

51: The first sealant

52: The second sealant

60: second wiring layer

601: Third Surface

602: Fourth Surface

603: external pad

61: tin ball

Claims (10)

A double-sided stacked chip packaging structure includes: A first redistribution layer has a first surface and a second surface. A plurality of first contacts are formed on the first surface, and a plurality of second contacts and a plurality of third contacts are formed on the second surface ； A plurality of first chips are partially stacked on the first surface of the first redistribution layer, each of the first chips has exposed first metal contacts, and each of the first metal contacts is electrically connected by a first metal wire To the first contact corresponding to the first surface; A plurality of second chips are partially stacked on the second surface of the first redistribution layer, each of the second chips has exposed second metal contacts, and each of the second metal contacts is electrically connected by a second metal wire To the second contact corresponding to the second surface; A plurality of metal pillars, the common ends of which are respectively electrically connected to the third contact on the second surface of the first redistribution layer, and the height of each metal pillar is higher than the height of the second metal wires; A first molding compound formed on the first surface of the first redistribution layer to cover the first chip set and the first metal wires; A second molding compound is formed on the second surface of the first redistribution layer to cover the second chip set, the second metal lines, and the metal pillars; wherein the metal pillars share another One end is exposed on an outer surface of the second sealing compound; and A second redistribution layer has a third surface formed on the outer surface of the second encapsulant body and electrically connected to the exposed side of the metal pillars, and a fourth surface is formed with a plurality of external pads. According to the double-sided stacked chip package structure of claim 1, the first circuit redistribution layer is formed with a plurality of internal connection lines in a dielectric body to connect with the first contacts and the second contacts Point electrical connection. In the double-sided stacked chip package structure described in claim 1 or 2, the external pads are formed with bumps or solder balls, respectively. A method for manufacturing a double-sided stacked chip packaging structure includes the following steps: (a) Prepare a carrier board on which a first redistribution layer is formed; (b) A plurality of first chips are sequentially partially stacked on a first surface of the first redistribution layer, and the first metal contacts of each first chip and the plurality of first contacts on the first surface Exposed (c) Wire each of the first metal contacts to the corresponding first contact, so that a first metal wire is connected between each of the first metal contacts and the corresponding first contact; (d) forming a first molding compound on the first surface of the first redistribution layer to cover the first chips and the first metal wires; (e) After reversing the carrier board, the carrier board is separated from a second surface of the first redistribution layer, so that the plurality of second contacts and the plurality of third contacts of the second surface are exposed; (f) A metal pillar is respectively formed on the exposed third contacts; (g) A plurality of second chips are sequentially partially stacked on the second surface of the first redistribution layer, and the second metal contacts of each second chip and the plurality of second contacts on the second surface Exposed (h) Wire each of the second metal contacts to the corresponding second contacts; (i) A second molding compound is formed on the second surface of the first redistribution layer to cover the second chips, the second metal wires and the metal pillars, one end of each metal pillar Is exposed on an outer surface of the second sealing compound; (j) A second rewiring layer is formed on the outer surface of the molding compound; and (k) A plurality of external pads are formed on the second rewiring layer. The manufacturing method of the double-sided stacked chip package structure as described in claim 4, wherein: The height of the first metal wires in the above step (c) is higher than the height of the first chips after stacking; and The above step (d) further includes the following steps after forming the first sealing compound: (d1) Grind the first sealing compound to a certain height so that each of the first metal wires retains the first straight line segment connected to the first metal contact of each first chip, and connects the second metal corresponding to the first contact Line segments; wherein the first straight lines are perpendicular to the corresponding first chip, and the second second metal line segments are perpendicular to the first redistribution layer, and the free ends of the first and second upright line segments Is exposed to the first sealant; and (d2) A third redistribution layer is formed on the first encapsulant, and the first vertical line segments and the second vertical line segments are correspondingly connected through the inner connecting lines of the third redistribution layer. According to the manufacturing method of the double-sided stacked chip package structure described in claim 5, in the above step (k), the external pads are further formed with bumps or solder balls, respectively. According to the manufacturing method of the double-sided stacked chip package structure of claim 5 or 6, in the above step (a), the first rewiring layer is formed on the carrier board with the second contacts and the first Three contacts, a dielectric body, a plurality of internal connecting lines and the first contacts. A method for manufacturing a double-sided stacked chip packaging structure includes the following steps: (a) Prepare a carrier board on which a first redistribution layer is formed; (b) A plurality of first chips are sequentially partially stacked on a first surface of the first redistribution layer, and the first metal contacts of each first chip and the plurality of first contacts on the first surface Exposed (c) Wire each of the first metal contacts to the corresponding first contacts; (d) forming a first molding compound on the first surface of the first redistribution layer to cover the first chips and the first metal wires; (e) After reversing the carrier board, the carrier board is separated from a second surface of the first redistribution layer, so that the plurality of second contacts and the plurality of third contacts of the second surface are exposed; (f) A plurality of second chips are sequentially partially stacked on the second surface of the first redistribution layer, and the second metal contacts of each second chip and the plurality of second contacts on the second surface Exposed (g) Wire each of the second metal contacts to the corresponding second contacts; (h) forming a second molding compound on the second surface of the first redistribution layer to cover the second chips and the second metal wires; (i) A through hole is formed in the second sealing compound body corresponding to each of the third contacts, and a metal pillar is plated in each through hole, so that one end of each metal pillar is exposed to the second sealing body An outer surface; (j) A second rewiring layer is formed on the outer surface of the molding compound; and (k) A plurality of external pads are formed on the second rewiring layer. According to the manufacturing method of the double-sided stacked chip package structure described in claim 8, in the above step (k), the external pads are further formed with bumps or solder balls, respectively. According to the method for manufacturing a double-sided stacked chip package structure according to claim 8 or 9, in the above step (a), the first rewiring layer is formed on the carrier board with the second contacts and the first Three contacts, a dielectric body, a plurality of internal connecting lines and the first contacts.

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