CN108630717A - 微led显示组件 - Google Patents
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Abstract
本发明涉及微LED显示组件。本公开涉及半导体结构，更具体地，涉及一种微LED显示组件及其制造方法。该结构包括插入件和多个微LED阵列，每个微LED阵列包括将多个微LED阵列的像素连接到插入件的多个通孔。
Description
技术领域
本公开涉及半导体结构，更具体地，涉及一种微LED显示组件及其制造方法。
背景技术
无机发光二极管(ILED)是由半导体材料制成的发光二极管。可以使用ILED产生各种不同的颜色，其包括红色，绿色，黄色和蓝色。在操作中，当正向偏置电压被施加到半导体材料的P-N结时，ILED发光。
用于显示系统的LED器件需要在大表面上的高像素设置密度。然而，用于LED的传统制造方法对于满足产量要求是具有挑战性的，特别是对于较大的显示尺寸。此外，由于差的晶片面积利用，更高的成本与下一代显示器相联系。对于后一点，用于大型LED显示器和图像传感器阵列的单个管芯的使用在部分场区域中留下在晶片边缘周围的显著未使用空间。
发明内容
在本公开的方面中，一种结构包括：插入件(interposer)；以及多个微LED阵列，每个微LED阵列包括将所述多个微LED阵列的像素连接到所述插入件的多个通孔。
在本公开的方面中，一种结构包括：插入件，其包括多个通孔；多个微LED阵列，每个微LED阵列包括连接到所述多个微LED阵列的每个像素的多个通孔；以及后段制程插入件，包括将所述像素的每个的所述通孔连接到所述插入件的所述通孔的布线结构。
在本公开的一方面，一种方法包括：在衬底中形成连接到微LED阵列的像素的多个通孔；以及将多个微LED阵列中的每一个的所述像素连接到单个插入件，其中所述通孔与所述插入件的连接对准。
附图说明
在下面的详细描述中，通过本公开的示例性实施例的非限制性示例参考所述多个附图来描述本公开。
图1示出了根据本公开的方面的像素设计。
图2示出了根据本公开的一个方面的微LED组件及其制造工艺的横截面图。
图3示出了根据本公开的方面的替代结构和各自的制造工艺。
图4示出了根据本公开的方面的微LED显示组件的横截面图。
图5示出了根据本公开的方面的微LED显示组件的透视图。
图6示出了根据本公开的方面的制造工艺的流程图。
具体实施方式
本公开涉及半导体结构，更具体地，涉及一种微LED显示组件及其制造方法。更具体地说，本公开内容涉及一种微LED显示组件，该微LED显示组件由在使用硅通孔技术的较大的阵列中设置的多个小型微LED阵列组成。也就是，微LED显示组件使用以阵列设置的多个小管芯来代替一个大阵列。微LED显示组件可用于例如2.5D和3D技术。
在实施例中，每个小型微LED阵列包括用于安装到衬底上以形成较大显示组件的硅通孔(TSV)技术。在实施例中，TSV连接到每个单独的微LED，例如像素。可以使用硅或玻璃插入件或直接地将TSV微LED阵列器件连接到像素驱动器。在实施例中，硅插入件允许像素驱动电路的直接集成；而玻璃插入件将需要单独的像素驱动器。在实施例中，多个小型微LED阵列提供到每个TSV/微LED连接的高密度布线。
有利地，与使用单个更大的像素阵列相比，微LED显示组件为大显示尺寸提供了改善的(例如，高的)产量。这是由于可以组装几个小管芯以共同形成较大的LED阵列，而不是单个大管芯。更具体地，如果在单个大管芯上发现故障，则整个管芯将需要被丢弃；而如本文所公开的，如果在较小的管芯上发现单个故障，则仅需要丢弃该单个更小的管芯。这将显着降低成本并提高产量，因为在像素故障时丢弃较小的管芯更便宜。
此外，通过更有效地利用晶片上的空间，可以显着降低制造成本。例如，通过使用较小的管芯，现在可以更有效地利用晶片边缘周围的未使用的空间。此外，本文所述的微LED显示组件通过使用用作板和微LED管芯之间的应力缓冲的插入件来提供改善的可靠性。
本公开的微LED显示组件可以使用许多不同的工具以多种方式制造。通常，方法和工具用于形成尺寸在微米和纳米级的结构。用于制造本公开的微LED显示组件的方法，即技术，已经从集成电路(IC)技术中被采用。例如，微LED显示组件构建在晶片上，并且以通过在晶片顶部上的光刻工艺而图案化的材料膜实现。特别地，晶片接合衬垫结构的制造使用三个基本构造块：(i)在衬底上沉积材料薄膜，(ii)通过光刻成像在膜的顶部上施加图案化掩模，以及(iii)将膜选择性地蚀刻到掩模。
图1示出了根据本公开的方面在微LED组件中使用的单个像素。本领域的技术人员应该理解，图1(和本文所描述的其它图)还可以表示用于任何可重复设计结构(例如存储单元阵列等)的布局图案。如图1所示，像素10包括具有四个子像素14a-14d的接触板或电极12。在实施例中，接触板或电极12可以是由不透明材料(例如金属)组成的纳米线接触和反射器板，例如以使最大化从子像素14a-14d发射的光。
在实施例中，像素10具有6.35μm×6.35μm的尺寸，子像素14a-14d具有3.175μm×3.175μm的尺寸，尽管这里也考虑了其他尺寸。如本领域技术人员应当理解的，根据本公开的方面，这些像素10中的多个可以形成在单个微LED组件上。例如，这里实现的微LED组件可以包括1000个像素×1000个像素，尽管这里还考虑到取决于组装技术或工具的其它像素数量。
仍然参考图1，在一个说明性示例中，子像素14a-14d包括在无机发光二极管(ILED)中使用的RGB像素设计。在实施例中，子像素14a-14d中的每一个可以具有由用以发射一定的颜色(例如，波长)的不同材料组成的不同数量的纳米线16。作为非限制性示例，(i)对于绿光，存在用于子像素14a、14d的四个纳米线16，(ii)对于蓝光，存在用于子像素14b的九个纳米线16，以及(iii)对于红光，存在用于子像素14c的四个纳米线16。尽管子像素14d被示为对子像素14a是冗余的，但是应当理解，子像素14d对于子像素14a-14c中的任一个可以是冗余的。或者，子像素14d可以是留空的，例如没有任何纳米线。
虽然对于本公开的理解不是关键的，但是纳米线16可以由不同的材料组成以便提供不同的波长。例如，下表1示出了可用于纳米线的半导体材料的示例性组合。
图2示出了根据本公开的一个方面的微LED组件及其制造工艺的横截面图。如图2所示，微LED组件20包括各自具有多个纳米线16的子像素14a、14b。在所示的示例中，微LED组件20的截面图示出了用于每一个像素10a、10b的子像素14a、14b。
如图2进一步所示，微LED组件20还包括具有多个TSV 24的衬底22，该多个TSV 24连接到与每个像素10a、10b(例如，子像素14a、14b)电连接的金属衬垫26(例如铜衬垫)。如图所示，为每个像素使用单个TSV 24，TSV 24的直径约为1/2像素栅距(pitch)。例如，在说明性实施例中，对于具有约6μm的栅距的像素，TSV 24可以具有大约小于3μm的直径/宽度，尽管用较薄的管芯时较小的尺寸是可以的。在实施例中，衬垫26可以与pGaN子像素14a、14b直接电连通，所有像素共享均厚(blanket)nGaN连接28，反之亦然。在该表示中，衬垫26a和TSV 24a可以连接到导电端子层30。以这种方式，对于每个像素，不需要具有单独的TSV或导电端子。
图3示出了根据本公开的方面的替代结构和相应的制造方法。在这种结构中，像素10被示意性地表示为由多个层100a-100f组成的叠层结构，每个层100a-100f连接到形成在基板22中的TSV 24。在实施例中，这些层包括：nGaN 100a、InGaN 100b、pGaN 100c、端子层100d、含磷(phosphorous)层100e和滤色器100f。应当认识到，这些层被提供作为说明性示例，并且不应被认为是本公开的限制特征。为了简化说明，未示出布线到单独的TSV的公共pGaN端子。
在图2和图3的每个表示中，ILED晶片被分开形成，然后接合到TSV载体晶片(例如，晶片22)。此外，TSV 24可以通过常规的背侧研磨方法，然后进行用以形成过孔的深Si蚀刻(例如Bosch蚀刻)而形成，其中该过孔与形成在晶片的前侧上(以及与像素电接触)的衬垫对准并暴露该衬垫。然后，用介电衬里(例如，诸如SiO2的无机材料)涂覆过孔。在实施例中，介电衬里将被沉积到约200nm的厚度，尽管本文考虑了其它厚度。可以在介电衬里之上形成阻挡金属，例如Ta或TiN，以防止Cu扩散到氧化物和晶片中。种子层可以溅射到阻挡金属上，随后进行电镀工艺，例如Cu电镀工艺。可以通过化学机械抛光步骤除去任何残留的材料。应当理解，附图标记24表示通孔本身内的不同材料。
图4示出了根据本公开的方面的微LED显示组件的截面图。更具体地说，图4示出了安装在插入件30上的多个微LED组件20。在实施例中，插入件30可以是由集成ILED像素驱动器电路构成的Si插入件。在替代实施例中，插入件30可以是玻璃插入件或有源管芯。在实施例中，如本文进一步描述的，多个微LED组件20(例如，包含TSV互连的至少两个ILED管芯)以等间距放置在插入件30上。
后段制程(BEOL)布线35被设置(例如，接合)在多个微LED组件20和插入件30之间。在实施例中，BEOL布线35包括将多个微LED组件20中的像素10的每个电连接到插入件30的布线结构(wiring scheme)。更具体地，每个微LED组件20的每个像素的每个TSV 24连接到微柱互连45，微柱互连45进而连接到BEOL布线35的布线结构。在实施例中，微柱互连45的栅距将匹配TSV 24，例如5-10μm栅距。如本领域技术人员应该理解的那样，微柱互连45可以是常规的可控塌陷芯片连接(C4)焊料互连。在替代实施例中，多个微LED组件20可以整体接合到BEOL布线35。
仍然参考图4，BEOL布线35的布线结构被连接到插入件30的多个TSV 50。插入件30的TSV 50可以以与针对微LED组件20的每个像素的TSV 24相同的方式制造。在连接插入件30的多个TSV 50时，在实施例中，跨管芯像素栅距/间隔“X”优选地等于管芯内像素栅距/间隔“X”，以便不会干扰整体像素阵列的观看。在另外的实施例中，插入件30包括与插入件30的TSV 50电接触的焊料连接55。以这种方式，焊料连接55提供用于微LED组件20的外部互连。
图5示出了根据本公开的方面的微LED显示组件的透视图。更具体地说，图5示出了安装在插入件30上的多个微LED组件20。在实施例中，多个微LED组件20，例如至少两个ILED管芯，每个包含在插入件30上以相等间隔设置、具有TSV互连的多个LED像素10。BEOL插入件35位于多个微LED组件20和插入件30之间。插入件30包括焊料连接55以提供用于微LED组件20的外部互连。
图6示出了根据本公开的方面的制造方法的流程图。特别地，为了制造图2-5所示的结构，在步骤600，使用常规CMOS制造方法在晶片上制造LED器件，例如像素10。在步骤605，将晶片翻转并进行背面研磨方法。在实施例中，背面研磨方法可将晶片(例如Si)减薄至约50微米。在步骤610，晶片的背面然后经历深Si蚀刻，例如Bosch蚀刻，以形成过孔，该过孔与形成在晶片前侧(且与像素电接触)的衬垫对准并暴露的该衬垫。在步骤615，在过孔中形成介电衬里。介电衬里可以是例如有机旋涂材料(SiCOH)或聚酰亚胺材料。在实施例中，介电衬里将被沉积到约200nm的厚度。在步骤620，可以在介电衬里之上形成阻挡金属，以防止Cu扩散到氧化物和晶片中。在实施例中，阻挡金属可以是通过溅射化学气相沉积方法沉积的Ta或TiN。在步骤625，执行电镀工艺。例如，将种子层溅射到阻挡金属上，然后使用电镀工艺(例如Cu电镀工艺)填充过孔。在步骤630，可以通过化学机械抛光(CMP)方法从晶片的背面去除任何残留材料。在步骤635，形成与TSV的金属材料直接电连接的互连。作为示例，在步骤640，通过例如将每个微LED阵列连接到插入件，将微LED阵列组装成较大的阵列。
如上所述的方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原料晶片形式(即，作为具有多个未封装芯片的单个晶片)作为裸芯片或以封装形式分发。在后一种情况下，芯片安装在单个芯片封装(例如塑料载体中，其中引线固定到主板或其它更高级别的载体)或多芯片封装(例如陶瓷载体，其具有任一或两者表面互连或掩埋互连)。在任何情况下，芯片然后与其他芯片、分立电路元件和/或其他信号处理设备集成，作为(a)中间产品(例如主板)或(b)终端产品的一部分。最终产品可以是包括集成电路芯片的任何产品，范围从玩具和其他低端应用到具有显示器、键盘或其他输入设备以及中央处理器的高级计算机产品。
已经出于说明的目的呈现了本公开的各种实施例的描述，但并不旨在穷尽或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。选择这里使用的术语是为了最好地解释实施例的原理、对市场中发现的技术的实际应用或技术改进，或使本领域普通技术人员能够理解本文公开的实施例。
Claims (20)
1.一种结构，包括：
插入件；以及
多个微LED阵列，每个微LED阵列包括将所述多个微LED阵列的像素连接到所述插入件的多个通孔。
2.根据权利要求1所述的结构，其中所述插入件是具有驱动器电路的硅插入件。
3.根据权利要求1所述的结构，其中所述插入件是玻璃插入件。
4.根据权利要求1所述的结构，其中所述通孔是硅通孔技术。
5.根据权利要求4所述的结构，其中每个所述像素通过单独的硅过孔技术连接到所述插入件。
6.根据权利要求1所述的结构，其中所述像素由GaN构成，并且所述通孔是与所述像素集成到相同管芯中的铜硅通孔。
7.根据权利要求1所述的结构，其中所述通孔通过与所述通孔的栅距相匹配的微柱连接到所述插入件。
8.根据权利要求1所述的结构，其中所述多个微LED阵列在所述插入件上等间距地间隔开。
9.根据权利要求8所述的结构，其中跨管芯像素栅距/间隔等于所述多个微LED阵列的每一个内的像素栅距/间隔。
10.根据权利要求1所述的结构，其中所述通孔的直径大约为像素栅距的1/2。
11.一种结构，包括：
插入件，其包括多个通孔；
多个微LED阵列，每个微LED阵列包括连接到所述多个微LED阵列的每个像素的多个通孔；以及
后段制程插入件，包括将所述像素的每个的所述通孔连接到所述插入件的所述通孔的布线结构。
12.根据权利要求11所述的结构，其中：
所述多个微LED阵列等间距地间隔开；以及
跨管芯像素栅距/间隔等于所述多个微LED阵列的每一个内的像素栅距/间隔。
13.根据权利要求12所述的结构，其中所述像素由GaN构成，并且所述通孔是与所述像素集成到相同管芯中的铜硅通孔。
14.根据权利要求13所述的结构，其中所述硅通孔通过微柱连接到所述插入件的后端。
15.根据权利要求14所述的结构，其中所述微柱是焊料连接。
16.根据权利要求14所述的结构，其中所述微柱匹配所述硅通孔的栅距。
17.根据权利要求13所述的结构，其中每个通孔的直径大约为像素栅距的1/2。
18.根据权利要求11所述的结构，其中所述插入件是具有驱动器电路的硅插入件。
19.根据权利要求11所述的结构，其中所述插入件是玻璃插入件。
20.一种方法，包括：
在衬底中形成连接到微LED阵列的像素的多个通孔；以及
将多个微LED阵列中的每一个的所述像素连接到单个插入件，其中所述通孔与所述插入件的连接对准。
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- 2017-06-16 TW TW106120184A patent/TWI691046B/zh active
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| WO2021073288A1 (zh) * | 2019-10-16 | 2021-04-22 | 福州大学 | 一种基于纳米线的μLED显示设计方法 |
| WO2024103223A1 (en) * | 2022-11-14 | 2024-05-23 | Caspol Visual Technologies Limited | Display panel and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
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| TW201839952A (zh) | 2018-11-01 |
| US20180269191A1 (en) | 2018-09-20 |
| CN108630717B (zh) | 2023-02-21 |
| US10770440B2 (en) | 2020-09-08 |
| TWI691046B (zh) | 2020-04-11 |
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