TWI683114B - 顯示面板 - Google Patents

顯示面板 Download PDF

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Publication number
TWI683114B
TWI683114B TW107142535A TW107142535A TWI683114B TW I683114 B TWI683114 B TW I683114B TW 107142535 A TW107142535 A TW 107142535A TW 107142535 A TW107142535 A TW 107142535A TW I683114 B TWI683114 B TW I683114B
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Taiwan
Prior art keywords
electrically coupled
test pad
terminal
pixel circuits
switch circuit
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TW107142535A
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English (en)
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TW202020466A (zh
Inventor
陳奕冏
張翔昇
鄭貿薰
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友達光電股份有限公司
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Priority to TW107142535A priority Critical patent/TWI683114B/zh
Priority to CN201910092082.XA priority patent/CN109559687B/zh
Priority to US16/677,757 priority patent/US20200168140A1/en
Application granted granted Critical
Publication of TWI683114B publication Critical patent/TWI683114B/zh
Publication of TW202020466A publication Critical patent/TW202020466A/zh

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    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一種顯示面板具有主動區以及周邊區。顯示面板包含N條閘極線、N個移位暫存器、複數個畫素電路、開關電路以及複數個測試墊。開關電路設置於周邊區,且電性耦接至N個移位暫存器、N條閘極線及畫素電路,用以接收控制訊號以及致能訊號並將N條閘極線的電壓位準下拉至低位準。測試墊設置於周邊區,且電性耦接至開關電路以及畫素電路,用以提供控制訊號、致能訊號、資料訊號以及參考訊號。

Description

顯示面板
本揭示文件有關一種顯示面板,尤指一種用於測試階段燒機的顯示面板。
有機發光二極體(Organic light emitting diode,AMOLED)的顯示面板,為了提升顯示品質,在製造過程中通常需要經過燒機(Burn in)、組裝測試(Cell test)以及晶片覆膜(IC bonding)等測試階段。在目前的面板檢測機制中,通常需要針對個別的有機發光二極體提供檢測訊號,並且在檢測完畢後,會將測試接腳切斷使得顯示面板可以進行後續的顯示功能。然而,現有的測試機制在與顯示面板斷開後,如果顯示面板還需要後續的檢測時,無法有效地再度透過檢測機制重新進行檢測,造成後續的不便。
本發明提供一種顯示面板,其主要係利用畫素電路中有機發光二極體陽極端的重置電路架構,再結合額外的開關電路,在測試階段時可以致能開關電路,利用電源供應器經由測試墊輸入所需的電流,直接點亮有機發光 二極體,不需要額外的Burn-in治具。在出廠後的顯示階段,禁能開關電路,仍然可以達到原本重置有機發光二極體陽極端的功能,達到節省製造成本並且有效監控顯示面板元件的功效。
本案之一實施態樣是在提供一種顯示面板,顯示面板具有主動區以及周邊區,周邊區設置於主動區的一側,顯示面板包含N條閘極線、N個移位暫存器、複數個畫素電路、開關電路以及複數個測試墊,其中N為正整數。N個移位暫存器設置於周邊區,且電性耦接至N條閘極線,用以輸出閘極訊號。複數個畫素電路設置於主動區,且電性耦接至N條閘極線,用以接收閘極訊號、資料訊號以及參考訊號。開關電路設置於周邊區,且電性耦接至N個移位暫存器、N條閘極線及畫素電路,用以接收控制訊號以及致能訊號並將N條閘極線的電壓位準下拉至低位準。複數個測試墊設置於周邊區,且電性耦接至開關電路以及畫素電路,用以提供控制訊號、致能訊號、資料訊號以及參考訊號。
本揭露之顯示面板主要係利用畫素電路中有機發光二極體陽極端的重置電路架構,再結合額外的開關電路,在測試階段時可以致能開關電路,利用電源供應器經由測試墊輸入所需的電流,直接點亮有機發光二極體,不需要額外的Burn-in治具,達到節省製造成本並且有效監控顯示面板元件的功效。
100、300、400、500‧‧‧顯示裝置
110‧‧‧移位暫存器
120‧‧‧畫素電路
121‧‧‧驅動電路
1211‧‧‧寫入電路
1212‧‧‧補償電路
1213‧‧‧驅動電晶體
122‧‧‧測試開關
130‧‧‧開關電路
130_1~130_N‧‧‧開關
140~147‧‧‧測試墊
GL[1]~GL[N]‧‧‧閘極線
Scan[1]~Scan[N]‧‧‧閘極訊號
AA‧‧‧主動區
PA‧‧‧周邊區
CTL‧‧‧畫素控制訊號
SW1‧‧‧致能訊號
SW2‧‧‧控制訊號
VS、VR、VG、VB、VOLED‧‧‧資料訊號
OVSS‧‧‧參考訊號
OVDD‧‧‧電源高電壓
Vref‧‧‧參考低電壓
Vdata‧‧‧資料電壓
S1~S3‧‧‧掃描訊號
T1~T8‧‧‧電晶體
C1‧‧‧電容
OLED‧‧‧發光二極體
為讓揭示文件之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖為根據本揭示文件一實施例的顯示裝置的示意圖;第2圖為根據本揭示文件一實施例的畫素電路的電路圖;第3圖為根據本揭示文件另一實施例的顯示面板的示意圖;第4圖為根據本揭示文件另一實施例的顯示面板的示意圖;以及第5圖為根據本揭示文件另一實施例的顯示面板的示意圖。
以下將配合相關圖式來說明本發明的實施例。在圖式中,相同的標號表示相同或類似的元件或方法流程。
請參閱第1圖。第1圖為根據本揭示文件一實施例的顯示面板100的示意圖。如第1圖所繪示,顯示面板100具有主動區AA以及周邊區PA,周邊區PA設置於主動區AA的一側。顯示面板100包含N條閘極線GL[1]~GL[N]、N個移位暫存器110、複數個畫素電路120、開關電路130以及複數個測試墊140,其中N為正整數。N個移位暫存器110設置於周邊區PA,且N個移位暫存器110電性耦接至N條閘極線GL[1]~GL[N],N個移位暫存器110用以輸出閘極訊 號Scan[1]~Scan[N]。畫素電路120設置於主動區AA,且電性耦接至N條閘極線GL[1]~GL[N],畫素電路120用以接收閘極訊號Scan[1]~Scan[N]、資料訊號VS以及參考訊號OVSS。
承上述,開關電路130設置於周邊區PA,且電性耦接至N個移位暫存器110、N條閘極線GL[1]~GL[N]及畫素電路120,開關電路130用以接收控制訊號SW2以及致能訊號SW1並將N條閘極線GL[1]~GL[N]的電壓位準下拉至低位準。測試墊140設置於周邊區PA,且電性耦接至開關電路130以及畫素電路120,測試墊140用以提供控制訊號SW2、致能訊號SW1、資料訊號VS以及參考訊號OVSS。其中,資料訊號VS包含第一資料訊號VR、第二資料訊號VG以及第三資料訊號VB。
請繼續參考第1圖,測試墊140包含第一測試墊141、第二測試墊142、第三測試墊143、第四測試墊144、第五測試墊145以及第六測試墊146。第一測試墊141電性耦接至畫素電路120,用以提供參考訊號OVSS至畫素電路120。第二測試墊142電性耦接至開關電路130,用以提供控制訊號SW2至開關電路130。第三測試墊143電性耦接至開關電路130,用以提供致能訊號SW1至開關電路130。第四測試墊144電性耦接至畫素電路120,用以提供第一資料訊號VR至畫素電路120。第五測試墊145電性耦接至畫素電路120,用以提供第二資料訊號VG至畫素電路120。第六測試墊146電性耦接至畫素電路120,用以提供第三資料訊 號VB至畫素電路120。
進一步參考第2圖,第2圖為根據本揭示文件一實施例的畫素電路120的電路圖。如第2圖所繪示,畫素電路120係為8個電晶體1個電容(8T1C)的架構,此畫素電路120為習知的畫素電路架構。畫素電路120包含驅動電路121、測試開關122以及發光二極體OLED。驅動電路121包含寫入電路1211、補償電路1212以及驅動電晶體1213。在本揭露的畫素電路120中,測試開關122會在測試階段時作動,但在顯示階段時則是作為畫素電路120的重置電晶體T7使用,用以重置發光二極體OLED的陽極端。
承上述,寫入電路1211包含電晶體T1及T2以及電容C1,寫入電路1211用以接收畫素控制訊號CTL、掃描訊號S3、參考低電壓Vref以及資料電壓Vdata。補償電路1212包含電晶體T3、T4、T5及T6,補償電路1212用以接收畫素控制訊號CTL、掃描訊號S1及S3以及參考低電壓Vref並產生補償電壓。驅動電晶體1213包含電晶體T8,用以接收電源高電壓OVDD,用以產生流經發光二極體OLED的驅動電流Id。重置電晶體T7用以接收掃描訊號S2並重置驅動電路1213的電壓位準。
請一併參閱第1圖及第2圖。發光二極體OLED的第一端電性耦接至驅動電路121,發光二極體OLED的第二端電性耦接至第一測試墊141。測試開關122的第一端電性耦接至發光二極體OLED的第一端,測試開關122的第二端電性耦接至第四測試墊144、第五測試墊145以及第六測 試墊146的其中之一,測試開關122的控制端電性耦接至N條閘極線GL[1]~GL[N]的其中之一。
如第1圖所示,開關電路130包含N個開關130_1~130_N,N個開關彼此依序串聯。舉例而言,第1個開關130_1的第一端電性耦接至第1條閘極線GL[1],第1個開關130_1的第二端電性耦接至第2條閘極線GL[2],第1個開關130_1的控制端電性耦接至第二測試墊142。第2個開關130_2的第一端電性耦接至第2條閘極線GL[2],第2個開關130_2的第二端電性耦接至第3條閘極線GL[3],第2個開關130_2的控制端電性耦接至第二測試墊142。由上述可知,第1個開關130_1至第N-1個130_N-1電性耦接在當級閘極線以及下一級閘極線之間,除了第N個開關130_N以外,第N個開關130_N的第一端電性耦接至第N條閘極線GL[N],第N個開關130_N的第二端電性耦接至第三測試墊143,第N個開關130_N的控制端電性耦接至第二測試墊142。
承上述,第二測試墊142輸出的控制訊號SW2具有第一低電壓,因此會致能N個開關130_1~130_N,由於第N個開關130_N的第二端電性耦接至第三測試墊143,由第三測試墊143輸入的致能訊號SW1具有第二低電壓,因此N個開關130_1~130_N可以將閘極訊號Scan[1]~Scan[N]拉低至第二低電壓,以致能畫素電路120中的測試開關122,使得資料訊號VS可以輸入畫素電路120,點亮發光二極體OLED。其中第一低電壓小於第二低電壓,並且 第一低電壓與第二低電壓之間的位準差至少需要大於開關電路130中的開關的臨界電壓。
承上述,在一般的顯示階段,第二測試墊142輸出的控制訊號SW2會切換至高電壓,因此會禁能N個開關130_1~130_N,使得開關電路130不會作動,畫素電路120的測試開關122則轉換成重置電晶體T7的操作,用以重置發光二極體OLED的陽極端,畫素電路120可以根據源極驅動電路(圖未示)的資料電壓進行顯示。
於此實施例中,開關電路130的N個電晶體可以利用N型的電晶體來實現,但本實施例並不以此為限,於本揭露中也可以用P型電晶體,配合的致能位準切換為正電壓來實現。
請再參考第1圖,於此實施例中,根據第四測試墊144、第五測試墊145以及第六測試墊146將畫素電路120分成為三個群組,第一群組的畫素電路120的測試開關122接電性耦接至第四測試墊144,並接收第一資料訊號VR。第二群組的畫素電路120的測試開關122接電性耦接至第五測試墊145,並接收第二資料訊號VG。第三群組的畫素電路120的測試開關122接電性耦接至第六測試墊146,並接收第三資料訊號VB。
接著,請參考第3圖,第3圖為根據本揭示文件另一實施例的顯示面板300的示意圖。如第3圖所繪示,第3圖所示的實施例與第1圖所示的實施例差異在於,第3圖所示的開關電路130僅包含N-1個開關130_1~130_N-1,第3 圖所示的開關電路130的操作方式與第1圖所示的開關電路130相同,當控制訊號SW2致能開關電路130時,致能訊號SW1用以將閘極訊號Scan[1]~Scan[N]拉低至第二低電壓,以致能畫素電路120中的測試開關122。第3圖所示的開關電路130的第N-1個開關130_N-1的第一端電性耦接至第N-1條閘極線GL[N-1],第N-1個開關130_N-1的第二端電性耦接至第N條閘極線GL[N],第N-1個開關130_N-1的控制端電性耦接至第二測試墊142。於此實施例中,缺少第N個開關130_N的用處在於,可以透過第三試墊143測試第N條閘極線GL[N]的閘極訊號Scan[N],不需要再額外接出一個測試墊測試閘極訊號。
請參閱第4圖。第4圖為根據本揭示文件另一實施例的顯示面板400的示意圖。如第4圖所繪示,第4圖所示的實施例與第1圖所示的實施例差異在於,第4圖所示的測試墊140包含第一測試墊141、第二測試墊142、第三測試墊143、第七測試墊147。第一測試墊141電性耦接至畫素電路120,用以提供參考訊號OVSS至畫素電路120。第二測試墊142電性耦接至開關電路130,用以提供控制訊號SW2至開關電路130。第三測試墊143電性耦接至開關電路130,用以提供致能訊號SW1至開關電路130。第七測試墊147電性耦接至畫素電路120,用以提供資料訊號VOLED至畫素電路120。第4圖所示的實施例與第1圖所示的實施例差異在於,第1圖所示的畫素電路120分成三個群組,並且分別電性耦接至第四測試墊144、第五測試墊145以及第六 測試墊146。第4圖所示的畫素電路120的測試開關122的第二端皆電性耦接至第七測試墊147,於第4圖所示的實施例中,畫素電路120只會接收到第七測試墊147提供的資料訊號VOLED,因此在測試時無法像第1圖所示的實施例可以同時輸入三個不同的電壓位準(第一資料訊號VR、第二資料訊號VG及第三資料訊號VB),點亮發光二極體OLED。
請參閱第5圖。第5圖為根據本揭示文件另一實施例的顯示面板500的示意圖。如第5圖所繪示,第5圖所示的實施例與第4圖所示的實施例差異在於,第5圖所示的開關電路130僅包含N-1個開關130_1~130_N-1,第5圖所示的開關電路130的操作方式與第3圖所示的開關電路130相同,在此不再贅述。
綜上所述,本揭露之顯示面板主要係利用畫素電路中有機發光二極體陽極端的重置電路架構,再結合額外的開關電路,在測試階段時可以致能開關電路,利用電源供應器經由測試墊輸入所需的電流,直接點亮有機發光二極體,不需要額外的Burn-in治具。在出廠後的顯示階段,禁能開關電路,仍然可以達到原本重置有機發光二極體陽極端的功能,達到節省製造成本並且有效監控顯示面板元件的功效。
在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件。然而,所屬技術領域中具有通常知識者應可理解,同樣的元件可能會用不同的名詞來稱呼。說明書及申請專利範圍並不以名稱的差異做為區分元件的方 式,而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍所提及的「包含」為開放式的用語,故應解釋成「包含但不限定於」。另外,「耦接」在此包含任何直接及間接的連接手段。因此,若文中描述第一元件耦接於第二元件,則代表第一元件可通過電性連接或無線傳輸、光學傳輸等信號連接方式而直接地連接於第二元件,或者通過其他元件或連接手段間接地電性或信號連接至該第二元件。
另外,除非說明書中特別指明,否則任何單數格的用語都同時包含複數格的涵義。
以上僅為本發明的較佳實施例,凡依本發明請求項所做的均等變化與修飾,皆應屬本發明的涵蓋範圍。
100‧‧‧顯示裝置
110‧‧‧移位暫存器
120‧‧‧畫素電路
121‧‧‧驅動電路
122‧‧‧測試開關
130‧‧‧開關電路
130_1~130_N‧‧‧開關
140~146‧‧‧測試墊
GL[1]~GL[N]‧‧‧閘極線
Scan[1]~Scan[N]‧‧‧閘極訊號
AA‧‧‧主動區
PA‧‧‧周邊區
SW1‧‧‧致能訊號
SW2‧‧‧控制訊號
VS、VR、VG、VB‧‧‧資料訊號
OVSS‧‧‧參考訊號
OLED‧‧‧發光二極體

Claims (10)

  1. 一種顯示面板,該顯示面板具有一主動區以及一周邊區,該周邊區設置於該主動區的一側,該顯示面板包含:N條閘極線,其中N為正整數;N個移位暫存器,設置於該周邊區,且電性耦接至該N條閘極線,用以輸出一閘極訊號;複數個畫素電路,設置於該主動區,且電性耦接至該N條閘極線,用以接收該閘極訊號、一資料訊號以及一參考訊號;一開關電路,設置於該周邊區,且電性耦接至該N個移位暫存器、該N條閘極線及該些畫素電路,用以接收一控制訊號以及一致能訊號並將該N條閘極線的電壓位準下拉至低位準;以及複數個測試墊,設置於該周邊區,且電性耦接至該開關電路以及該些畫素電路,用以提供該控制訊號、該致能訊號、該資料訊號以及該參考訊號。
  2. 如請求項1所述的顯示面板,其中該資料訊號包含一第一資料訊號、一第二資料訊號以及一第三資料訊號。
  3. 如請求項2所述的顯示面板,其中該些測試墊,更包含: 一第一測試墊,電性耦接至該些畫素電路,用以提供該參考訊號至該些畫素電路;一第二測試墊,電性耦接至該開關電路,用以提供該控制訊號至該開關電路;一第三測試墊,電性耦接至該開關電路,用以提供該致能訊號至該開關電路;一第四測試墊,電性耦接至該些畫素電路,用以提供該第一資料訊號至該些畫素電路;一第五測試墊,電性耦接至該些畫素電路,用以提供該第二資料訊號至該些畫素電路;以及一第六測試墊,電性耦接至該些畫素電路,用以提供該第三資料訊號至該些畫素電路。
  4. 如請求項3所述的顯示面板,該些畫素電路,更包含:一驅動電路;一發光二極體,具有一第一端以及一第二端,該第一端電性耦接至該驅動電路,該第二端電性耦接至該第一測試墊;以及一測試開關,具有一第三端、一第四端以及一控制端,該第三端電性耦接至該第一端,該第四端電性耦接至該第四測試墊、該第五測試墊以及該第六測試墊的其中之一,該控制端電性耦接至該N條閘極線的其中之一。
  5. 如請求項3所述的顯示面板,其中該開關電路,更包含:N-1個開關,該N-1個開關彼此依序串聯,其中第N-1個開關具有一第一端、一第二端以及一控制端,該第一端電性耦接至第N-1條閘極線,該第二端電性耦接至第N條閘極線,該控制端電性耦接至該第二測試墊。
  6. 如請求項5所述的顯示面板,其中該開關電路,更包含:第N個開關,具有一第一端、一第二端以及一控制端,該第一端電性耦接至第N條閘極線,該第二端電性耦接至該第三測試墊,該控制端電性耦接至該第二測試墊。
  7. 如請求項1的顯示面板,其中該些測試墊,更包含:一第一測試墊,電性耦接至該些畫素電路,用以提供該參考訊號至該些畫素電路;一第二測試墊,電性耦接至該開關電路,用以提供該控制訊號至該開關電路;一第三測試墊,電性耦接至該開關電路,用以提供該致能訊號至該開關電路;以及一第四測試墊,電性耦接至該些畫素電路,用以提供該資料訊號至該些畫素電路。
  8. 如請求項7所述的顯示面板,該些畫素電路,更包含:一驅動電路;一發光二極體,具有一第一端以及一第二端,該第一端電性耦接至該驅動電路,該第二端電性耦接至該第一測試墊;以及一測試開關,具有一第三端、一第四端以及一控制端,該第三端電性耦接至該第一端,該第四端電性耦接至該第四測試墊,該控制端電性耦接至該N條閘極線的其中之一。
  9. 如請求項7所述的顯示面板,其中該開關電路,更包含:N-1個開關,該N-1個開關彼此依序串聯,其中第N-1個開關具有一第一端、一第二端以及一控制端,該第一端電性耦接至第N-1條閘極線,該第二端電性耦接至第N條閘極線,該控制端電性耦接至該第二測試墊。
  10. 如請求項9所述的顯示面板,其中該開關電路,更包含:第N個開關,具有一第一端、一第二端以及一控制端,該第一端電性耦接至第N條閘極線,該第二端電性耦接至該第三測試墊,該控制端電性耦接至該第二測試墊。
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