WO2019037302A1 - 像素内部补偿电路及驱动方法 - Google Patents

像素内部补偿电路及驱动方法 Download PDF

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WO2019037302A1
WO2019037302A1 PCT/CN2017/111407 CN2017111407W WO2019037302A1 WO 2019037302 A1 WO2019037302 A1 WO 2019037302A1 CN 2017111407 W CN2017111407 W CN 2017111407W WO 2019037302 A1 WO2019037302 A1 WO 2019037302A1
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control signal
node
phase
low level
compensation circuit
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PCT/CN2017/111407
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English (en)
French (fr)
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何健
许神贤
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/744,829 priority Critical patent/US10504441B2/en
Publication of WO2019037302A1 publication Critical patent/WO2019037302A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel internal compensation circuit and a driving method.
  • the OLED display device can be classified into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED) according to the driving method.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • AMOLED is a current-driven device. The brightness is determined by the current flowing through the OLED itself.
  • Most existing chips (IC) only transmit voltage signals, so the AMOLED pixel driving circuit must complete the task of converting the voltage signal into a current signal.
  • the active matrix light-emitting diode realizes the display effect by driving the TFT to control the current flowing through the light-emitting diode.
  • the driving TFT is affected by the illumination, the source-drain voltage stress and the like during use, and the threshold voltage is biased. The shift, which in turn affects the current flowing through the LED, results in uneven display of the panel.
  • FIG. 1 it is a schematic diagram of the internal compensation circuit of the existing pixel 4T1C
  • FIG. 2 is a schematic diagram of its driving timing
  • the 4T1C refers to a circuit mainly comprising four thin film transistors T1 T T4 and one capacitor C1 .
  • T2 is the driving TFT
  • the threshold voltage can be expressed as Vth_T2
  • OVDD is the power supply high potential
  • OVSS is the power supply low potential
  • SCAN1 and SCAN2 are the control signals for controlling the corresponding TFT switches
  • Vdata is the data voltage
  • Vini For the initial point
  • Vref is the reference potential.
  • Panel manufacturers often compensate for TFT threshold voltage offset by internal compensation.
  • the entire internal compensation process can include Reset, Sensing, and Data writing. ), Emission four stages.
  • Reset phase T3, T4 is turned on, discharges voltages of point A and point B to Vini;
  • detection phase T1 is turned on, voltage of point A is maintained at reference potential Vref, and is affected by OVDD charging, and voltage of point B is gradually charged to Vref-Vth_T2, but It is smaller than the turn-on voltage of the OLED.
  • the equivalent capacitance C2 of the OLED itself maintains the voltage at point B;
  • the data writing phase T1 continues to be turned on, the data voltage Vdata is written to point A;
  • the light-emitting phase T2 is turned on, and the OLED starts to emit light.
  • T SCAN As the resolution of the panel continues to increase, the single-line scan time T SCAN becomes shorter and shorter. Since the potential of the data line needs to be switched between the reference potential Vref and the data voltage Vdata, the upper and lower rows of adjacent pixels The internal compensation process cannot be overlapped, so T SENSE ⁇ T SCAN , where T SENSE is the detection time. The detection process of the threshold voltage Vth needs to be long enough, otherwise the B point cannot be fully charged, which directly leads to the final compensation failure. Therefore, this internal compensation method is not applicable to high resolution panels.
  • Another object of the present invention is to provide an improved driving method for a pixel internal compensation circuit, which is suitable for increasing the detection time of threshold voltage compensation.
  • the present invention provides a pixel internal compensation circuit, including:
  • a first thin film transistor having a gate connected to a third control signal, and a source and a drain respectively connected to the data voltage and the first node;
  • a second thin film transistor having a gate connected to the first node, a source and a drain respectively connected to the second node and a high potential of the power source;
  • a third thin film transistor having a gate connected to the first control signal, and a source and a drain connected to the first node and the reference potential, respectively;
  • a fourth thin film transistor having a gate connected to the second control signal, the source and the drain being respectively connected to the second node and the initial potential;
  • the anode is connected to the second node, and the cathode is connected to the power source at a low potential;
  • the timings of the first control signal, the second control signal, and the third control signal are configured to include a reset phase, a detection phase, a data writing phase, and an illumination phase.
  • the first control signal is at a high level
  • the second control signal is at a high level
  • the third control signal is at a low level.
  • the first control signal is at a high level
  • the second control signal is at a low level
  • the third control signal is at a low level
  • the first control signal is a low level
  • the second control signal is a low level
  • the third control signal is a high level
  • the first control signal is a low level
  • the second control signal is a low level
  • the third control signal is a low level
  • the first control signal of the current row pixel and the adjacent row pixel is respectively configured, and the second control The timing of the signal and the third control signal causes the data writing phase of the current row of pixels to be staggered from the data writing phase of the adjacent row of pixels.
  • the present invention also provides a driving method of the pixel internal compensation circuit as described above, including: the timing of the first control signal, the second control signal, and the third control signal is configured to include a reset phase, a detection phase , data writing phase, and lighting phase.
  • the first control signal in the reset phase, is at a high level, the second control signal is at a high level, and the third control signal is at a low level; in the detecting phase, the first control signal is a high level Ping, the second control signal is low level, the third control signal is low level; in the data writing phase, the first control signal is low level, the second control signal is low level, and the third control signal is It is a high level; in the light emitting phase, the first control signal is a low level, the second control signal is a low level, and the third control signal is a low level.
  • the timings of the first control signal, the second control signal, and the third control signal of the current row pixel and the adjacent row pixel are respectively configured, so that the data writing phase of the current row pixel and the data writing phase of the adjacent row pixel are respectively performed. Staggered from each other.
  • the invention also provides a pixel internal compensation circuit, comprising:
  • a first thin film transistor having a gate connected to a third control signal, and a source and a drain respectively connected to the data voltage and the first node;
  • a second thin film transistor having a gate connected to the first node, a source and a drain respectively connected to the second node and a high potential of the power source;
  • a third thin film transistor having a gate connected to the first control signal, and a source and a drain connected to the first node and the reference potential, respectively;
  • a fourth thin film transistor having a gate connected to the second control signal, the source and the drain being respectively connected to the second node and the initial potential;
  • the anode is connected to the second node, and the cathode is connected to the power source at a low potential;
  • the timings of the first control signal, the second control signal, and the third control signal are configured to include a reset phase, a detection phase, a data writing phase, and an illumination phase;
  • the first control signal is at a high level
  • the second control signal is at a high level
  • the third control signal is at a low level
  • the first control signal is a high level
  • the second control signal is a low level
  • the third control signal is a low level
  • the first control signal is a low level
  • the second control signal Low level the third control signal is high.
  • the pixel internal compensation circuit and the driving method of the present invention improve the problem that the current threshold voltage compensation time is limited by the resolution, and can effectively increase the detection time of the threshold voltage compensation by the parallel driving method, thereby improving the compensation effect.
  • FIG. 1 is a schematic structural diagram of an internal compensation circuit of a conventional pixel 4T1C;
  • FIG. 2 is a schematic diagram of driving timing of FIG. 1;
  • FIG. 3 is a schematic circuit diagram of a pixel internal compensation circuit according to a preferred embodiment of the present invention.
  • FIG. 4 is a timing diagram of parallel driving of a pixel internal compensation circuit according to a preferred embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a pixel internal compensation circuit according to a preferred embodiment of the present invention.
  • the preferred embodiment is a 4T1C circuit, including thin film transistors T1 to T4, and a capacitor C1.
  • the three control signals are SCAN1 and SCAN2, respectively.
  • SCAN3, corresponding to control three thin film transistors T3, T4 and T1, T2 is the driving TFT in the circuit.
  • T1 connects node A and data line with input data voltage Vdata
  • T3 connects node A and reference voltage Vref
  • T4 connects node B and initial voltage Vini.
  • the data line provides only Vdata and does not need to be switched between Vdata and Vref as in the prior art.
  • the pixel internal compensation circuit of the present invention mainly comprises: T1, a gate connection control signal SCAN3, a source and a drain respectively connected to the data voltage Vdata and the node A; T2, a gate connection node A, and a source and a drain respectively connected to the node B And the power supply high potential OVDD; T3, the gate connection control signal SCAN1, the source and the drain are respectively connected to the node A and the reference potential Vref; T4, the gate is connected to the control signal SCAN2, and the source and the drain are respectively connected to the node B and the initial potential Vini; capacitor C1, both ends are connected to node A and node B; OLED, anode is connected to node B, and cathode is connected to power supply low potential OVSS; wherein initial potential Vini ⁇ OLED opening voltage, reference potential Vref-initial potential Vini>T2 Threshold voltage Vth_T2.
  • the entire driving process includes Reset, Sensing, Data writing, Emission.
  • the stages are represented by (1), (2), (3), and (4).
  • Reset phase SCAN1 and SCAN2 are high, that is, T3 and T4 are open, SCAN3 is low, and T1 is off.
  • the node A voltage (VA) is discharged to the Vref voltage
  • the node B voltage (VB) is discharged to the Vini voltage, where Vini is lower than the OLED lighting voltage threshold Vth_OLED to ensure that the OLED does not emit light during the reset phase.
  • Vref satisfies Vref-Vini>Vth_T2 to turn T2 on, where Vth_T2 is the threshold voltage of T2.
  • the pixel internal compensation circuit of the invention improves the existing 4T1C internal compensation pixel structure, and is suitable for combining the parallel driving method, thereby improving the compensation time.
  • the parallel driving mode of the Nth row and the N+1 row pixel is taken as an example to illustrate the parallel driving mode. Since the data line only provides Vdata, there is no need to switch like the existing circuit shown in FIG. 1, and the pixel of the present invention is used.
  • the internal compensation circuit, the internal compensation process of the upper and lower two rows of adjacent pixels can be overlapped, so parallel driving can be adopted.
  • the detection time T SENSE of the threshold voltage Vth of the driving TFT T2 is not Further limited by the single-line scan time T SCAN , the T SENSE can be set long enough to fully charge the node B voltage and increase the threshold voltage Vth compensation effect, so the present invention can be applied to a high-resolution panel.
  • the present invention further provides a driving method of the pixel internal compensation circuit, which is suitable for effectively increasing the detection time of the driving TFT threshold voltage Vth compensation in combination with the parallel driving mode, thereby improving the compensation effect.
  • the pixel internal compensation circuit and the driving method of the present invention improve the problem that the current threshold voltage compensation time is limited by the resolution, and can effectively increase the detection time of the threshold voltage compensation by the parallel driving method, thereby improving the compensation effect, and is suitable for high Resolution AMOLED panel.

Abstract

一种像素内部补偿电路，该像素内部补偿电路包括：第一薄膜晶体管(T1)栅极连接第三控制信号(SCAN3)，源极和漏极连接数据电压(Vdata)和第一节点(A)；第二薄膜晶体管(T2)栅极连接第一节点(A)，源极和漏极连接第二节点(B)和电源高电位(OVDD)；第三薄膜晶体管(T3)栅极连接第一控制信号(SCAN1)，源极和漏极连接第一节点(A)和参考电位(Vref)；第四薄膜晶体管(T4)栅极连接第二控制信号(SCAN2)，源极和漏极连接第二节点(B)和初始电位(Vini)；电容(C1)连接第一节点(A)和第二节点(B)；OLED连接第二节点(B)和电源低电位(OVSS)。还提供了一种像素内部补偿电路的驱动方法。该电路和驱动方法能够通过并行驱动方式有效增加阈值电压补偿的侦测时间，提升补偿效果。

Description

像素内部补偿电路及驱动方法 技术领域
本发明涉及显示技术领域，尤其涉及一种像素内部补偿电路及驱动方法。
背景技术
OLED显示装置按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。AMOLED是电流驱动器件，亮度由流过OLED自身的电流决定，大部分已有芯片(IC)都只传输电压信号，故AMOLED像素驱动电路要完成将电压信号转变为电流信号的任务。
有源矩阵发光二极管(简称AMOLED)是通过驱动TFT控制流过发光二极管的电流实现显示效果，驱动TFT在使用过程中由于受到光照、源漏极电压应力等因素影响，导致其阈值电压的产生偏移，进而影响流过发光二极管的电流，导致面板的显示不均。
参见图1，其为现有像素4T1C内部补偿电路结构示意图，图2为其驱动时序示意图，4T1C指电路主要包括四个薄膜晶体管T1～T4和一个电容C1。图1所示电路中，T2为驱动TFT，其阈值电压可以表示为Vth_T2，OVDD为电源高电位，OVSS为电源低电位，SCAN1和SCAN2为控制相应TFT开关的控制信号，Vdata为数据电压，Vini为初始点位，Vref为参考电位。面板厂商常常通过内部补偿的方式对TFT阈值电压偏移进行补偿恢复，参照图2所示时序图，整个内部补偿过程可以包括重置(Reset)、侦测(Sensing)、数据写入(Data writing)、发光(Emission)四个阶段。重置阶段T3，T4开启，将A点和B点电压放电到Vini；侦测阶段T1开启，A点电压维持在参考电位Vref，受到OVDD充电影响，B点电压逐渐充电到Vref－Vth_T2，但小于OLED的开启电压，此时OLED本身的等效电容C2保持B点电压；数据写入阶段T1继续开启，数据电压Vdata写入A点；发光阶段T2开启，OLED开始发光。
随着面板解析度不断提升，单行的扫描时间TSCAN变得越来越短，由于数据线(Data line)的电位需要在参考电位Vref和数据电压Vdata之间切换， 因此上下两行相邻像素的内部补偿过程无法重叠进行，因此TSENSE<TSCAN，其中TSENSE为侦测时间。阈值电压Vth的侦测过程需要满足足够长时间，否则B点无法充电完全，直接导致最终补偿失败。因此该内部补偿方式并不适用高解析度面板。
发明内容
因此，本发明的目的在于提供一种改进的像素内部补偿电路，适合于提升阈值电压补偿的侦测时间。
本发明的另一目的在于提供一种改进的像素内部补偿电路的驱动方法，适合于提升阈值电压补偿的侦测时间。
为实现上述目的，本发明提供了一种像素内部补偿电路，包括：
第一薄膜晶体管，其栅极连接第三控制信号，源极和漏极分别连接数据电压和第一节点；
第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和电源高电位；
第三薄膜晶体管，其栅极连接第一控制信号，源极和漏极分别连接第一节点和参考电位；
第四薄膜晶体管，其栅极连接第二控制信号，源极和漏极分别连接第二节点和初始电位；
电容，其两端分别连接第一节点和第二节点；
OLED，其阳极连接第二节点，阴极连接电源低电位；
该初始电位＜OLED的开启电压，参考电位－初始电位>第二薄膜晶体管的阈值电压。
其中，所述第一控制信号，第二控制信号，以及第三控制信号的时序配置为包括重置阶段，侦测阶段，数据写入阶段，以及发光阶段。
其中，在重置阶段，所述第一控制信号为高电平，第二控制信号为高电平，第三控制信号为低电平。
其中，在侦测阶段，所述第一控制信号为高电平，第二控制信号为低电平，第三控制信号为低电平。
其中，在数据写入阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为高电平。
其中，在发光阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为低电平。
其中，分别配置当前行像素与相邻行像素的第一控制信号，第二控制 信号，以及第三控制信号的时序，使当前行像素的数据写入阶段与相邻行像素的数据写入阶段相互错开。
本发明还提供了一种如上所述的像素内部补偿电路的驱动方法，包括：所述第一控制信号，第二控制信号，以及第三控制信号的时序配置为包括重置阶段，侦测阶段，数据写入阶段，以及发光阶段。
其中，在重置阶段，所述第一控制信号为高电平，第二控制信号为高电平，第三控制信号为低电平；在侦测阶段，所述第一控制信号为高电平，第二控制信号为低电平，第三控制信号为低电平；在数据写入阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为高电平；在发光阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为低电平。
其中，分别配置当前行像素与相邻行像素的第一控制信号，第二控制信号，以及第三控制信号的时序，使当前行像素的数据写入阶段与相邻行像素的数据写入阶段相互错开。
本发明还提供一种像素内部补偿电路，包括：
第一薄膜晶体管，其栅极连接第三控制信号，源极和漏极分别连接数据电压和第一节点；
第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和电源高电位；
第三薄膜晶体管，其栅极连接第一控制信号，源极和漏极分别连接第一节点和参考电位；
第四薄膜晶体管，其栅极连接第二控制信号，源极和漏极分别连接第二节点和初始电位；
电容，其两端分别连接第一节点和第二节点；
OLED，其阳极连接第二节点，阴极连接电源低电位；
该初始电位＜OLED的开启电压，参考电位－初始电位>第二薄膜晶体管的阈值电压；
其中，所述第一控制信号，第二控制信号，以及第三控制信号的时序配置为包括重置阶段，侦测阶段，数据写入阶段，以及发光阶段；
其中，在重置阶段，所述第一控制信号为高电平，第二控制信号为高电平，第三控制信号为低电平；
其中，在侦测阶段，所述第一控制信号为高电平，第二控制信号为低电平，第三控制信号为低电平；
其中，在数据写入阶段，所述第一控制信号为低电平，第二控制信号 为低电平，第三控制信号为高电平。
综上，本发明的像素内部补偿电路及驱动方法改善现有阈值电压补偿时间受限于解析度的问题，能够通过并行驱动方式有效增加阈值电压补偿的侦测时间，提升补偿效果。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有像素4T1C内部补偿电路结构示意图；
图2为图1的驱动时序示意图；
图3为本发明像素内部补偿电路一较佳实施例的电路示意图；
图4为本发明像素内部补偿电路一较佳实施例的并行驱动时序示意图。
具体实施方式
参见图3，其为本发明像素内部补偿电路一较佳实施例的电路示意图，该较佳实施例为4T1C电路，包括薄膜晶体管T1～T4，以及电容C1，三个控制信号分别是SCAN1、SCAN2和SCAN3，对应控制T3、T4和T1三个薄膜晶体管，T2为该电路中的驱动TFT。其中T1连接节点A和数据线(data line)以输入数据电压Vdata，T3连接节点A和参考电压Vref，T4连接节点B和初始电压Vini。在本发明中，数据线仅提供Vdata，不需要如现有技术在Vdata和Vref之间切换。
本发明的像素内部补偿电路主要包括：T1，栅极连接控制信号SCAN3，源极和漏极分别连接数据电压Vdata和节点A；T2，栅极连接节点A，源极和漏极分别连接节点B和电源高电位OVDD；T3，栅极连接控制信号SCAN1，源极和漏极分别连接节点A和参考电位Vref；T4，栅极连接控制信号SCAN2，源极和漏极分别连接节点B和初始电位Vini；电容C1，两端分别连接节点A和节点B；OLED，阳极连接节点B，阴极连接电源低电位OVSS；其中，初始电位Vini＜OLED的开启电压，参考电位Vref－初始电位Vini>T2的阈值电压Vth_T2。
现结合图4来进一步说明本发明的像素内部补偿电路。对于每一行像素来说，无论是第N行或第N+1行像素，整个驱动过程都包括重置(Reset)、侦测(Sensing)、数据写入(Data writing)、发光(Emission)四个阶段，分别用(1)、(2)、(3)、(4)表示。
(1)重置阶段：SCAN1和SCAN2为高电平，即T3和T4打开，SCAN3为低电平，T1关闭。节点A电压(VA)被放电到Vref电压，节点B电压(VB)被放电到Vini电压，其中Vini低于OLED发光电压阈值Vth_OLED，以确保重置阶段OLED不发光。Vref满足Vref－Vini>Vth_T2，以使T2打开，其中Vth_T2为T2的阈值电压。
(2)侦测阶段：SCAN2转为低电平，T4关闭。由于T2打开，节点B逐渐充电，电压最终变为Vref-Vth_T2，此时T2关闭，通过OLED本身的等效电容C2保持节点B的电压；
(3)数据写入阶段：SCAN1和SCAN2为低电平，T3和T4关闭，SCAN3转高电平，T1打开，节点A被充电至Vdata；
(4)发光阶段：SCAN1、SCAN2和SCAN3拉低电平，T1、T2和T3关闭，OLED开始发光。
本发明的像素内部补偿电路改进了现有4T1C内部补偿像素结构，适合于结合并行驱动方法，从而提升补偿时间。参见图4，以第N行和N+1行像素的并行驱动时序为例来说明并行驱动方式，由于数据线仅提供Vdata，无需像图1所示现有电路一样切换，采用本发明的像素内部补偿电路，上下两行相邻像素的内部补偿过程可以重叠进行，因此可采用并行驱动方式。只需满足第N行和N+1行的数据写入阶段相互错开，其中重置、侦测阶段由于相互独立，因此可以重叠，作为驱动TFT的T2的阈值电压Vth的侦测时间TSENSE不再受限于单行扫描时间TSCAN，可以将TSENSE设置足够长，使得节点B电压充电完全，提升阈值电压Vth补偿效果，因此本发明可适用于高解析度面板。
对应于上述像素内部补偿电路，本发明还相应提供了像素内部补偿电路的驱动方法，适合于结合并行驱动方式有效增加驱动TFT阈值电压Vth补偿的侦测时间，提升补偿效果。
综上，本发明的像素内部补偿电路及驱动方法改善现有阈值电压补偿时间受限于解析度的问题，能够通过并行驱动方式有效增加阈值电压补偿的侦测时间，提升补偿效果，适用于高解析度AMOLED面板。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (13)

  1. 一种像素内部补偿电路，包括：
    第一薄膜晶体管，其栅极连接第三控制信号，源极和漏极分别连接数据电压和第一节点；
    第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和电源高电位；
    第三薄膜晶体管，其栅极连接第一控制信号，源极和漏极分别连接第一节点和参考电位；
    第四薄膜晶体管，其栅极连接第二控制信号，源极和漏极分别连接第二节点和初始电位；
    电容，其两端分别连接第一节点和第二节点；
    OLED，其阳极连接第二节点，阴极连接电源低电位；
    该初始电位＜OLED的开启电压，参考电位－初始电位>第二薄膜晶体管的阈值电压。
  2. 如权利要求1所述的像素内部补偿电路，其中，所述第一控制信号，第二控制信号，以及第三控制信号的时序配置为包括重置阶段，侦测阶段，数据写入阶段，以及发光阶段。
  3. 如权利要求2所述的像素内部补偿电路，其中，在重置阶段，所述第一控制信号为高电平，第二控制信号为高电平，第三控制信号为低电平。
  4. 如权利要求2所述的像素内部补偿电路，其中，在侦测阶段，所述第一控制信号为高电平，第二控制信号为低电平，第三控制信号为低电平。
  5. 如权利要求2所述的像素内部补偿电路，其中，在数据写入阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为高电平。
  6. 如权利要求2所述的像素内部补偿电路，其中，在发光阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为低电平。
  7. 如权利要求2所述的像素内部补偿电路，其中，分别配置当前行像素与相邻行像素的第一控制信号，第二控制信号，以及第三控制信号的时序，使当前行像素的数据写入阶段与相邻行像素的数据写入阶段相互错开。
  8. 一种如权利要求1所述的像素内部补偿电路的驱动方法，包括：所述第一控制信号，第二控制信号，以及第三控制信号的时序配置为包括重置阶段，侦测阶段，数据写入阶段，以及发光阶段。
  9. 如权利要求8所述的像素内部补偿电路的驱动方法，其中，在重置阶段，所述第一控制信号为高电平，第二控制信号为高电平，第三控制信号为低电平；在侦测阶段，所述第一控制信号为高电平，第二控制信号为低电平，第三控制信号为低电平；在数据写入阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为高电平；在发光阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为低电平。
  10. 如权利要求8所述的像素内部补偿电路的驱动方法，其中，分别配置当前行像素与相邻行像素的第一控制信号，第二控制信号，以及第三控制信号的时序，使当前行像素的数据写入阶段与相邻行像素的数据写入阶段相互错开。
  11. 一种像素内部补偿电路，包括：
    第一薄膜晶体管，其栅极连接第三控制信号，源极和漏极分别连接数据电压和第一节点；
    第二薄膜晶体管，其栅极连接第一节点，源极和漏极分别连接第二节点和电源高电位；
    第三薄膜晶体管，其栅极连接第一控制信号，源极和漏极分别连接第一节点和参考电位；
    第四薄膜晶体管，其栅极连接第二控制信号，源极和漏极分别连接第二节点和初始电位；
    电容，其两端分别连接第一节点和第二节点；
    OLED，其阳极连接第二节点，阴极连接电源低电位；
    该初始电位＜OLED的开启电压，参考电位－初始电位>第二薄膜晶体管的阈值电压；
    其中，所述第一控制信号，第二控制信号，以及第三控制信号的时序配置为包括重置阶段，侦测阶段，数据写入阶段，以及发光阶段；
    其中，在重置阶段，所述第一控制信号为高电平，第二控制信号为高电平，第三控制信号为低电平；
    其中，在侦测阶段，所述第一控制信号为高电平，第二控制信号为低电平，第三控制信号为低电平；
    其中，在数据写入阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为高电平。
  12. 如权利要求11所述的像素内部补偿电路，其中，在发光阶段，所述第一控制信号为低电平，第二控制信号为低电平，第三控制信号为低电 平。
  13. 如权利要求11所述的像素内部补偿电路，其中，分别配置当前行像素与相邻行像素的第一控制信号，第二控制信号，以及第三控制信号的时序，使当前行像素的数据写入阶段与相邻行像素的数据写入阶段相互错开。
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