TWI679741B - 互補金屬氧化物半導體感測器及其形成方法 - Google Patents

互補金屬氧化物半導體感測器及其形成方法 Download PDF

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Publication number
TWI679741B
TWI679741B TW107114019A TW107114019A TWI679741B TW I679741 B TWI679741 B TW I679741B TW 107114019 A TW107114019 A TW 107114019A TW 107114019 A TW107114019 A TW 107114019A TW I679741 B TWI679741 B TW I679741B
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Taiwan
Prior art keywords
dielectric layer
semiconductor substrate
bonding pad
dielectric
pattern
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TW107114019A
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English (en)
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TW201919183A (zh
Inventor
辜瑜倩
Yu-Chien Ku
董懷仁
Huai-Jen Tung
廖耕潁
Keng-Ying Liao
陳益弘
Yi-Hung Chen
徐世勳
Shih-Hsun Hsu
楊怡芳
Yi-fang YANG
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台灣積體電路製造股份有限公司
Taiwan Semiconductor Manufacturing Co., Ltd.
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Publication of TW201919183A publication Critical patent/TW201919183A/zh
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Abstract

本發明實施例提供一種互補金屬氧化物半導體感測器，包括半導體基底、介電層、內連線、接合墊以及虛設圖案。所述半導體基底具有畫素區和電路區。所述介電層被所述電路區中的所述半導體基底環繞。所述內連線設置在所述電路區中的所述介電層上。所述接合墊設置在所述電路區中的所述介電層中且電連接至所述內連線。所述虛設圖案設置在所述電路區中的所述介電層中且環繞所述接合墊。

Description

互補金屬氧化物半導體感測器及其形成方法
本發明實施例是有關於一種互補金屬氧化物半導體感測器及其形成方法。
影像感測器廣泛應用於數位相機、手機、安防攝影機、醫療、汽車等應用領域。用於製造影像感測器(特別是用於製造互補金屬氧化物半導體(complementary metal-oxide-semiconductor，CMOS))影像感測器)的技術持續快速發展。舉例來說，高解析度和低功率消耗的要求促使了影像感測器的進一步微型化和集成化。
本發明實施例的一種互補金屬氧化物半導體感測器包括半導體基底、介電層、內連線、接合墊以及虛設圖案。所述半導體基底具有畫素區和電路區。所述介電層被所述電路區中的所述半導體基底環繞。所述內連線設置在所述電路區中的所述介電層 上。所述接合墊設置在所述電路區中的所述介電層中且電連接至所述內連線。所述虛設圖案設置在所述電路區中的所述介電層中且環繞所述接合墊。
本發明實施例的一種互補金屬氧化物半導體感測器包括圖案化的半導體基底、圖案化的介電層、內連線、接合墊以及虛設圖案。所述圖案化的介電層由所述圖案化的半導體基底暴露且所述圖案化的介電層在其第一表面處具有至少一個溝槽。所述內連線設置在與所述圖案化的介電層的所述第一表面相對的第二表面上。所述接合墊設置在所述圖案化的介電層的所述第一表面上且電連接至所述內連線。所述虛設圖案設置在所述溝槽內，並設置在所述接合墊旁。
本發明實施例的一種形成互補金屬氧化物半導體感測器的方法，包括以下步驟。提供具有畫素區和電路區的所述半導體基底。在所述電路區中的所述半導體基底上形成介電圖案。在所述半導體基底上形成介電層以覆蓋所述介電圖案。在所述電路區中的所述介電層上形成內連線。移除所述半導體基底的一部分，以形成第一開口，所述第一開口暴露所述介電圖案。移除所述介電圖案，以在所述第一開口中的所述介電層中形成溝槽，所述溝槽不穿透所述介電層。在所述第一開口中的所述介電層中形成接合墊，以電連接至所述內連線。在所述溝槽中形成位於所述接合墊旁的虛設圖案。
110‧‧‧基底
110a‧‧‧第一表面
110b‧‧‧第二表面
112‧‧‧畫素區
114‧‧‧電路區
116‧‧‧絕緣體
116a‧‧‧外部分
120‧‧‧介電圖案
122、134、138、142a、142b‧‧‧介電層
122a、122b‧‧‧表面
130‧‧‧內連線
132、136、140‧‧‧導電結構
132a、136a、140a‧‧‧接觸窗
132b、136b、140b、150‧‧‧導電層
141‧‧‧鈍化層
144‧‧‧光阻層
144a、146、149‧‧‧開口
148‧‧‧溝槽
152‧‧‧接合墊
154‧‧‧虛設圖案
S210、S220、S230、S240‧‧‧步驟
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1是根據本發明的一些實施例的形成CMOS感測器的方法的流程圖。
圖2A至圖2E繪示根據本發明的一些實施例的形成CMOS感測器的方法的示意性橫截面圖。
圖3繪示根據本發明的一些實施例的CMOS感測器的虛設圖案和接合墊的示意性上視圖。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例且不旨在執行限制。舉例來說，以下說明中將第一特徵形成在第二特徵“上方”或第二特徵“上”可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、從而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開可能在各種實例中重複使用參考編號及/或字母。這種重複 使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在...之下(beneath)”、“在...下面(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或其他取向)，且本文中所用的空間相對性描述語可同樣相應地執行解釋。
圖1是根據本發明的一些實施例的形成CMOS感測器的方法的流程圖。圖2A至圖2E繪示根據本發明的一些實施例的形成CMOS感測器的方法的示意性橫截面圖。圖3繪示根據本發明的一些實施例的CMOS感測器的虛設圖案和接合墊的示意性上視圖。
請參考圖1和圖2A，在步驟S210中，提供半導體基底110，並且介電圖案120、介電層122和內連線130依序地設置在半導體基底110上方。半導體基底110包括第一表面110a和與第一表面110a相對的第二表面110b。舉例來說，在一些實施例中，第一表面110a是前側，第二表面110b是後側。半導體基底110具有畫素區112和在畫素區112旁的電路區114。舉例來說，畫素區112也是主動區，並且包括多個影像感測單元和相位檢測單元。在一些實施例中，影像感測單元和相位檢測單元是通過對半導體 基底110的第一表面110a進行離子植入而形成的。舉例來說，影像感測單元和相位檢測單元是光電二極體，其中每個光電二極體可以包括至少一個p型摻雜區、至少一個n型摻雜區以及在p型摻雜區和n型摻雜區之間形成的pn接面。具體而言，當半導體基底110是p型基底時，諸如磷(P)或砷(As)的n型摻雜劑可以摻雜到畫素區112中以形成n型阱，以及畫素區112中所形成的pn接面能夠執行影像感測功能和相位檢測功能。類似地，當半導體基底110是n型基底時，諸如BF2的硼之類的p型摻雜劑可以被摻雜到畫素區112中以形成p型阱，以及畫素區112中所形成的pn接面能夠執行影像感測功能和相位檢測功能。這裡省略了用於形成n型摻雜區(阱)或p型摻雜區(阱)的離子植入製程的詳細描述。在一些替代實施例中，影像感測單元和相位檢測單元可以是能夠執行影像感測和相位檢測功能的其他光電元件。當反偏壓施加到影像感測單元和相位檢測單元的pn接面時，pn接面對入射光線敏感。由影像感測單元和相位檢測單元接收或檢測到的光線被轉換成光電流，使得產生代表光電流強度的類比訊號。電路區114被指定為用於接收和處理源自影像感測單元和相位檢測單元的訊號。電路區114例如包括導線和與非/反或閘。
半導體基底110的材料包括合適的元素半導體，例如矽、金剛石或鍺；合適的化合物半導體，例如砷化鎵、碳化矽、砷化銦或磷化銦；或合適的合金半導體，例如矽鍺碳化物、磷砷化鎵或磷化鎵銦。在一些實施例中，半導體基底110可以包括摻雜有 磷或砷等p型摻雜劑的矽。在一些實施例中，半導體基底110具有約1.5μm至約3μm的厚度。
在一些實施例中，在第一表面110a處的半導體基底110中形成絕緣體116。換句話說，絕緣體116形成為嵌入在半導體基底110中。在一些實施例中，絕緣體116是淺溝槽隔離(shallow trench isolation，STI)結構。然而，本發明不限於此。絕緣體116(即STI結構)的形成製程可以通過以下步驟獲得。舉例來說，首先，通過微影/蝕刻製程或其他合適的圖案化製程在半導體基底110中形成具有預定深度的淺溝槽，以形成圖案化的半導體基底110。接下來，將介電層沉積在溝槽中。隨後，移除(例如，研磨、蝕刻或其組合)介電層的一部分以形成絕緣體116(即STI結構)。絕緣體116(即STI結構)的材料包括氧化矽、氮化矽、氮氧化矽、其他合適的材料或其組合。在一些替代實施例中，在電路區114的半導體基底110上形成各種半導體元件，例如n型金屬氧化物半導體(MOS)電晶體或/和p型金屬氧化物半導體電晶體。
在一些實施例中，介電圖案120形成在電路區114中的半導體基底110的第一表面110a上方。舉例來說，介電圖案120形成為環繞絕緣體116。在一些實施例中，介電圖案120呈環形。環形可以是矩形、圓形、橢圓形或其他合適的形狀。介電圖案120的材料具有類似於半導體基底110的蝕刻選擇性。在一些實施例中，介電圖案120的材料包括諸如多晶矽的矽基材料。介電圖案120可以由化學氣相沉積(chemical vapor deposition，CVD)形成， 例如低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)、電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition，PECVD)、高密度電漿化學氣相沉積(high density plasma chemical vapor deposition，HDPCVD)或原子層化學氣相沉積(atomic layer chemical vapor deposition，ALCVD)或其他合適的方法。
在形成介電圖案120之後，介電層122形成在半導體基底110的第一表面110a上方以覆蓋電路區114中的介電圖案120。在一些實施例中，介電層122形成在畫素區112和電路區114兩者中。在一些實施例中，介電層122的材料具有不同於介電圖案120和半導體基底110的蝕刻特性。介電層122的材料可以是低k介電材料(具有小於3.0的k值)，例如旋塗無機介電材料、旋塗有機介電材料、多孔無機介電材料、多孔有機介電材料、有機聚合物或有機矽玻璃。舉例來說，SiLK(k=2.7)或聚烯丙基醚(polyallyl ether，PAE)系材料的FLARE(k=2.8)、黑鑽石(Black Diamond，k=3.0~2.4)、FSG(SiOF系材料)、HSQ(氫倍半矽氧烷(hydrogen silsesquioxane)，k=2.8~3.0)、MSQ(甲基倍半矽氧烷(methyl silsesquioxane)，k=2.5~2.7)、多孔HSQ或多孔MSQ材料。介電層122可以通過諸如LPCVD、PECVD、HDPCVD或ALCVD的CVD、旋塗或其他合適的方法形成。
內連線130形成在電路區114中的介電層122上方。舉例來說，在一些實施例中，內連線130可以是多層內連線，並且 包括導電結構132、136、140。在一些實施例中，導電結構132形成在介電層122上方和之內。在一些實施例中，具有介層孔和溝槽的雙大馬士革製程結構由一系列微影和非等向性蝕刻形成。接下來，通過電化學鍍覆(electrochemical plating，ECP)或無電電鍍將導電材料層鍍在介電層122上。然後，通過化學機械研磨(chemical mechanical polishing，CMP)將導電材料層平坦化以形成包括導電層132b和接觸窗132a的導電結構132。在一些實施例中，導電結構132電連接至半導體元件中的至少一個。然後，通過諸如LPCVD、PECVD、HDPCVD或ALCVD的CVD或旋塗在介電層122上形成介電層134。介電層134的材料可以與介電層122的材料相同或不同。使用一系列微影和非等向性蝕刻在介電層134中形成雙大馬士革製程結構。將導電材料層鍍在介電層134上，接著平坦化導電材料層，以形成通過接觸窗136a連接到導電層132b的導電層136b。隨後，通過CVD或旋塗沉積介電材料在介電層134上形成介電層138。使用一系列微影和非等向性蝕刻在介電層138中形成雙大馬士革製程結構。將導電材料層電鍍在介電層138上，然後平坦化導電材料層，以形成通過接觸窗140a連接到導電層136b的導電層140b。因此，包括接觸窗132a、導電層132b、接觸窗136a、導電層136b、接觸窗140a和導電層140b的多層內連線130鑲嵌在介電層122、134、138中。介電層134、138的材料可以是低k介電材料(具有小於3.0的k值)，例如旋塗無機介電材料、旋塗有機介電材料、多孔無機介電材料、多孔 有機介電材料、有機聚合物或有機矽玻璃。舉例來說，SiLK(k=2.7)或聚烯丙基醚(polyallyl ether，PAE)系材料的FLARE(k=28)、黑鑽石(Black Diamond，k=3.0~2.4)、FSG(SiOF系材料)、HSQ(氫倍半矽氧烷(hydrogen silsesquioxane)，k=2.8~3.0)、MSQ(甲基倍半矽氧烷(methyl silsesquioxane)，k=2.5~2.7)、多孔HSQ或多孔MSQ材料。介電層134、138可以通過諸如LPCVD、PECVD、HDPCVD或ALCVD的CVD、旋塗或其他合適的方法形成。舉例來說，在一些實施例中，在內連線130上形成鈍化層141。
請參考圖1、圖2B和圖2C，在步驟S220和S230中，通過移除半導體基底110的一部分在電路區114中的半導體基底110中形成開口146，並且通過移除介電圖案120在介電層122中形成溝槽148，以形成圖案化的介電層122。在一些實施例中，如圖2B所示，翻轉圖2A的結構，並且在半導體基底110的第二表面110b上方形成光阻層144。光阻層144被圖案化並且在絕緣體116和介電圖案120上方具有開口144a。舉例來說，開口144a的側壁實質上與介電圖案120的外側壁對齊。光阻層144由包括光阻旋塗、軟烘烤、曝光、顯影和硬烘烤的微影形成。在一些實施例中，介電層142a、142b可以形成在光阻層144和半導體基底110之間。因此，光阻層144形成在介電層142b上，並且光阻層144的開口暴露在絕緣體116和介電圖案120上方的介電層142b的一部分。介電層142a、142b的材料具有不同於介電圖案120但類似 於半導體基底110的蝕刻特性。介電層142a、142b可以通過諸如LPCVD、PECVD、HDPCVD或ALCVD的CVD或其他合適的方法形成。
如圖2C所示，在一些實施例中，通過使用光阻層144作為蝕刻罩幕，通過蝕刻製程移除半導體基底110的一部分和介電層142a、142b的一部分，直到絕緣體116的頂面被暴露。另外，由於介電圖案120的材料具有類似於半導體基底110的蝕刻選擇性，所以在半導體基底110和介電層142a、142b的部分移除製程期間，介電圖案120同時被移除以在介電層122中形成溝槽148。換句話說，開口146在邊緣處具有溝槽148。舉例來說，在一些實施例中，半導體基底110的一部分和介電圖案120的一部分可以用背側切割線(back side scribe line，BSSL)蝕刻製程或其他蝕刻製程移除。在一些替代實施例中，可以通過不同於移除半導體基底110和介電層142a、142b的蝕刻製程移除介電圖案120。由於溝槽148是通過移除整個介電圖案120形成的，因此溝槽148的輪廓對應於介電圖案120的輪廓，並且溝槽148的深度對應於介電圖案120的厚度。舉例來說，在一些實施例中，溝槽148圍繞絕緣體116並呈環形。環形可以是矩形、圓形、橢圓形或其他合適的形狀。溝槽148形成在介電層122中，但不穿透介電層122。溝槽148設置在介電層122的表面122a處，並且內連線130設置在與介電層122的表面122a相對的表面122b處。換句話說，溝槽148和內連線130設置在介電層122的相對表面122a、122b處。
開口146的側壁與溝槽148的側壁(即外側壁)對齊，並且溝槽148和由溝槽148圍繞的絕緣體116通過開口146暴露。舉例來說，開口146具有約50至150μm的尺寸，並且溝槽148具有約0.5至1μm的尺寸。溝槽148的深度約為介電層122的厚度的20-30%。舉例來說，溝槽148的深度約為800-1500埃，並且介電層122的厚度約為1000-3200埃。開口146的邊緣的深度大致等於介電層142a、142b、半導體基底110和介電圖案120的總厚度。舉例來說，用於半導體基底110和介電圖案120的蝕刻氣體可能包括溴化氫(HBr)和氧氣。之後，如圖2D所示，光阻層144可以通過例如光阻剝離製程或光阻灰化製程來移除。
請參考圖1、圖2D和圖2E，在步驟S240和S250中，在開口146的一部分中形成接合墊152以電連接至內連線130，並且在接合墊152旁的溝槽148中形成虛設圖案154。在一些實施例中，如圖2D所示，絕緣體116和介電層122的一部分被移除以形成暴露內連線130的一部分的至少一個開口149。然後，導電層150共形地形成在半導體基底110上方的介電層142b上以及絕緣體116的頂面和包括溝槽148的介電層122的頂面上。另外，導電層150填充在溝槽148和開口149中。形成導電層150的方法包括物理氣相沉積(physical vapor deposition，PVD)或使用包括諸如銅(Cu)、鋁(Al)或鋁銅合金的材料的靶進行濺射或其他合適方法。在一些替代實施例中，導電層150更可以包括晶種層、阻擋層或其組合或其多層。
之後，如圖2E所示，通過使用介電層142b作為蝕刻終止層，移除開口146外部和絕緣體116的外部分116a上方的導電層150的一部分。因此，導電層150在開口146中被分成兩部分，即接合墊152和虛設圖案154，且接合墊152和虛設圖案154被絕緣體116的外部分116a和設置在外部分116a下方的介電層122分離。舉例來說，移除導電層150的一部分的方法包括非等向性蝕刻製程。設置在介電層142b和絕緣體116的外部分116a上方的導電層150的一部分被垂直地移除。接合墊152和虛設圖案154彼此隔開一距離，此距離等於絕緣體116的外部分116a的寬度。相對於介電層122的第二表面122b，虛設圖案154的頂面高於接合墊152的頂面。舉例來說，在一些實施例中，虛設圖案154的頂面與半導體基底110的頂面實質上共平面。虛設圖案154通過以諸如垂直方向的方向設置在虛設圖案154和內連線130之間的介電層122與內連線130絕緣。虛設圖案154通過以諸如水平方向的方向設置在虛設圖案154和接合墊152之間的介電層122和絕緣體116與接合墊152絕緣。在一些實施例中，接合墊152設置在貫穿半導體基底110的開口146中，因此半導體基底110不設置在接合墊152和內連線130之間。虛設圖案154和內連線130之間的介電層122的厚度小於介於接合墊152和內連線130之間的介電層122的厚度。虛設圖案154的材料和接合墊152的材料相同。虛設圖案154填滿溝槽148，因此虛設圖案154也具有如圖3所示的環形。環形可以是矩形、圓形、橢圓形或其他合適的形狀。 另外，插入溝槽148中的虛設圖案154具有與插銷相似的形狀。
舉例來說，在一些替代實施例中，例如焊球、微凸塊、控制塌陷晶片連接(C4)凸塊或其組合的導電材料可稍後貼合到接合墊152上以電連接至內連線130。在一些替代實施例中，CMOS影像感測器更可以包括在半導體基底110上的第一平坦化層、在畫素區中第一平坦化層上的濾光器以及在第一平坦化層和濾光器上的第二平坦化層。CMOS影像感測器更可以包括在第二平坦化層上的微透鏡，其中微透鏡與濾光器實質上對齊。舉例來說，CMOS影像感測器可能是NIR(近紅外(near-infrared))CMOS。
在一些實施例中，接合墊被虛設圖案環繞，且虛設圖案以水平方向等方向設置在半導體基底與接合墊之間。在一些實施例中，虛設圖案形成於介電層的溝槽中，並且接觸半導體基底的側壁和絕緣體的側壁以及絕緣體下方的介電層的側壁。換句話說，虛設圖案設置在半導體基底的側壁與絕緣體及絕緣體下方的介電層的側壁之間的空間中，並且虛設圖案進一步插入到溝槽中。因此，虛設圖案實質上被固定在半導體基底與絕緣體之間以及半導體基底與絕緣體下方的介電層中。因此，防止接合墊從半導體基底的側壁上剝落。
在一實施例中，提供一種互補金屬氧化物半導體感測器，包括半導體基底、介電層、內連線、接合墊以及虛設圖案。所述半導體基底具有畫素區和電路區。所述介電層被所述電路區中的所述半導體基底環繞。所述內連線設置在所述電路區中的所 述介電層上。所述接合墊設置在所述電路區中的所述介電層中且電連接至所述內連線。所述虛設圖案設置在所述電路區中的所述介電層中且環繞所述接合墊。
在一些實施例中，所述半導體基底不設置在所述接合墊和所述內連線之間。
在一些實施例中，所述接合墊和所述虛設圖案被所述半導體基底環繞。
在一些實施例中，所述虛設圖案設置在所述半導體基底和所述接合墊之間。
在一些實施例中，所述虛設圖案為環形。
在一些實施例中，所述虛設圖案的材料與所述接合墊的材料相同。
在一些實施例中，所述接合墊與所述虛設圖案相距一定距離。
在一實施例中，提供一種互補金屬氧化物半導體感測器，包括圖案化的半導體基底、圖案化的介電層、內連線、接合墊以及虛設圖案。所述圖案化的介電層由所述圖案化的半導體基底暴露且所述圖案化的介電層在其第一表面處具有至少一個溝槽。所述內連線設置在與所述圖案化的介電層的所述第一表面相對的第二表面上。所述接合墊設置在所述圖案化的介電層的所述第一表面上且電連接至所述內連線。所述虛設圖案設置在所述溝槽內，並設置在所述接合墊旁。
在一些實施例中，互補金屬氧化物半導體感測器更包括絕緣體，其中所述絕緣體設置在所述接合墊和所述圖案化的介電層之間。
在一些實施例中，所述虛設圖案設置在所述半導體基底的側壁及所述絕緣體的側壁之間且與所述半導體基底的側壁及所述絕緣體的側壁接觸。
在一些實施例中，相對於所述第二表面，所述虛設圖案的頂面高於所述接合墊的頂面。
在一些實施例中，所述虛設圖案與所述內連線之間的所述圖案化的介電層的厚度小於所述接合墊與所述內連線之間的所述圖案化介電層的厚度。
在一些實施例中，所述溝槽不穿透所述圖案化的介電層。
在一些實施例中，所述虛設圖案的材料與所述接合墊的材料相同。
在一實施例中，提供一種形成互補金屬氧化物半導體感測器的方法，包括以下步驟。提供具有畫素區和電路區的所述半導體基底。在所述電路區中的所述半導體基底上形成介電圖案。在所述半導體基底上形成介電層以覆蓋所述介電圖案。在所述電路區中的所述介電層上形成內連線。移除所述半導體基底的一部分，以形成第一開口，所述第一開口暴露所述介電圖案。移除所述介電圖案，以在所述第一開口中的所述介電層中形成溝槽，所述溝槽不穿透所述介電層。在所述第一開口中的所述介電層中形 成接合墊，以電連接至所述內連線。在所述溝槽中形成位於所述接合墊旁的虛設圖案。
在一些實施例中，所述半導體基底的一部分和所述介電圖案被同時移除。
在一些實施例中，所述方法更包括在所述介電層中形成至少一個第二開口，以在形成所述接合墊之前暴露所述內連線的一部分，其中所述接合墊通過所述至少一個第二開口電連接至所述內連線。
在一些實施例中，形成所述接合墊和所述虛設圖案包括：在所述半導體基底上共形地形成導電層；以及移除所述導電層的一部分，以形成彼此分離的所述接合墊和所述虛設圖案，其中所述接合墊和所述虛設圖案不會延伸到所述第一開口外。
在一些實施例中，移除所述導電層的一部分的方法包括非等向性蝕刻製程。
在一些實施例中，所述第一開口的側壁與所述溝槽的側壁對齊。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應知，他們可容易地使用本公開作為設計或修改其他過程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在 不背離本公開的精神及範圍的條件下對其作出各種改變、替代及變更。

Claims (10)

  1. 一種互補金屬氧化物半導體感測器，包括：半導體基底，具有畫素區和電路區；介電層，被所述電路區中的所述半導體基底環繞；內連線，設置在所述電路區中的所述介電層上；接合墊，設置在所述電路區中的所述介電層中且電連接至所述內連線；以及虛設圖案，設置在所述電路區中的所述介電層中且環繞所述接合墊，其中所述虛設圖案與所述接合墊分離配置。
  2. 如申請專利範圍第1項所述的互補金屬氧化物半導體感測器，其中所述半導體基底不設置在所述接合墊和所述內連線之間。
  3. 如申請專利範圍第1項所述的互補金屬氧化物半導體感測器，其中所述接合墊和所述虛設圖案被所述半導體基底環繞。
  4. 如申請專利範圍第1項所述的互補金屬氧化物半導體感測器，其中所述虛設圖案設置在所述半導體基底和所述接合墊之間。
  5. 一種互補金屬氧化物半導體感測器，包括：圖案化的半導體基底；圖案化的介電層，其中所述圖案化的介電層由所述圖案化的半導體基底暴露且所述圖案化的介電層在其第一表面處具有至少一個溝槽；內連線，設置在與所述圖案化的介電層的所述第一表面相對的第二表面上；接合墊，設置在所述圖案化的介電層的所述第一表面上且電連接至所述內連線；以及虛設圖案，設置在所述至少一個溝槽內，並設置在所述接合墊旁，其中所述虛設圖案與所述接合墊分離配置。
  6. 如申請專利範圍第5項所述的互補金屬氧化物半導體感測器，更包括絕緣體，其中所述絕緣體設置在所述接合墊和所述圖案化的介電層之間。
  7. 如申請專利範圍第5項所述的互補金屬氧化物半導體感測器，其中相對於所述第二表面，所述虛設圖案的頂面高於所述接合墊的頂面。
  8. 一種形成互補金屬氧化物半導體感測器的方法，包括：提供具有畫素區和電路區的半導體基底；在所述電路區中的所述半導體基底上形成介電圖案；在所述半導體基底上形成介電層以覆蓋所述介電圖案；在所述電路區中的所述介電層上形成內連線；移除所述半導體基底的一部分，以形成第一開口，所述第一開口暴露所述介電圖案；移除所述介電圖案，以在所述第一開口中的所述介電層中形成溝槽，所述溝槽不穿透所述介電層；在所述第一開口中的所述介電層中形成接合墊，以電連接至所述內連線；以及在所述溝槽中形成位於所述接合墊旁的虛設圖案。
  9. 如申請專利範圍第8項所述的方法，其中所述半導體基底的一部分和所述介電圖案被同時移除。
  10. 如申請專利範圍第8項所述的方法，更包括在所述介電層中形成至少一個第二開口，以在形成所述接合墊之前暴露所述內連線的一部分，其中所述接合墊通過所述至少一個第二開口電連接至所述內連線。
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