TWI675475B - 緊湊源極鎮流器mosfet及其製備方法 - Google Patents

緊湊源極鎮流器mosfet及其製備方法 Download PDF

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TWI675475B
TWI675475B TW107113393A TW107113393A TWI675475B TW I675475 B TWI675475 B TW I675475B TW 107113393 A TW107113393 A TW 107113393A TW 107113393 A TW107113393 A TW 107113393A TW I675475 B TWI675475 B TW I675475B
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燮光 雷
馬督兒 博德
繼 潘
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澳門商萬民半導體 (澳門) 有限公司
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Abstract

一種溝槽金屬-氧化物-半導體場效應電晶體（MOSFET）裝置，包括一個第一導電類型的基板，一個第二導電類型的本體區，一個形成在閘極溝槽中的閘極電極，在本體區和基板中延伸，一個輕摻雜源極區和一個形成在本體區中的重摻雜源極區，以及一個延伸到本體區的源極接頭形成在閘極溝槽附近的源極接觸溝槽中。輕摻雜源極區延伸到本體區中比重摻雜源極區更深處。輕摻雜源極區在源極接觸溝槽附近。鎮流電阻器形成在輕摻雜源極區中，在重摻雜源極區和本體區之間，以及一個肖特基二極體形成在源極接頭和輕摻雜源極區之間的接頭處。

Description

緊湊源極鎮流器MOSFET及其製備方法
本發明主要涉及金屬-氧化物-半導體場效應電晶體（MOSFET），更確切地說是用於帶有源極鎮流電阻器的改良溝槽MOSFET結構，及其相同裝置的製備方法。
微處理器和記憶體件等積體電路包括多個金屬-氧化物-半導體場效應電晶體（MOSFET），提供基本的開關功能，以配置邏輯閘極、資料存儲和功率開關等。當MOSFET如圖1A所示並聯，以處理慢開關應用中的大電流時，MOSFET之間的參數失配（例如導通電阻、閾值電壓、通道長度）導致動態電流失衡，從而造成電流扭曲。當較大部分的電流流經多個並聯MOSFET當中的一個時，由於較低的閾值電壓或通道長度，會發生電流扭曲。由於特定的MOSFET消耗了絕大多數的裝置功率，會發生局域化的熱點。較高的溫度進一步降低了該MOSFET的閾值電壓，消耗了更多的功率。最終，會發生熱量逃逸。
眾所周知，本領域中源極鎮流會為反向電流扭曲提供負反饋。因此，為了避免電流扭曲，通常增加一個源極鎮流電阻器，與每個MOSFET串聯，如圖1B所示，以平衡並聯MOSFET中負載電流的分佈。正是在這一前提下，提出了本發明的各種實施例。
爲了解决以上問題，本發明的目的在于提供一種溝槽金屬-氧化物-半導體場效應電晶體（MOSFET）裝置，其包括： a) 一個第一導電類型的基板，基板包括一個第一導電類型的外延層，位於相同導電類型的重摻雜矽晶圓上方； b) 一個第二導電類型的本體區，形成在基板的上方，第二導電類型與第一導電類型相反； c) 一個閘極溝槽，形成在本體區和基板中，其中閘極溝槽內襯電介質層，一個閘極電極形成在閘極溝槽中； d) 一個輕摻雜源極區和一個重摻雜源極區，形成在本體區中，其中輕摻雜源極區延伸到本體區中比重摻雜源極區更深處；以及 e) 一個延伸到本體區的源極接頭，形成在閘極溝槽附近的源極接觸溝槽中，其中輕摻雜源極區在源極接觸溝槽附近，其中肖特基二極體形成在源極接頭和輕摻雜源極區之間的接頭處。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中輕摻雜源極區完全延伸到閘極溝槽和源極接觸溝槽之間。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中重摻雜源極區僅部分延伸到閘極溝槽和源極接觸溝槽之間。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中鎮流電阻器形成在重摻雜源極區和本體區之間的輕摻雜源極區處。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中鎮流電阻器具有長度，其中通過改變重摻雜源極區的深度，可以調節鎮流電阻器的長度。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中鎮流電阻器具有一個寬度，其中鎮流電阻器的寬度可以通過源極接觸溝槽的寬度調節。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中鎮流電阻器具有電阻值，其中電阻值可以通過輕摻雜源極區的摻雜濃度調節。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中本體區的深度D在0.5T至0.8T之間，其中T是閘極溝槽的深度；其中輕摻雜源極區的深度d在0.25D至0.5D之間；並且其中重摻雜源極區的深度在0.25d至0.5d之間。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中源極接觸溝槽具有一個寬度，其中間距在0.5微米(μm)至1.5μm範圍內。
本發明的一種溝槽金屬-氧化物-半導體場效應電晶體裝置，其中輕摻雜源極區的摻雜濃度在1×1015 /cm3 至1×1018 /cm3 之間，重摻雜源極區的摻雜濃度在8×1019 /cm3 至8×1020 /cm3 之間。
本發明的一種製備溝槽MOSFET裝置的方法，其包括： a) 提供一個第一導電類型的基板，其中基板包括一個第一導電類型的外延層，位於相同導電類型的重摻雜矽晶圓上方； b) 在基板中，製備一個閘極溝槽，其中閘極溝槽內襯一個電介質層，以及一個閘極電極形成在閘極溝槽中； c) 在基板中，製備一個第二導電類型的本體區，其中第二導電類型與第一導電類型相反， d) 通過源極注入，在本體區中，製備一個輕摻雜源極區和一個重摻雜源極區，其中輕摻雜源極區延伸到本體區中比重摻雜源極區更深處； e) 在基板上方，通過低溫氧化工藝，製備一個電介質層；並且 f) 製備一個源極接觸溝槽，延伸到本體區，其中源極接頭形成在源極接觸溝槽中，其中輕摻雜源極區在源極接觸溝槽附近。
本發明的一種製備溝槽MOSFET裝置的方法，其中源極注入包括一個深源極注入和一個淺源極注入的組合，其中深源極注入以及淺源極注入的摻雜離子與基板的摻雜離子導電類型相同。
本發明的一種製備溝槽MOSFET裝置的方法，其中用於深源極注入的摻雜離子為磷離子，用於淺源極注入的摻雜離子為砷離子。
本發明的一種製備溝槽MOSFET裝置的方法，其中深源極注入和淺源極注入發生在形成本體區之後,以及形成電介質層之前。
本發明的一種製備溝槽MOSFET裝置的方法，其中深源極注入發生在製備本體區之後，以及製備電介質層之前，淺源極注入發生在形成電介質層之後。
本發明的一種製備溝槽MOSFET裝置的方法，其中肖特基二極體形成在源極接頭和輕摻雜源極區之間的接頭處。
本發明的一種製備溝槽MOSFET裝置的方法，其中輕摻雜源極區完全延伸在閘極溝槽和源極接觸溝槽之間。
本發明的一種製備溝槽MOSFET裝置的方法，其中重摻雜源極區僅部分延伸到閘極溝槽和源極接觸溝槽之間。
本發明的一種製備溝槽MOSFET裝置的方法，其中本體區的深度D在0.5T至0.8T之間，其中T是閘極溝槽的深度；其中輕摻雜源極區的深度d在0.25D至0.5D之間；並且其中重摻雜源極區的深度在0.25d至0.5d之間。
本發明的一種製備溝槽MOSFET裝置的方法，其中輕摻雜源極區的摻雜濃度在1×1015 /cm3 至1×1018 /cm3 範圍內，重摻雜源極區的摻雜濃度在8×1019 /cm3 至8×1020 /cm3 範圍內。
在以下詳細說明中，參照附圖，構成典型實施例的一部分，經過典型實施例的說明，可以實施本發明。為了簡便，在導電性或電荷載流子類型（p或n）的符號之後使用+或-通常是指半導體材料中指定類型的電荷載流子濃度的相對程度。通常來說，定義為n+材料的負電荷載流子（即電子）濃度大於n材料的負電荷載流子濃度，n材料的負電荷載流子濃度大於n-材料的負電荷載流子濃度。與之類似，p+材料的正電荷載流子（即空穴）大於p材料的正電荷載流子濃度，p材料的正電荷載流子濃度大於p-材料的正電荷載流子濃度。要注意的是，有關係的是電荷載流子濃度，而不是摻雜物。例如，金屬可以重摻雜n-型摻雜物，但是如果材料也足夠反摻雜p-型摻雜物，那麼仍然可以具有相對很低的電荷載流子濃度。本文所用的摻雜物濃度小於1016 /cm3 可以稱為“輕摻雜”，摻雜物濃度大於1017 /cm3 可以稱為“重摻雜”。
引 言
人們已經提出了某些設計用於與MOSFET串聯的鎮流電阻器。Worley發明的美國專利號為6,927,458的專利提出了利用鎮流結構，用於CMOS設計中的源極和漏極區，特此引用，以作參考。Hsieh發明的美國專利號7,816,720和Hebert等人發明的美國專利申請號8,703,563都提到了使用源極鎮流電阻器，控制電路的增益，以便當溝槽MOSFET並聯時，分佈地更加均勻，特此引用，以作參考。由於這些設計具有源極鎮流電阻器與MOSFET中的重摻雜源極區平行串聯，因此這些設計中的源極鎮流電阻器將佔據較大的面積。另外，當需要電阻電荷時，都需要新型的佈局/設計。
本發明的各個方面提出了一種帶有接觸源極鎮流結構的溝槽MOSFET裝置的改良結構。確切地說，依據本發明的各個方面，溝槽MOSFET裝置包括一個輕摻雜的源極區，構成在重摻雜源極區和本體區之間的鎮流結構。由於改良了結構，依據本發明的各個方面，可以輕鬆調節溝槽MOSFET中的鎮流電阻。確切地說，通過改變重摻雜源極區的深度，可以調節電阻器長度。通過改變接觸寬度，可以調節電阻器寬度，例如如上所述的接觸溝槽寬度。另外，通過改變輕摻雜源極區的摻雜濃度，可以調節電阻。
實施例
圖2A表示依據本發明的各個方面，一部分溝槽MOSFET裝置的剖面示意圖。圖2B表示圖2A所示溝槽MOSFET裝置的三維圖。隨著所述的其他附圖，所示元件的相對維度和尺寸不會影響實際的維度，僅用於解釋說明。
溝槽MOSFET裝置200從基板210開始。基板210包括一個第一導電類型的外延層，在相同導電類型的重摻雜矽晶圓上方。作為示例，但不作為局限，外延層和矽晶圓可以摻雜任意合適的n-型摻雜物（離子或原子），例如磷或砷。與外延層的摻雜相比，矽晶圓可以重摻雜。基板210用作溝槽MOSFET裝置200的漏極。
第二導電類型的本體區230形成在基板210上方。第二導電類型與第一導電類型相反。在一個實施例中，第一導電類型為n-型，第二導電類型為p-型。本體區230可以摻雜任意合適的p-型摻雜物，例如硼。
閘極溝槽220形成在本體區230中，並且延伸到基板210頂部。閘極溝槽內襯電介質材料222，例如氧化矽。閘極電極224形成在閘極溝槽220中，通過內襯閘極溝槽220的電介質材料222，閘極電極224與本體區230和基板210絕緣。作為示例，但不作為局限，閘極電極224可以由多晶矽或任何其他導電材料製成。
輕摻雜源極區240形成在本體區230的頂部，如圖2所示。源極區240可以輕摻雜與基板210相同導電類型的摻雜物。作為示例，但不作為局限，輕摻雜源極區240的摻雜濃度可以從1×1015 /cm3 至1×1018 /cm3 範圍內。
重摻雜源極區250形成在輕摻雜源極區240上方。源極區250可以重摻雜與基板210相同導電類型的摻雜物。作為示例，但不作為局限，這些源極區250可以摻雜n+型，用於n型基板210。在圖2A-2B所示的實施例中，重摻雜源極區250延展到閘極溝槽220和源極接觸溝槽270之間的區域寬度。
電介質層260形成在重摻雜源極區250上方。源極金屬墊280位於電介質層260上方。源極接觸溝槽270中的源極接頭272還將源極金屬墊280連接到本體區230。源極金屬墊280和源極接頭272用作源極墊，提供到溝槽MOSFET裝置200的源極區250的外部接頭。
依據上述結構，鎮流結構形成在重摻雜源極區250和本體區230之間的輕摻雜源極區240處。另外，肖特基二極體形成在輕摻雜源極區240和源極接頭272之間的接頭處，如圖2所示，歐姆接觸形成在重摻雜源極區和源極接頭272之間的接頭處。由於形成肖特基二極體用於源極-本體短路，因此通道電流流經輕摻雜源極區到重摻雜源極區，平行於溝槽的方向。依據本發明的各個方面，可以輕鬆調節溝槽MOSFET中的鎮流電阻。確切地說，通過改變重摻雜源極區的深度，可以調節電阻器長度。通過改變接頭寬度，可以調節電阻器寬度。另外，通過改變輕摻雜源極區的摻雜濃度，可以調節電阻。
圖3A表示依據本發明的各個方面，一部分溝槽MOSFET裝置的剖面示意圖。圖3B表示圖3A所示溝槽MOSFET裝置的三維圖。在圖3A或3B所示的溝槽MOSFET裝置300中，重摻雜源極區250’形成在源極接觸溝槽270附近的輕摻雜區240中。在本實施例中，重摻雜源極區250’沒有擴展到閘極溝槽220和源極接觸溝槽270之間區域的整個寬度上。除此之外，圖3A所示的MOSFET裝置300的結構類似於圖2A所示的MOSFET裝置200的結構，因此為了簡便，這些結構的詳細說明不再贅述。
圖4A-4J表示圖2A所示的溝槽MOSFET 200的製備工藝的剖面圖，溝槽MOSFET 200具有一個輕摻雜源極區，在重摻雜源極區和本體區之間。
參見圖4A，該工藝使用一個第一導電類型的半導體基板410，作為初始材料。在一些實施例中，基板410包括一個N-型外延層，在重摻雜N型（N+）矽晶圓上方。在基板410上使用一個掩膜（圖中沒有表示出來），該掩膜包括限定多個閘極溝槽位置的開口，用於MOSFET裝置200的溝槽電晶體。在圖4A中，進行刻蝕工藝，刻蝕掉下方基板410相應的位置，構成多個閘極溝槽420。一旦形成溝槽420之後，就除去掩膜，生長一個犧牲氧化層（圖中沒有表示出來）然後除去，以改良矽表面。
參見圖4B，沿閘極溝槽420的內表面，形成一個絕緣層（例如閘極氧化物）422。在圖4C中，在閘極氧化層422上方，放置導電材料。在一些實施例中，導電材料可以是原位摻雜的或未摻雜的多晶矽。因此，如圖4D所示，在基板410上方的導電材料上進行回刻工藝之後，為每一個溝槽電晶體製備一個閘極電極424。
參見圖4E，進行全面本體注入，形成本體區430。摻雜離子的導電類型與基板410的摻雜導電類型相同。在一些實施例中，對於N-通道裝置來說，摻雜離子可以是硼離子。在一些實施例中，對於P-通道裝置來說，可以使用磷或砷離子。此後，進行熱擴散，啟動摻雜原子，驅使摻雜擴散，形成本體區430。
參見圖4F，進行源極注入。確切地說，源極注入可以是深磷（N-）注入和淺砷（N+）注入的結合。然後進行源極區擴散，在本體區430中形成一個輕摻雜源極區440，比重摻雜源極區450更深，如圖4G所示。作為示例，但不作為局限，輕摻雜源極區440的摻雜濃度在1×1015 /cm3 至1×1018 /cm3 範圍內，同時重摻雜源極區450的摻雜濃度在8×1019 /cm3 至8×1020 /cm3 範圍內。作為示例，但不作為局限，輕摻雜源極區440可以在本體區430和重摻雜源極區450之間延伸。本體區430的深度可以在0.5T至0.8T範圍內，其中T是閘極溝槽420的深度。輕摻雜區440的深度d可以在0.25D至0.5D範圍內。重摻雜源極區450的深度可以在0.25d至0.5d範圍內。通過控制注入能量，通常使用10keV至500keV範圍內的注入能量，可以控制各個區域的深度。
然後，如圖4H所示，在基板410上方放置一個極化電介質層460。在一些實施例中，通過低溫氧化沉積，隨後沉積含有硼酸的矽玻璃（BPSG），形成電介質層460。
在電介質層460上使用光致抗蝕劑（圖中沒有表示出來），電介質層460帶有圖案，在接觸溝槽的位置上具有一個開口。進行刻蝕工藝，除去電介質層460未被覆蓋的部分，通過本體區420內的源極區430，形成接觸溝槽470，如圖4I所示。作為示例，但不作為局限，接觸溝槽470的寬度在0.5μm至1.5μm範圍內。
在電介質層460上方，放置一個金屬層480。通過導電材料填充接觸開口，在每個源極接觸溝槽470中形成一個源極接頭472。金屬層480和源極接頭472互連所有的源極區，形成溝槽MOSFET裝置200，帶有MOS電晶體並聯。
圖5A-5L表示圖3A所示溝槽MOSFET 300的製備工藝剖面圖，溝槽MOSFET 300具有一個重摻雜源極區，在源極接觸溝槽附近的輕摻雜源極區中。
參見圖5A，該工藝使用第一導電類型的半導體基板510作為初始材料。在一些實施例中，基板510可能包括一個N-型外延層，在重摻雜N型（N+）矽晶圓上方。在基板510上使用一個掩膜（圖中沒有表示出來），掩膜包括限定多個閘極溝槽位置的開口，用於MOSFET裝置300的溝槽電晶體。在圖5A中，進行刻蝕工藝，刻蝕掉下方基板510相應的部分，以形成多個閘極溝槽520。一旦形成溝槽520之後，就除去掩膜，生長一個犧牲氧化層（圖中沒有表示出來）然後除去，以改良矽表面。
參見圖5B，沿閘極溝槽520的內表面，形成一個絕緣層（例如閘極氧化物）522。在圖5C中，在閘極氧化層522上方，放置導電材料。在一些實施例中，導電材料可以是原位摻雜的或未摻雜的多晶矽。因此，如圖5D所示，在基板510上方的導電材料上進行回刻工藝之後，為每一個溝槽電晶體製備一個閘極電極524。
參見圖5E，進行全面本體注入，形成本體區530。摻雜離子的導電類型與基板510的摻雜導電類型相反。在一些實施例中，對於N-通道裝置來說，摻雜離子可以是硼離子。在一些實施例中，對於P-通道裝置來說，可以使用磷或砷離子。此後，進行熱擴散，啟動摻雜原子，驅使摻雜擴散，形成本體區530。
參見圖5F，進行源極注入。摻雜離子的導電類型與基板510的摻雜導電類型相同。在一些實施例中，對於N-通道裝置來說，可以注入磷離子。隨後進行源極區擴散，形成輕摻雜源極區540，如圖5G所示。作為示例，但不作為局限，輕摻雜源極區540的摻雜濃度在1×1015 /cm3 至1×1018 /cm3 範圍內。通過控制注入能量，通常使用10keV至500keV範圍內的注入能量，可以控制各個區域的深度。
然後，如圖5H所示，在基板510上方放置一個極化電介質層560。在一些實施例中，通過低溫氧化沉積，隨後沉積含有硼酸的矽玻璃（BPSG），形成電介質層560。
在電介質層560上，使用接觸光致抗蝕劑（圖中沒有表示出來），帶有圖案，在接觸溝槽的位置處具有一個開口。進行刻蝕工藝除去未被覆蓋的電介質層560，如圖5I所示。
在圖5J中，進行淺源極注入，隨後退火，用於水準擴散，形成重摻雜源極區550。摻雜離子的導電類型與基板510的摻雜導電類型相同。在一些實施例中，對於N-通道裝置來說，摻雜離子可以是砷離子。作為示例，但不作為局限，重摻雜源極區550的摻雜濃度在8×1019 /cm3 至8×1020 /cm3 範圍內。本體區530的深度D在0.5T至0.8T之間，其中T是閘極溝槽520的深度。輕摻雜區540的深度d在0.25D至0.5D之間。源極區550的深度在0.25d至0.5d之間。
參見圖5K，進行另一個刻蝕工藝，通過刻蝕本體區530中的源極接觸開口，形成源極接觸溝槽570。作為示例，但不作為局限，接觸溝槽570的寬度在0.5μm至1.5μm範圍內。在電介質層560上方放置一個金屬層580。通過用導電材料填充接觸開口，在每個源極接觸溝槽570中，形成一個源極接頭572。金屬層580和源極接頭572互連所有的源極區，形成溝槽MOSFET裝置300，帶有MOS電晶體並聯。
儘管本發明關於某些較佳的版本已經做了詳細的敘述，但是仍可能存在其他版本。因此，本發明的範圍不應由上述說明決定，與之相反，本發明的範圍應參照所附的權利要求書及其全部等效內容。任何可選件（無論首選與否），都可與其他任何可選件（無論首選與否）組合。在以下權利要求中，除非特別聲明，否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個專案的數量。除非用“意思是”明確指出限定功能，否則所附的權利要求書並不應認為是意義和功能的局限。
210‧‧‧基板
220‧‧‧閘極溝槽
222‧‧‧電介質材料
224‧‧‧閘極電極
230‧‧‧本體區
240‧‧‧輕摻雜源極區
250‧‧‧重摻雜源極區
260‧‧‧電介質層
270‧‧‧源極接觸溝槽
272‧‧‧源極接頭
280‧‧‧源極金屬墊
410‧‧‧基板
420‧‧‧閘極溝槽
422‧‧‧閘極氧化層
424‧‧‧閘極電極
430‧‧‧本體區
440‧‧‧輕摻雜源極區
450‧‧‧重摻雜源極區
460‧‧‧電介質層
470‧‧‧接觸溝槽
472‧‧‧源極接頭
480‧‧‧金屬層
510‧‧‧基板
520‧‧‧溝槽
522‧‧‧閘極氧化層
524‧‧‧閘極電極
530‧‧‧本體區
540‧‧‧輕摻雜源極區
550‧‧‧重摻雜源極區
560‧‧‧電介質層
570‧‧‧源極接觸溝槽
572‧‧‧源極接頭
580‧‧‧金屬層
閱讀以下詳細說明並參照以下附圖之後，本發明的其他特徵和優勢將顯而易見：
圖1A表示並聯MOSFET的示意圖。 圖1B表示並聯MOSFET的示意圖，並聯MOSFET具有一個源極鎮流電阻器，與每個MOSFET串聯。 圖2A表示依據本發明的各個方面，一部分溝槽MOSFET裝置的剖面示意圖。 圖2B表示圖2A所示溝槽MOSFET裝置的三維圖。 圖3A表示依據本發明的各個方面，一部分溝槽MOSFET裝置的剖面示意圖。 圖3B表示圖3A所示溝槽MOSFET裝置的三維圖。 圖4A-4J表示依據本發明的各個方面，圖2A所示溝槽MOSFET裝置製備方法的剖面示意圖。 圖5A-5L表示依據本發明的各個方面，圖3A所示溝槽MOSFET裝置製備方法的剖面示意圖。

Claims (19)

  1. 一種溝槽金屬-氧化物-半導體場效應電晶體(MOSFET)裝置，其包括：a)一個第一導電類型的基板，基板包括一個第一導電類型的外延層，位於相同導電類型的重摻雜矽晶圓上方；b)一個第二導電類型的本體區，形成在基板的上方，第二導電類型與第一導電類型相反；c)一個閘極溝槽，形成在本體區和基板中，其中閘極溝槽內襯電介質層，一個閘極電極形成在閘極溝槽中；d)一個輕摻雜源極區和一個重摻雜源極區，形成在本體區中，其中輕摻雜源極區延伸到本體區中比重摻雜源極區更深處；以及e)一個延伸到本體區的源極接頭，形成在閘極溝槽附近的源極接觸溝槽中，其中輕摻雜源極區在源極接觸溝槽附近，其中肖特基二極體形成在源極接頭和輕摻雜源極區之間的接頭處；其中鎮流電阻器形成在重摻雜源極區和本體區之間的輕摻雜源極區處。
  2. 如申請專利範圍第1項所述之裝置，其中輕摻雜源極區完全延伸到閘極溝槽和源極接觸溝槽之間。
  3. 如申請專利範圍第1項所述之裝置，其中重摻雜源極區僅部分延伸到閘極溝槽和源極接觸溝槽之間。
  4. 如申請專利範圍第1項所述之裝置，其中鎮流電阻器具有長度，其中通過改變重摻雜源極區的深度，可以調節鎮流電阻器的長度。
  5. 如申請專利範圍第1項所述之裝置，其中鎮流電阻器具有一個寬 度，其中鎮流電阻器的寬度可以通過源極接觸溝槽的寬度調節。
  6. 如申請專利範圍第1項所述之裝置，其中鎮流電阻器具有電阻值，其中電阻值可以通過輕摻雜源極區的摻雜濃度調節。
  7. 如申請專利範圍第1項所述之裝置，其中本體區的深度D在0.5T至0.8T之間，其中T是閘極溝槽的深度；其中輕摻雜源極區的深度d在0.25D至0.5D之間；並且其中重摻雜源極區的深度在0.25d至0.5d之間。
  8. 如申請專利範圍第1項所述之裝置，其中源極接觸溝槽具有一個寬度，其中間距在0.5μm至1.5μm範圍內。
  9. 如申請專利範圍第1項所述之裝置，其中輕摻雜源極區的摻雜濃度在1×1015/cm3至1×1018/cm3之間，重摻雜源極區的摻雜濃度在8×1019/cm3至8×1020/cm3之間。
  10. 一種製備溝槽MOSFET裝置的方法，其包括：a)提供一個第一導電類型的基板，其中基板包括一個第一導電類型的外延層，位於相同導電類型的重摻雜矽晶圓上方；b)在基板中，製備一個閘極溝槽，其中閘極溝槽內襯一個電介質層，以及一個閘極電極形成在閘極溝槽中；c)在基板中，製備一個第二導電類型的本體區，其中第二導電類型與第一導電類型相反，d)通過源極注入，在本體區中，製備一個輕摻雜源極區和一個重摻雜源極區，其中輕摻雜源極區延伸到本體區中比重摻雜源極區更深處；e)在基板上方，通過低溫氧化工藝，製備一個電介質層；並且f)製備一個源極接觸溝槽，延伸到本體區，其中源極接頭形成在源極接觸溝 槽中，其中輕摻雜源極區在源極接觸溝槽附近；其中鎮流電阻器形成在重摻雜源極區和本體區之間的輕摻雜源極區處。
  11. 如申請專利範圍第10項所述之方法，其中源極注入包括一個深源極注入和一個淺源極注入的組合，其中深源極注入以及淺源極注入的摻雜離子與基板的摻雜離子導電類型相同。
  12. 如申請專利範圍第11項所述之方法，其中用於深源極注入的摻雜離子為磷離子，用於淺源極注入的摻雜離子為砷離子。
  13. 如申請專利範圍第11項所述之方法，其中深源極注入和淺源極注入發生在形成本體區之後，以及形成電介質層之前。
  14. 如申請專利範圍第11項所述之方法，其中深源極注入發生在製備本體區之後，以及製備電介質層之前，淺源極注入發生在形成電介質層之後。
  15. 如申請專利範圍第10項所述之方法，其中肖特基二極體形成在源極接頭和輕摻雜源極區之間的接頭處。
  16. 如申請專利範圍第10項所述之方法，其中輕摻雜源極區完全延伸在閘極溝槽和源極接觸溝槽之間。
  17. 如申請專利範圍第10項所述之方法，其中重摻雜源極區僅部分延伸到閘極溝槽和源極接觸溝槽之間。
  18. 如申請專利範圍第10項所述之方法，其中本體區的深度D在0.5T至0.8T之間，其中T是閘極溝槽的深度；其中輕摻雜源極區的深度d在0.25D至0.5D之間；並且其中重摻雜源極區的深度在0.25d至0.5d之間。
  19. 如申請專利範圍第10項所述之方法，其中輕摻雜源極區的摻雜濃度在1×1015/cm3至1×1018/cm3範圍內，重摻雜源極區的摻雜濃度在8×1019/cm3至 8×1020/cm3範圍內。
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