CN108807539A - 紧凑源极镇流器mosfet及其制备方法 - Google Patents

紧凑源极镇流器mosfet及其制备方法 Download PDF

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CN108807539A
CN108807539A CN201810312715.9A CN201810312715A CN108807539A CN 108807539 A CN108807539 A CN 108807539A CN 201810312715 A CN201810312715 A CN 201810312715A CN 108807539 A CN108807539 A CN 108807539A
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source
polar region
doped
lightly
body zone
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雷燮光
马督儿·博德
潘继
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NATIONS SEMICONDUCTOR (CAYMAN) Ltd
Alpha and Omega Semiconductor Cayman Ltd
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NATIONS SEMICONDUCTOR (CAYMAN) Ltd
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Abstract

一种沟槽金属‑氧化物‑半导体场效应晶体管(MOSFET)器件，包括一个第一导电类型的衬底，一个第二导电类型的本体区，一个形成在栅极沟槽中的栅极电极，在本体区和衬底中延伸，一个轻掺杂源极区和一个形成在本体区中的重掺杂源极区，以及一个延伸到本体区的源极接头形成在栅极沟槽附近的源极接触沟槽中。轻掺杂源极区延伸到本体区中比重掺杂源极区更深处。轻掺杂源极区在源极接触沟槽附近。镇流电阻器形成在轻掺杂源极区中，在重掺杂源极区和本体区之间，以及一个肖特基二极管形成在源极接头和轻掺杂源极区之间的接头处。

Description

紧凑源极镇流器MOSFET及其制备方法
技术领域
本发明主要涉及金属-氧化物-半导体场效应晶体管(MOSFET)，更确切地说是用于带有源极镇流电阻器的改良沟槽MOSFET结构，及其相同器件的制备方法。
背景技术
微处理器和存储器件等集成电路包括多个金属-氧化物-半导体场效应晶体管(MOSFET)，提供基本的开关功能，以配置逻辑栅极、数据存储和功率开关等。当MOSFET如图1A所示并联，以处理慢开关应用中的大电流时，MOSFET之间的参数失配(例如导通电阻、阈值电压、通道长度)导致动态电流失衡，从而造成电流扭曲。当较大部分的电流流经多个并联MOSFET当中的一个时，由于较低的阈值电压或通道长度，会发生电流扭曲。由于特定的MOSFET消耗了绝大多数的器件功率，会发生局域化的热点。较高的温度进一步降低了该MOSFET的阈值电压，消耗了更多的功率。最终，会发生热量逃逸。
众所周知，本领域中源极镇流会为反向电流扭曲提供负反馈。因此，为了避免电流扭曲，通常增加一个源极镇流电阻器，与每个MOSFET串联，如图1B所示，以平衡并联MOSFET中负载电流的分布。正是在这一前提下，提出了本发明的各种实施例。
发明内容
为了解决以上问题，本发明的目的在于提供一种沟槽金属-氧化物-半导体场效应电晶体(MOSFET)器件，其包括：
a)一个第一导电类型的衬底，衬底包括一个第一导电类型的外延层，位于相同导电类型的重掺杂硅晶圆上方；
b)一个第二导电类型的本体区，形成在衬底的上方，第二导电类型与第一导电类型相反；
c)一个栅极沟槽，形成在本体区和衬底中，其中栅极沟槽内衬电介质层，一个栅极电极形成在栅极沟槽中；
d)一个轻掺杂源极区和一个重掺杂源极区，形成在本体区中，其中轻掺杂源极区延伸到本体区中比重掺杂源极区更深处；以及
e)一个延伸到本体区的源极接头，形成在栅极沟槽附近的源极接触沟槽中，其中轻掺杂源极区在源极接触沟槽附近，其中肖特基二极体形成在源极接头和轻掺杂源极区之间的接头处。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中轻掺杂源极区完全延伸到栅极沟槽和源极接触沟槽之间。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中重掺杂源极区仅部分延伸到栅极沟槽和源极接触沟槽之间。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中镇流电阻器形成在重掺杂源极区和本体区之间的轻掺杂源极区处。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中镇流电阻器具有长度，其中通过改变重掺杂源极区的深度，可以调节镇流电阻器的长度。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中镇流电阻器具有一个宽度，其中镇流电阻器的宽度可以通过源极接触沟槽的宽度调节。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中镇流电阻器具有电阻值，其中电阻值可以通过轻掺杂源极区的掺杂浓度调节。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中本体区的深度D在0.5T至0.8T之间，其中T是栅极沟槽的深度；其中轻掺杂源极区的深度d在0.25D至0.5D之间；并且其中重掺杂源极区的深度在0.25d至0.5d之间。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中源极接触沟槽具有一个宽度，其中间距在0.5μm至1.5μm范围内。
本发明的一种沟槽金属-氧化物-半导体场效应电晶体器件，其中轻掺杂源极区的掺杂浓度在1×1015/cm3至1×1018/cm3之间，重掺杂源极区的掺杂浓度在8×1019/cm3至8×1020/cm3之间。
本发明的一种制备沟槽MOSFET器件的方法，其包括：
a)提供一个第一导电类型的衬底，其中衬底包括一个第一导电类型的外延层，位于相同导电类型的重掺杂硅晶圆上方；
b)在衬底中，制备一个栅极沟槽，其中栅极沟槽内衬一个电介质层，以及一个栅极电极形成在栅极沟槽中；
c)在衬底中，制备一个第二导电类型的本体区，其中第二导电类型与第一导电类型相反，
d)通过源极注入，在本体区中，制备一个轻掺杂源极区和一个重掺杂源极区，其中轻掺杂源极区延伸到本体区中比重掺杂源极区更深处；
e)在衬底上方，通过低温氧化工艺，制备一个电介质层；并且
f)制备一个源极接触沟槽，延伸到本体区，其中源极接头形成在源极接触沟槽中，其中轻掺杂源极区在源极接触沟槽附近。
本发明的一种制备沟槽MOSFET器件的方法，其中源极注入包括一个深源极注入和一个浅源极注入的组合，其中深源极注入以及浅源极注入的掺杂离子与衬底的掺杂离子导电类型相同。
本发明的一种制备沟槽MOSFET器件的方法，其中用于深源极注入的掺杂离子为磷离子，用于浅源极注入的掺杂离子为砷离子。
本发明的一种制备沟槽MOSFET器件的方法，其中深源极注入和浅源极注入发生在形成本体区之后,以及形成电介质层之前。
本发明的一种制备沟槽MOSFET器件的方法，其中深源极注入发生在制备本体区之后，以及制备电介质层之前，浅源极注入发生在形成电介质层之后。
本发明的一种制备沟槽MOSFET器件的方法，其中肖特基二极体形成在源极接头和轻掺杂源极区之间的接头处。
本发明的一种制备沟槽MOSFET器件的方法，其中轻掺杂源极区完全延伸在栅极沟槽和源极接触沟槽之间。
本发明的一种制备沟槽MOSFET器件的方法，其中重掺杂源极区仅部分延伸到栅极沟槽和源极接触沟槽之间。
本发明的一种制备沟槽MOSFET器件的方法，其中本体区的深度D在0.5T至0.8T之间，其中T是栅极沟槽的深度；其中轻掺杂源极区的深度d在0.25D至0.5D之间；并且其中重掺杂源极区的深度在0.25d至0.5d之间。
本发明的一种制备沟槽MOSFET器件的方法，其中轻掺杂源极区的掺杂浓度在1×1015/cm3至1×1018/cm3范围内，重掺杂源极区的掺杂浓度在8×1019/cm3至8×1020/cm3范围内。
附图说明
阅读以下详细说明并参照以下附图之后，本发明的其他特征和优势将显而易见：
图1A表示并联MOSFET的示意图。
图1B表示并联MOSFET的示意图，并联MOSFET具有一个源极镇流电阻器，与每个MOSFET串联。
图2A表示依据本发明的各个方面，一部分沟槽MOSFET器件的剖面示意图。
图2B表示图2A所示沟槽MOSFET器件的三维图。
图3A表示依据本发明的各个方面，一部分沟槽MOSFET器件的剖面示意图。
图3B表示图3A所示沟槽MOSFET器件的三维图。
图4A-4J表示依据本发明的各个方面，图2A所示沟槽MOSFET器件制备方法的剖面示意图。
图5A-5L表示依据本发明的各个方面，图3A所示沟槽MOSFET器件制备方法的剖面示意图。
具体实施方式
在以下详细说明中，参照附图，构成典型实施例的一部分，经过典型实施例的说明，可以实施本发明。为了简便，在导电性或电荷载流子类型(p或n)的符号之后使用+或-通常是指半导体材料中指定类型的电荷载流子浓度的相对程度。通常来说，定义为n+材料的负电荷载流子(即电子)浓度大于n材料的负电荷载流子浓度，n材料的负电荷载流子浓度大于n-材料的负电荷载流子浓度。与之类似，p+材料的正电荷载流子(即空穴)大于p材料的正电荷载流子浓度，p材料的正电荷载流子浓度大于p-材料的正电荷载流子浓度。要注意的是，有关系的是电荷载流子浓度，而不是掺杂物。例如，金属可以重掺杂n-型掺杂物，但是如果材料也足够反掺杂p-型掺杂物，那么仍然可以具有相对很低的电荷载流子浓度。本文所用的掺杂物浓度小于1016/cm3可以称为“轻掺杂”，掺杂物浓度大于1017/cm3可以称为“重掺杂”。
引言
人们已经提出了某些设计用于与MOSFET串联的镇流电阻器。Worley发明的美国专利号为6,927,458的专利提出了利用镇流结构，用于CMOS设计中的源极和漏极区，特此引用，以作参考。Hsieh发明的美国专利号7,816,720和Hebert等人发明的美国专利申请号8,703,563都提到了使用源极镇流电阻器，控制电路的增益，以便当沟槽MOSFET并联时，分布地更加均匀，特此引用，以作参考。由于这些设计具有源极镇流电阻器与MOSFET中的重掺杂源极区平行串联，因此这些设计中的源极镇流电阻器将占据较大的面积。另外，当需要电阻电荷时，都需要新型的布局/设计。
本发明的各个方面提出了一种带有接触源极镇流结构的沟槽MOSFET器件的改良结构。确切地说，依据本发明的各个方面，沟槽MOSFET器件包括一个轻掺杂的源极区，构成在重掺杂源极区和本体区之间的镇流结构。由于改良了结构，依据本发明的各个方面，可以轻松调节沟槽MOSFET中的镇流电阻。确切地说，通过改变重掺杂源极区的深度，可以调节电阻器长度。通过改变接触宽度，可以调节电阻器宽度，例如如上所述的接触沟槽宽度。另外，通过改变轻掺杂源极区的掺杂浓度，可以调节电阻。
实施例
图2A表示依据本发明的各个方面，一部分沟槽MOSFET器件的剖面示意图。图2B表示图2A所示沟槽MOSFET器件的三维图。随着所述的其他附图，所示元件的相对维度和尺寸不会影响实际的维度，仅用于解释说明。
沟槽MOSFET器件200从衬底210开始。衬底210包括一个第一导电类型的外延层，在相同导电类型的重掺杂硅晶圆上方。作为示例，但不作为局限，外延层和硅晶圆可以掺杂任意合适的n-型掺杂物(离子或原子)，例如磷或砷。与外延层的掺杂相比，硅晶圆可以重掺杂。衬底210用作沟槽MOSFET器件200的漏极。
第二导电类型的本体区230形成在衬底210上方。第二导电类型与第一导电类型相反。在一个实施例中，第一导电类型为n-型，第二导电类型为p-型。本体区230可以掺杂任意合适的p-型掺杂物，例如硼。
栅极沟槽220形成在本体区230中，并且延伸到衬底210顶部。栅极沟槽内衬电介质材料222，例如氧化硅。栅极电极224形成在栅极沟槽220中，通过内衬栅极沟槽220的电介质材料222，栅极电极224与本体区230和衬底210绝缘。作为示例，但不作为局限，栅极电极224可以由多晶硅或任何其他导电材料制成。
轻掺杂源极区240形成在本体区230的顶部，如图2所示。源极区240可以轻掺杂与衬底210相同导电类型的掺杂物。作为示例，但不作为局限，轻掺杂源极区240的掺杂浓度可以从1×1015/cm3至1×1018/cm3范围内。
重掺杂源极区250形成在轻掺杂源极区240上方。源极区250可以重掺杂与衬底210相同导电类型的掺杂物。作为示例，但不作为局限，这些源极区250可以掺杂n+型，用于n型衬底210。在图2A-2B所示的实施例中，重掺杂源极区250延展到栅极沟槽220和源极接触沟槽270之间的区域宽度。
电介质层260形成在重掺杂源极区250上方。源极金属垫280位于电介质层260上方。源极接触沟槽270中的源极接头272还将源极金属垫280连接到本体区230。源极金属垫280和源极接头272用作源极垫，提供到沟槽MOSFET器件200的源极区250的外部接头。
依据上述结构，镇流结构形成在重掺杂源极区250和本体区230之间的轻掺杂源极区240处。另外，肖特基二极管形成在轻掺杂源极区240和源极接头272之间的接头处，如图2所示，欧姆接触形成在重掺杂源极区和源极接头272之间的接头处。由于形成肖特基二极管用于源极-本体短路，因此通道电流流经轻掺杂源极区到重掺杂源极区，平行于沟槽的方向。依据本发明的各个方面，可以轻松调节沟槽MOSFET中的镇流电阻。确切地说，通过改变重掺杂源极区的深度，可以调节电阻器长度。通过改变接头宽度，可以调节电阻器宽度。另外，通过改变轻掺杂源极区的掺杂浓度，可以调节电阻。
图3A表示依据本发明的各个方面，一部分沟槽MOSFET器件的剖面示意图。图3B表示图3A所示沟槽MOSFET器件的三维图。在图3A或3B所示的沟槽MOSFET器件300中，重掺杂源极区250’形成在源极接触沟槽270附近的轻掺杂区240中。在本实施例中，重掺杂源极区250’没有扩展到栅极沟槽220和源极接触沟槽270之间区域的整个宽度上。除此之外，图3A所示的MOSFET器件300的结构类似于图2A所示的MOSFET器件200的结构，因此为了简便，这些结构的详细说明不再赘述。
图4A-4J表示图2A所示的沟槽MOSFET 200的制备工艺的剖面图，沟槽MOSFET 200具有一个轻掺杂源极区，在重掺杂源极区和本体区之间。
参见图4A，该工艺使用一个第一导电类型的半导体衬底410，作为初始材料。在一些实施例中，衬底410包括一个N-型外延层，在重掺杂N型(N+)硅晶圆上方。在衬底410上使用一个掩膜(图中没有表示出来)，该掩膜包括限定多个栅极沟槽位置的开口，用于MOSFET器件200的沟槽晶体管。在图4A中，进行刻蚀工艺，刻蚀掉下方衬底410相应的位置，构成多个栅极沟槽420。一旦形成沟槽420之后，就除去掩膜，生长一个牺牲氧化层(图中没有表示出来)然后除去，以改良硅表面。
参见图4B，沿栅极沟槽420的内表面，形成一个绝缘层(例如栅极氧化物)422。在图4C中，在栅极氧化层422上方，放置导电材料。在一些实施例中，导电材料可以是原位掺杂的或未掺杂的多晶硅。因此，如图4D所示，在衬底410上方的导电材料上进行回刻工艺之后，为每一个沟槽晶体管制备一个栅极电极424。
参见图4E，进行全面本体注入，形成本体区430。掺杂离子的导电类型与衬底410的掺杂导电类型相同。在一些实施例中，对于N-通道器件来说，掺杂离子可以是硼离子。在一些实施例中，对于P-通道器件来说，可以使用磷或砷离子。此后，进行热扩散，激活掺杂原子，驱使掺杂扩散，形成本体区430。
参见图4F，进行源极注入。确切地说，源极注入可以是深磷(N-)注入和浅砷(N+)注入的结合。然后进行源极区扩散，在本体区430中形成一个轻掺杂源极区440，比重掺杂源极区450更深，如图4G所示。作为示例，但不作为局限，轻掺杂源极区440的掺杂浓度在1×1015/cm3至1×1018/cm3范围内，同时重掺杂源极区450的掺杂浓度在8×1019/cm3至8×1020/cm3范围内。作为示例，但不作为局限，轻掺杂源极区440可以在本体区430和重掺杂源极区450之间延伸。本体区430的深度可以在0.5T至0.8T范围内，其中T是栅极沟槽420的深度。轻掺杂区440的深度d可以在0.25D至0.5D范围内。重掺杂源极区450的深度可以在0.25d至0.5d范围内。通过控制注入能量，通常使用10keV至500keV范围内的注入能量，可以控制各个区域的深度。
然后，如图4H所示，在衬底410上方放置一个极化电介质层460。在一些实施例中，通过低温氧化沉积，随后沉积含有硼酸的硅玻璃(BPSG)，形成电介质层460。
在电介质层460上使用光致抗蚀剂(图中没有表示出来)，电介质层460带有图案，在接触沟槽的位置上具有一个开口。进行刻蚀工艺，除去电介质层460未被覆盖的部分，通过本体区420内的源极区430，形成接触沟槽470，如图4I所示。作为示例，但不作为局限，接触沟槽470的宽度在0.5μm至1.5μm范围内。
在电介质层460上方，放置一个金属层480。通过导电材料填充接触开口，在每个源极接触沟槽470中形成一个源极接头472。金属层480和源极接头472互连所有的源极区，形成沟槽MOSFET器件200，带有MOS晶体管并联。
图5A-5L表示图3A所示沟槽MOSFET 300的制备工艺剖面图，沟槽MOSFET 300具有一个重掺杂源极区，在源极接触沟槽附近的轻掺杂源极区中。
参见图5A，该工艺使用第一导电类型的半导体衬底510作为初始材料。在一些实施例中，衬底510可能包括一个N-型外延层，在重掺杂N型(N+)硅晶圆上方。在衬底510上使用一个掩膜(图中没有表示出来)，掩膜包括限定多个栅极沟槽位置的开口，用于MOSFET器件300的沟槽晶体管。在图5A中，进行刻蚀工艺，刻蚀掉下方衬底510相应的部分，以形成多个栅极沟槽520。一旦形成沟槽520之后，就除去掩膜，生长一个牺牲氧化层(图中没有表示出来)然后除去，以改良硅表面。
参见图5B，沿栅极沟槽520的内表面，形成一个绝缘层(例如栅极氧化物)522。在图5C中，在栅极氧化层522上方，放置导电材料。在一些实施例中，导电材料可以是原位掺杂的或未掺杂的多晶硅。因此，如图5D所示，在衬底510上方的导电材料上进行回刻工艺之后，为每一个沟槽晶体管制备一个栅极电极524。
参见图5E，进行全面本体注入，形成本体区530。掺杂离子的导电类型与衬底510的掺杂导电类型相反。在一些实施例中，对于N-通道器件来说，掺杂离子可以是硼离子。在一些实施例中，对于P-通道器件来说，可以使用磷或砷离子。此后，进行热扩散，激活掺杂原子，驱使掺杂扩散，形成本体区530。
参见图5F，进行源极注入。掺杂离子的导电类型与衬底510的掺杂导电类型相同。在一些实施例中，对于N-通道器件来说，可以注入磷离子。随后进行源极区扩散，形成轻掺杂源极区540，如图5G所示。作为示例，但不作为局限，轻掺杂源极区540的掺杂浓度在1×1015/cm3至1×1018/cm3范围内。通过控制注入能量，通常使用10keV至500keV范围内的注入能量，可以控制各个区域的深度。
然后，如图5H所示，在衬底510上方放置一个极化电介质层560。在一些实施例中，通过低温氧化沉积，随后沉积含有硼酸的硅玻璃(BPSG)，形成电介质层560。
在电介质层560上，使用接触光致抗蚀剂(图中没有表示出来)，带有图案，在接触沟槽的位置处具有一个开口。进行刻蚀工艺除去未被覆盖的电介质层560，如图5I所示。
在图5J中，进行浅源极注入，随后退火，用于水平扩散，形成重掺杂源极区550。掺杂离子的导电类型与衬底510的掺杂导电类型相同。在一些实施例中，对于N-通道器件来说，掺杂离子可以是砷离子。作为示例，但不作为局限，重掺杂源极区550的掺杂浓度在8×1019/cm3至8×1020/cm3范围内。本体区530的深度D在0.5T至0.8T之间，其中T是栅极沟槽520的深度。轻掺杂区540的深度d在0.25D至0.5D之间。源极区550的深度在0.25d至0.5d之间。
参见图5K，进行另一个刻蚀工艺，通过刻蚀本体区530中的源极接触开口，形成源极接触沟槽570。作为示例，但不作为局限，接触沟槽570的宽度在0.5μm至1.5μm范围内。在电介质层560上方放置一个金属层580。通过用导电材料填充接触开口，在每个源极接触沟槽570中，形成一个源极接头572。金属层580和源极接头572互连所有的源极区，形成沟槽MOSFET器件300，带有MOS晶体管并联。
尽管本发明关于某些较佳的版本已经做了详细的叙述，但是仍可能存在其他版本。因此，本发明的范围不应由上述说明决定，与之相反，本发明的范围应参照所附的权利要求书及其全部等效内容。任何可选件(无论首选与否)，都可与其他任何可选件(无论首选与否)组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能，否则所附的权利要求书并不应认为是意义和功能的局限。权利要求书中没有进行特定功能的精确指明“意义是”的任何项目，都不应理解为美国§112,6中35所述的“意义”或“步骤”。

Claims (20)

1.一种沟槽金属-氧化物-半导体场效应晶体管(MOSFET)器件，包括：
a)一个第一导电类型的衬底，衬底包括一个第一导电类型的外延层，位于相同导电类型的重掺杂硅晶圆上方；
b)一个第二导电类型的本体区，形成在衬底的上方，第二导电类型与第一导电类型相反；
c)一个栅极沟槽，形成在本体区和衬底中，其中栅极沟槽内衬电介质层，一个栅极电极形成在栅极沟槽中；
d)一个轻掺杂源极区和一个重掺杂源极区，形成在本体区中，其中轻掺杂源极区延伸到本体区中比重掺杂源极区更深处；以及
e)一个延伸到本体区的源极接头，形成在栅极沟槽附近的源极接触沟槽中，其中轻掺杂源极区在源极接触沟槽附近，其中肖特基二极管形成在源极接头和轻掺杂源极区之间的接头处。
2.权利要求1所述的器件，其中轻掺杂源极区完全延伸到栅极沟槽和源极接触沟槽之间。
3.权利要求1所述的器件，其中重掺杂源极区仅部分延伸到栅极沟槽和源极接触沟槽之间。
4.权利要求1所述的器件，其中镇流电阻器形成在重掺杂源极区和本体区之间的轻掺杂源极区处。
5.权利要求4所述的器件，其中镇流电阻器具有长度，其中通过改变重掺杂源极区的深度，可以调节镇流电阻器的长度。
6.权利要求4所述的器件，其中镇流电阻器具有一个宽度，其中镇流电阻器的宽度可以通过源极接触沟槽的宽度调节。
7.权利要求4所述的器件，其中镇流电阻器具有电阻值，其中电阻值可以通过轻掺杂源极区的掺杂浓度调节。
8.权利要求1所述的器件，其中本体区的深度D在0.5T至0.8T之间，其中T是栅极沟槽的深度；其中轻掺杂源极区的深度d在0.25D至0.5D之间；并且其中重掺杂源极区的深度在0.25d至0.5d之间。
9.权利要求1所述的器件，其中源极接触沟槽具有一个宽度，其中间距在0.5μm至1.5μm范围内。
10.权利要求1所述的器件，其中轻掺杂源极区的掺杂浓度在1×1015/cm3至1×1018/cm3之间，重掺杂源极区的掺杂浓度在8×1019/cm3至8×1020/cm3之间。
11.一种制备沟槽MOSFET器件的方法，包括：
a)提供一个第一导电类型的衬底，其中衬底包括一个第一导电类型的外延层，位于相同导电类型的重掺杂硅晶圆上方；
b)在衬底中，制备一个栅极沟槽，其中栅极沟槽内衬一个电介质层，以及一个栅极电极形成在栅极沟槽中；
c)在衬底中，制备一个第二导电类型的本体区，其中第二导电类型与第一导电类型相反，
d)通过源极注入，在本体区中，制备一个轻掺杂源极区和一个重掺杂源极区，其中轻掺杂源极区延伸到本体区中比重掺杂源极区更深处；
e)在衬底上方，通过低温氧化工艺，制备一个电介质层；并且
f)制备一个源极接触沟槽，延伸到本体区，其中源极接头形成在源极接触沟槽中，其中轻掺杂源极区在源极接触沟槽附近。
12.权利要求11所述的方法，其中源极注入包括一个深源极注入和一个浅源极注入的组合，其中深源极注入以及浅源极注入的掺杂离子与衬底的掺杂离子导电类型相同。
13.权利要求12所述的方法，其中用于深源极注入的掺杂离子为磷离子，用于浅源极注入的掺杂离子为砷离子。
14.权利要求12述的方法，其中深源极注入和浅源极注入发生在形成本体区之后，以及形成电介质层之前。
15.权利要求12所述的方法，其中深源极注入发生在制备本体区之后，以及制备电介质层之前，浅源极注入发生在形成电介质层之后。
16.权利要求11所述的方法，其中肖特基二极管形成在源极接头和轻掺杂源极区之间的接头处。
17.权利要求11所述的方法，其中轻掺杂源极区完全延伸在栅极沟槽和源极接触沟槽之间。
18.权利要求11所述的方法，其中重掺杂源极区仅部分延伸到栅极沟槽和源极接触沟槽之间。
19.权利要求11所述的方法，其中本体区的深度D在0.5T至0.8T之间，其中T是栅极沟槽的深度；其中轻掺杂源极区的深度d在0.25D至0.5D之间；并且其中重掺杂源极区的深度在0.25d至0.5d之间。
20.权利要求11所述的方法，其中轻掺杂源极区的掺杂浓度在1×1015/cm3至1×1018/cm3范围内，重掺杂源极区的掺杂浓度在8×1019/cm3至8×1020/cm3范围内。
CN201810312715.9A 2017-04-26 2018-04-09 紧凑源极镇流器mosfet及其制备方法 Pending CN108807539A (zh)

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